{"paper":{"title":"JANUS: an FPGA-based System for High Performance Scientific Computing","license":"","headline":"","cross_cats":[],"primary_cat":"cs.AR","authors_text":"A. Cruz, A. Gordillo, A. Maiorano, A. Mu\\~noz-Sudupe, A. Taranc\\'on, D. Navarro, D. Sciretti, E. Marinari, F. Belletti, F. Mantovani, G. Parisi, J. J. Ruiz-Lorenzo, J. L. Velasco, L. A. Fern\\'andez, M. Cotallo, M. Guidetti, M. Rossi, R. Tripiccione, S. F. Schifano, S. P\\'erez-Gaviro, V. Mart\\'in-Mayor","submitted_at":"2007-10-18T15:26:32Z","abstract_excerpt":"This paper describes JANUS, a modular massively parallel and reconfigurable FPGA-based computing system. Each JANUS module has a computational core and a host. The computational core is a 4x4 array of FPGA-based processing elements with nearest-neighbor data links. Processors are also directly connected to an I/O node attached to the JANUS host, a conventional PC. JANUS is tailored for, but not limited to, the requirements of a class of hard scientific applications characterized by regular code structure, unconventional data manipulation instructions and not too large data-base size. We discus"},"claims":{"count":0,"items":[],"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"source":{"id":"0710.3535","kind":"arxiv","version":2},"verdict":{"id":null,"model_set":{},"created_at":null,"strongest_claim":"","one_line_summary":"","pipeline_version":null,"weakest_assumption":"","pith_extraction_headline":""},"references":{"count":0,"sample":[],"resolved_work":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57","internal_anchors":0},"formal_canon":{"evidence_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"author_claims":{"count":0,"strong_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"builder_version":"pith-number-builder-2026-05-17-v1"}