{"id":"4b10879c-dbb2-4413-8602-1fb2209b0db6","arxiv_id":"2411.09546","paper_version":1,"verdict":"REJECT","confidence":"MODERATE","novelty_score":4.0,"correctness_risk":"high","formal_verification":"none","parameter_count":4,"one_line_summary":"The paper presents a design-space exploration tool for resonant SRAM compute-in-memory and claims 80.9% average energy savings, but the detailed results report much smaller and conflicting savings.","lead":"This paper presents an automated tool that maps combinational logic circuits onto resonant SRAM compute-in-memory arrays, choosing among macro topologies and synthesis recipes. The tool is potentially useful, but the headline 80.9% energy-saving figure does not match the detailed results in the body.","discovery_kind":"extension","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The 80.9% average energy-savings claim is not supported by the paper's own numbers: Section IV-B implies ~30% for six-macro, the conclusion says 40.52%, and Table I's caption says 89.12% using a confounded best-versus-worst comparison.","rationale":"The reader's verdict of REJECT is justified by the internal inconsistency alone. The reader's weakest_assumption (the unvalidated linear scaling energy model) is a legitimate concern, but it is secondary: even granting that model, the reported numbers do not match the claim. The most load-bearing issue is the contradiction between the abstract's 80.9%, the body's implied ~30%, the conclusion's 40.52%, and Table I's 89.12% (with a confounded comparison). This makes the central contribution—an automated tool achieving dramatic energy reduction—unverifiable. The Monte Carlo robustness analysis is a positive element but does not address the mapping tool's energy-optimization claim. Therefore the stress-test does not change the reader's verdict.","tokens_in":22852,"tokens_out":4504,"duration_ms":37211,"concrete_test":"Recompute the average energy reduction from the paper's own data. Use the energy values in Table I for each benchmark: compute the mean reduction of (a) best-case three-macro vs worst-case single-macro, (b) three-macro vs single-macro at matched macro size (e.g., 32KB), (c) six-macro vs single-macro using the Section IV-B percentages, and (d) the abstract's claimed 80.9% scenario. Also extract per-benchmark energy values from Figure 9(c) if available. If none of the computed averages equals 80.9%, and if 40.52% only matches the matched-size three-macro comparison, then the headline claim is contradicted by the paper's own reported data.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central claim is the abstract's statement that the tool reduces energy by 80.9% on average using the six-topology implementation versus a single-macro baseline. The body does not contain this figure. In Section IV-B (Figure 9(c)), the authors report that three-macro implementations use 39% lower energy than single-macro implementations, and six-macro implementations use 15% higher energy than three-macro implementations. That implies six-macro is roughly 30% lower energy than single-macro, not 80.9%. The conclusion instead reports 40.52% average savings for the three-macro topology compared with a single-macro implementation at the same macro size. The Table I caption claims an average 89.12% energy saving, but that comparison uses best-case 32KB three-macro configurations against worst-case 4KB single-macro configurations, confounding topology with memory size. Furthermore, if six-macro implementations consume 15% more energy than three-macro, the tool's energy optimization would never select six-macro over three-macro, so the abstract's 'six-topology implementation' is inconsistent with the reported energy ordering. The paper also does not provide the energy equations or raw per-benchmark data needed to reconcile these numbers. The only internally consistent statement is the 40.52% figure in the conclusion, which contradicts the abstract. Thus the central quantitative claim is unsupported by the manuscript's own reported results.","agreement_with_reader":"disagree"},"referee_report":{"model":"deepseek-v4-flash","summary":"This paper presents an architectural exploration tool that maps combinational RTL onto a resonant SRAM compute-in-memory (rCiM) architecture. The rCiM macro uses a 10T dual-read-port bitcell to perform NAND2/NOR2/NOT operations, a single-ended sense amplifier, and a series-resonant inductor write driver for energy recycling. The tool generates 64 AIG variants per benchmark via ABC/YOSYS synthesis transformations, evaluates them across 12 SRAM topologies (single-, three-, and six-macro configurations at sizes from 4KB to 192KB), and selects an energy/latency-optimal configuration for nine EPFL benchmark circuits in TSMC 28nm. The abstract claims an average 80.9% energy saving for the six-topology implementation over a single-macro baseline; the body instead reports three-macro implementations at 39% lower energy than single-macro and six-macro at 15% higher energy than three-macro, while the conclusion reports 40.52% and Table I reports 89.12% for best-case versus worst-case. The paper also provides transient simulations and 5000-sample Monte-Carlo analyses of the NAND2/NOR2 sensing operation, plus comparisons of throughput and energy efficiency with prior CiM macros.","tokens_in":23056,"tokens_out":9272,"duration_ms":84833,"significance":"If the energy-saving claims were consistent and the underlying energy model were validated, this would be a useful design-space exploration tool for SRAM-based CiM, combining synthesis-level AIG transformations with macro-level characterization. The paper's strengths are the breadth of the exploration (6912 implementations across 12 topologies and nine benchmarks), the detailed Monte-Carlo variation data for the sensing path, and the integration of established open-source synthesis tools with a custom characterization flow. However, the core quantitative contribution is currently not reliable: the headline savings figure in the abstract is not supported by the body, the reported savings figures are mutually inconsistent, and the analytical energy model used to produce them is not documented or validated. The significance of the contribution is therefore contingent on a substantial revision that reconciles the numbers and makes the energy-accounting layer reproducible.","major_comments":[{"comment":"The headline claim of an average 80.9% energy reduction with the six-topology implementation is not present in the body and is contradicted by the paper's own numbers. Section IV-B and Figure 9(c) state that three-macro implementations use 39% lower energy than single-macro implementations and that six-macro implementations use 15% higher energy than three-macro implementations, which implies roughly 30% savings for six-macro versus single-macro. The Conclusion reports 40.52% for three-macro versus single-macro at the same macro size, and the Table I caption reports 89.12% for best-case versus worst-case. These figures cannot all be correct, and because six-macro is reported as more energy-hungry than three-macro, the abstract's 'six-topology implementation' is inconsistent with an energy-minimizing tool selecting the best topology. Please reconcile all reported savings, define the exact comparison (same macro size, same synthesis transformations, same total memory footprint), and provide per-benchmark energy data.","section":"Abstract, Section IV-B, Conclusion, Table I"},{"comment":"The energy and latency evaluation is an undocumented analytical model. The text asserts that power is identical for single- and three-macro implementations because the total number of operations is constant, that six-macro power is double three-macro power because power per cycle doubles while the cycle count is unchanged, and implicitly that latency equals the number of AIG levels times the cycle time. No closed-form energy equations are given, no scaling rules for characterized per-operation power/latency values are specified, and the model is not validated against full-array SPICE or post-layout simulations. Since all savings in Figure 9 and Table I are computed through this evaluation step, the central energy results are not independently verifiable as reported.","section":"Algorithm I (lines 10-13) and Section IV-B"},{"comment":"The 89.12% average saving stated in the Table I caption is a best-case-versus-worst-case comparison that confounds three variables: macro count, macro size, and synthesis transformation. Every best-case row is a three-macro configuration with 16KB or 32KB SRAM, while every worst-case row is a single-macro 4KB implementation, and the synthesis recipes differ as well. This does not isolate the effect of the multi-macro topology. Please replace this with an apples-to-apples comparison that varies only the macro count while holding macro size and synthesis transformation fixed, or explicitly decompose the contributions of topology, size, and synthesis recipe.","section":"Table I"},{"comment":"The resonant write driver and the rCiM macro are adopted from references [51], [52], and [58], but the manuscript does not include an independent comparison of the resonant write-back path against a conventional write driver in the same 28nm implementation. The per-operation energy figures in Section IV-D (65 fJ per NAND2 and 116 fJ per NOR2) and the energy-efficiency comparisons in Table II therefore do not isolate the contribution of the series-resonant energy recycling that is presented as a main contribution. A direct simulation or measurement of write energy with and without the resonant driver would establish the claimed benefit.","section":"Section II and Section IV-D"}],"minor_comments":[{"comment":"The manuscript misspells 'von Neumann' as 'V on Neumann' in the Abstract, Section I, and Figure 1; please correct this across the text.","section":"Throughout"},{"comment":"The terminology 'six-topology implementation' in the abstract is not used in the body, which refers to 'six-macro' topologies; please define precisely which of the 12 topologies are single-, three-, and six-macro and use consistent names throughout.","section":"Abstract and Section IV-B"},{"comment":"Table II is difficult to read because several cells contain multiple unlabeled values, and the normalization of throughput to an 8KB array and the process scaling via Dennard's law are not described in sufficient detail to reproduce the comparison.","section":"Table II"},{"comment":"The Monte-Carlo analysis covers the NAND2/NOR2 sensing path but not the resonant write driver, pulse generator, or sense-amplifier offset; a sentence clarifying the scope of the variation analysis would prevent overgeneralization.","section":"Section IV-C"},{"comment":"The heuristic that the memory size must be at least four times the gate count (2 inputs plus 2 outputs per gate) is asserted without derivation; please justify it or provide a sensitivity analysis.","section":"Algorithm I, line 9"},{"comment":"There are missing cross-references and typos: the text refers to 'Figur. 8' and 'Algorithm' without a number, and the acronym 'rCIM' appears in Algorithm I while 'rCiM' is used elsewhere.","section":"Section III-D"}],"recommendation":"major_revision","confidential_remarks":"The central issue for the editor is that the paper's headline quantitative claim is internally inconsistent: the abstract's 80.9%, Section IV-B's implied 30%, the conclusion's 40.52%, and Table I's 89.12% cannot all be correct. This is not a stylistic concern but a load-bearing problem for the paper's main contribution. The circuit-level Monte-Carlo work is solid, so I would not reject outright; however, the authors must reconcile all reported savings with a single controlled comparison and provide the analytical energy model and its validation before the manuscript can be considered reliable."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Quick read: the actual contribution here is the mapping/exploration flow — 64 AIG synthesis variants from ABC times 12 SRAM macro topologies, evaluated across EPFL benchmarks — and that part is genuinely new relative to the authors' earlier rCiM macro papers. The circuit-level Monte Carlo work on NAND2/NOR2 sensing margins is careful and internally consistent; the numbers in Figures 10–12 support the claim that the 10T cell plus SA can distinguish the input cases. So there is a real tool story underneath.\n\nThe problem is the central energy-saving claim, and the stress test is right. The abstract says 80.9% average reduction for the six-topology implementation, but Section IV-B reports three-macro at 39% lower energy than single-macro and six-macro at 15% higher energy than three-macro, which puts six-macro around 30% below single, not 80.9%. The conclusion says 40.52% for three-macro versus single at the same macro size. Table I's caption claims 89.12% but uses best-case 32KB three-macro against worst-case 4KB single-macro, which confounds topology with memory size. These numbers cannot all be right, and nothing in the paper reconciles them. That is a load-bearing inconsistency because the headline is the tool's value proposition.\n\nThe second soft spot is the energy model. The algorithm evaluates power/latency/energy analytically from characterized per-operation values, with latency equated to AIG level count times cycle time and constant control overhead assumed. No closed-form energy equations are given, and the linear scaling is not validated against full-array simulation. With no code or data released, an independent check is impossible.\n\nI don't think this is a dishonest paper. The self-citation to [51]–[58] for the resonant driver is legitimate — that is their own prior work and the new thing here is the exploration flow, not the device. But the paper as submitted cannot be accepted with the headline number unsupported by its own body.\n\nThis deserves a serious referee: the toolflow is a plausible subfield contribution and the circuit simulation is real, so a referee can force the cleanup. My call is to send it to review but require major revision: reconcile the energy figures, specify the energy model, and ideally release code and per-benchmark data. For CiM/EDA readers, this is a useful data point once the numbers are straightened out.","headline":"A plausible new exploration flow over AIG transforms and SRAM topologies, undermined by an internally inconsistent headline energy-savings figure that the paper never reconciles.","tokens_in":23732,"tokens_out":1963,"would_cite":false,"duration_ms":19518,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"An automated tool maps combinational logic onto resonant SRAM compute-in-memory arrays and selects the most energy-efficient macro topology, reporting average savings of 80.9% over a single-macro baseline.","keywords":["compute-in-memory","SRAM","resonant energy recycling","architectural exploration","logic synthesis","AIG","10T bitcell","energy optimization"],"falsifier":"Run a full post-layout simulation of one benchmark (for example, the adder) on a single-macro and a three-macro configuration at the same macro size and compare measured energy against the tool's estimate; if the three-macro configuration is not the lower-energy one, the linear-scaling model fails.","tokens_in":22511,"feed_emoji":"⚡","tokens_out":9132,"duration_ms":75759,"temperature":0.7,"pith_summary":"This paper tries to establish that a design tool can automatically pick the most energy-efficient SRAM compute-in-memory (CiM) configuration for a given combinational logic circuit, and that splitting one large memory macro into several smaller macros that execute NAND, NOR, and NOT operations in parallel saves energy and latency. The tool synthesizes many logic-graph variants of the circuit, maps each onto up to twelve SRAM macro topologies, estimates power and latency from characterized per-operation data, and returns the lowest-energy option along with a resonant-inductor size. The paper reports substantial average energy reductions for multi-macro over single-macro implementations across nine benchmark circuits, with the abstract's headline figure being an 80.9% average reduction for the six-topology configuration. A sympathetic reader would care because this is a concrete step toward closing the design-automation gap that has slowed adoption of in-memory computing.","feed_headline":"80.9% energy cut: tool picks best SRAM macro split for in-memory logic","feed_subtitle":"An exploration of 6,900+ mappings finds parallel NAND/NOR/NOT macros that lower energy and latency.","key_machinery":"The load-bearing pieces are a 10-transistor SRAM bitcell with a dedicated dual read port (so two operands can be accessed without read disturb), a resonant write driver that recycles bitline discharge energy through a series inductor, and an exploration loop that combines the ABC logic synthesizer's AIG transformations with a linear energy and latency model. The evaluation model characterizes power and latency from post-layout simulations for each operation type and macro size, then scales them linearly by the number of operations and logic levels, with the inductor size chosen to match the macro's bitline capacitance. This machinery turns the architectural question of how many macros of what size into a finite search over 6,912 implementation strategies.","core_discovery":"The central claim is that a given combinational circuit's best implementation in the resonant compute-in-memory (rCiM) architecture can be found automatically rather than by manual architectural choice. The tool enumerates 64 and-inverter-graph (AIG) variants produced by ordered combinations of four logic-synthesis transformations, evaluates each against twelve SRAM topologies (macro sizes 4 KB to 192 KB, with one, three, or six macros), and selects the configuration with the lowest estimated energy along with the resonant-inductor value. The paper argues that splitting a large macro into three parallel macros, each dedicated to NAND2, NOR2, or NOT, cuts energy by about 39% on average relative to a single macro because the same number of operations finishes in fewer cycles, and that the six-macro configuration trades higher power for further latency reduction (66% lower than single-macro latency) at an energy cost 15% above the three-macro case. The abstract's headline figure is an 80.9% average energy reduction for the six-topology implementation over a single-macro baseline across cache sizes from 4 KB to 192 KB.","pith_inferences":["The same search methodology could be applied to other CiM cell types (for example, 6T or 8T with different logic primitives) by swapping the characterization data, making the exploration flow a general template rather than a one-off.","The linear scaling of power with operation count ignores potential overheads from address decoding and control that grow with macro count, so the reported savings may be optimistic for very small or very large macro counts.","The tradeoff between three and six macros suggests a sweet spot that depends on the circuit's ratio of logic levels to operations; the tool could be used to classify circuits as latency-bound or energy-bound and tune synthesis accordingly.","If energy recycling is as effective as simulated, the rCiM approach could lower the barrier to embedding boolean computation in last-level caches, where write energy is currently a blocker."],"forward_implications":["If the tool's energy estimates are accurate, circuit designers could hand a Verilog description to the tool and receive a memory-macro size, macro count, and inductor value without manual architectural exploration.","Multi-macro execution of NAND2/NOR2/NOT operations would let the same SRAM array serve as a programmable logic block, not just a store, cutting latency for combinational workloads.","Energy recycling through the resonant write driver would make the writeback cycle nearly free in energy, which is the operation that dominates CiM cost.","The tool's linear scaling model, if validated, would let the search extend to larger macro counts and memory sizes without re-characterizing every configuration.","Choosing among AIG variants with different levels and gate counts gives a new joint optimization knob: logic synthesis and memory topology can be co-optimized."],"supporting_citations":[{"why":"Supplies the ABC logic synthesizer and the four AIG sub-graph optimizations (balance, refactor, rewrite, resubstitution) that generate the 64 circuit variants.","marker":"[37]"},{"why":"YOSYS generates the gate-level netlists from RTL that feed the AIG creation and simulation flow.","marker":"[38]"},{"why":"Provides the nine combinational benchmark circuits used to evaluate the 6,912 implementation strategies.","marker":"[39]"},{"why":"Introduces the resonant energy-recycling SRAM design whose series-inductor write driver is the core of the rCiM power savings.","marker":"[51]"},{"why":"Prior rCiM 10T SRAM macro work that establishes the bitcell, the in-memory NAND2/NOR2/NOT scheme, and the writeback path this tool builds on.","marker":"[58]"},{"why":"The compute-SRAM baseline whose throughput and energy efficiency are compared against the proposed rCiM in the architecture-comparison table.","marker":"[22]"},{"why":"A bit-parallel 6T SRAM compute-in-memory baseline used to quantify the proposed architecture's energy-efficiency advantage.","marker":"[64]"}],"fun_headline_variants":["Tool explores 6900+ SRAM layouts for 80.9% energy savings","Automated SRAM splitter cuts energy 80.9% in-memory logic","rCiM tool auto-selects topology for 80.9% energy cut","Exploring 6900+ SRAM designs: tool finds 80.9% energy win"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The tool's energy and latency numbers assume that power per operation is constant and that total latency is simply the number of logic levels times a fixed cycle time, with no extra control or routing overhead when the number of macros grows.","fun_headline_variants_meta":{"raw":{"variants":["Tool explores 6900+ SRAM layouts for 80.9% energy savings","Automated SRAM splitter cuts energy 80.9% in-memory logic","rCiM tool auto-selects topology for 80.9% energy cut","Exploring 6900+ SRAM designs: tool finds 80.9% energy win"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000899,"raw_usage":{"total_tokens":3932,"prompt_tokens":1066,"completion_tokens":2866,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":682,"completion_tokens_details":{"reasoning_tokens":2775}},"tokens_in":682,"tokens_out":2866,"duration_ms":19067,"temperature":1.0,"reasoning_tokens":2775,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-12T20:32:45.818430+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Run a full post-layout simulation of one benchmark (for example, the adder) on a single-macro and a three-macro configuration at the same macro size and compare measured energy against the tool's estimate; if the three-macro configuration is not the lower-energy one, the linear-scaling model fails.","supporting_citations":[{"cited_title":"ABC: An academic industrial-strength verification tool,","cited_arxiv_id":null,"evidence_quote":"Supplies the ABC logic synthesizer and the four AIG sub-graph optimizations (balance, refactor, rewrite, resubstitution) that generate the 64 circuit variants."},{"cited_title":"The EPFL combi- national benchmark suite,","cited_arxiv_id":null,"evidence_quote":"Provides the nine combinational benchmark circuits used to evaluate the 6,912 implementation strategies."},{"cited_title":"Resonant Energy Recycling SRAM Architecture,","cited_arxiv_id":null,"evidence_quote":"Introduces the resonant energy-recycling SRAM design whose series-inductor write driver is the core of the rCiM power savings."},{"cited_title":"Resonant Compute- In-Memory (rCIM) 10T SRAM Macro for Boolean Logic,","cited_arxiv_id":null,"evidence_quote":"Prior rCiM 10T SRAM macro work that establishes the bitcell, the in-memory NAND2/NOR2/NOT scheme, and the writeback path this tool builds on."},{"cited_title":"14.2 A Compute SRAM with Bit-Serial Integer/Floating- Point Operations for Programmable In-Memory Vector Acceleration,","cited_arxiv_id":null,"evidence_quote":"The compute-SRAM baseline whose throughput and energy efficiency are compared against the proposed rCiM in the architecture-comparison table."},{"cited_title":"Bit parallel 6t sram in-memory computing with reconfigurable bit-precision,","cited_arxiv_id":null,"evidence_quote":"A bit-parallel 6T SRAM compute-in-memory baseline used to quantify the proposed architecture's energy-efficiency advantage."}],"review_version":1}