{"id":"6c6afc9b-ba4e-4e5a-84b5-528936758a28","arxiv_id":"2411.13882","paper_version":3,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":2,"one_line_summary":"A 2x2 array of silicon MOS quantum dots demonstrates voltage-tunable tunnel coupling between every neighboring pair at 4.2 K.","lead":"This paper reports a 2x2 grid of quantum dots in a silicon chip, with a gate between each pair of neighboring dots that can tune how strongly electrons hop between them. If the result holds up, it is an early step toward two-dimensional silicon quantum processors that could be made in standard chip factories.","discovery_kind":"new_application","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The central claim of tunable tunnel coupling for all nearest-neighbor pairs is not fully supported: no tunnel-rate data are reported for the P1–P2 pair (J12), and the 30 dec/V figure is measured only on J23.","rationale":"The reader's named weakest assumption is Eq. (B1), the conversion from measured tunnel control rates to predicted exchange control rates. That is a legitimate concern for the exchange estimates, but it is not the most load-bearing issue for the paper's central measured claim. The central claim requires demonstrating tunable tunnel coupling for every nearest-neighbor pair. The paper directly measures tunnel-rate control for only three of the four pairs; J12 is missing. The reader's rationale does mention the absence of J12 tunnel-rate data and the overstatement of the 30 dec/V figure, so there is partial agreement, but the reader did not elevate this to the weakest assumption. My assessment does not change the overall verdict: the device demonstration is credible and valuable, but the abstract and claims overstate the evidence. A conditional acceptance requiring the J12 data (or an explicit claim limitation) is appropriate, which matches the reader's existing conditional verdict.","tokens_in":14279,"tokens_out":3519,"duration_ms":36234,"concrete_test":"Check the Supplementary Information and raw measurement files for a J12 tunnel-rate frequency sweep along the P1–P2 transition line, analogous to the J34 data in Fig. 3(c). If no such measurement exists, the abstract and conclusion must be weakened from 'all nearest-neighbor tunnel couplings' to 'three of the four nearest-neighbor pairs,' and the '30 decades per volt' must be explicitly attributed to the J23 control rate rather than to the array as a whole. Optionally, re-measure J12 on a nominally identical device to fill the gap.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The paper's central claim, stated in the abstract and introduction, is that the device has 'tunable interdot coupling between all adjacent dots' and 'control of all nearest-neighbor tunnel couplings spanning up to 30 decades per volt.' Section IV reports pairwise tunnel-rate measurements for J23 (30.2±4.9 dec/V), J34 (10.4±0.7 dec/V), and J41 (2.5±0.2 dec/V), but no tunnel-rate data for J12. The text explicitly says 'we repeat the same measurement on J23, J34 and J41,' omitting J12. The only evidence for P1–P2 coupling control is the charge stability diagram in Fig. 2(a), which shows that the visibility of charge transitions changes with VJ12; this establishes qualitative tunability but not a quantitative tunnel-coupling control rate. Therefore, the 'all nearest-neighbor' claim rests on an unmeasured fourth pair. The '30 decades per volt' is a single-pair maximum, not an array-wide property. This concern is distinct from the Eq. (B1) exchange-conversion approximation: that issue affects the predicted exchange control rates, whereas the missing J12 data directly undermine the measured tunnel-coupling claim that is the paper's headline result. If J12 cannot be measured or its control rate is much lower than the others, the central claim fails as stated.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"This paper reports a 2×2 silicon metal-oxide-semiconductor (MOS) quantum dot array in which each nearest-neighbor pair is coupled through an interstitial exchange (J) gate, defined in a four-layer aluminum gate stack. At 4.2 K the authors demonstrate isolated-mode double-dot charge stability diagrams for all four pairs and triple-dot configurations for all four triples. Gate-pulsed lock-in measurements of interdot tunnel rates yield exponential control slopes of 30.2±4.9 dec/V for J23, 10.4±0.7 dec/V for J34, and 2.5±0.2 dec/V for J41; no quantitative tunnel-rate data are reported for the fourth pair (J12). Using the relation dlog10(J)/dV_J ≈ 2 dlog10(t)/dV_J (Appendix B), the authors estimate exchange control rates of 60, 21, and 5 dec/V, and conclude that only the J41 pair falls below the ~8 dec/V controllability benchmark. The manuscript claims this is the first silicon MOS 2D array with demonstrated tunable tunnel coupling between all adjacent dot pairs.","tokens_in":14563,"tokens_out":24842,"duration_ms":227698,"significance":"The device itself is a real advance with strong supporting evidence: clean few-electron stability diagrams for every adjacent pair, four different triple-dot configurations, three quantitative tunnel-rate control curves with a coherent and well-explained layer-dependent hierarchy (J23 > J34 > J41), a fabrication-aware simulation pipeline, and falsifiable quantitative predictions (exchange control rates of 5, 21, and 60 dec/V; only J41 below the 8 dec/V threshold) that can be tested at millikelvin temperatures. The authors also deserve credit for disclosing the limitations of their own evidence, including the qualitative-only agreement of the simulations and the model dependence of Eq. (B1). The weakness of the paper is that its headline claims overstate that evidence: the title and abstract assert fully tunable coupling for all pairs and 'up to 30 decades per volt,' while the data support quantitative control rates for only three of the four pairs, with the maximum realized on a single gate. Those calibration issues are fixable by adding the J12 dataset or rewording the claims, and I do not see a defect in the core device demonstration.","major_comments":[{"comment":"The paper's central claim is supported by quantitative data for only three of the four nearest-neighbor pairs. Section IV states 'We repeat the same measurement on J23, J34 and J41' and Fig. 3(d) shows fitted tunnel-rate control slopes for exactly these three gates (30.2±4.9, 10.4±0.7, and 2.5±0.2 dec/V); no tunnel-rate data are presented for J12. For P1–P2, Fig. 2(a) offers only qualitative evidence: the charge-transition visibility decreases as VJ12 is reduced, and for VJ12 > 1 V the J12 gate itself forms an unintended dot, so the demonstrated tuning range for that pair is, at best, one-directional. The abstract's claim of 'control of all nearest-neighbor tunnel couplings spanning up to 30 decades per volt' and the title's 'fully tuneable pairwise interdot coupling' therefore exceed the measurements. Note also that the 30 dec/V figure is the single best gate (J23), with the other two measured gates at 10.4 and 2.5 dec/V. The authors should either supply the missing J12 tunnel-rate measurement or revise the title, abstract, and conclusion to state that quantitative tunnel-rate control is demonstrated for three pairs and qualitative tunability (with a J-dot limitation) for the fourth, with measured slopes spanning approximately 2.5–30 dec/V.","section":"Abstract; Section IV; Fig. 3"},{"comment":"The exchange-control predictions (5, 21, 60 dec/V) and the conclusion that only J41 falls below the ~8 dec/V threshold rest on Eq. (B1), dlog10(J)/dV_J ≈ 2 dlog10(t)/dV_J, which is derived from the Hund-Mulliken relation J ≈ 4t²/U. The authors correctly disclose that this estimate 'may break down under strong interaction regimes,' and their path-integral support is admittedly only in qualitative agreement: the simulated tunnel control rates are 'significantly lower than experimental results' (caption of Fig. 7). In light of those self-stated caveats, the claims in Appendix B that tunnel-rate controllability 'can serve as an effective predictor' of exchange controllability, and in the Conclusion that the design ensures 'high-level exchange controllability,' are stated more firmly than the evidence. Please either present the exchange predictions as explicitly conditional on Eq. (B1) holding for this device geometry, or provide a quantitative validation of Eq. (B1) (for example, the same-device tunnel-versus-exchange comparison from Ref. [6]).","section":"Appendix B, Eq. (B1); Section IV"},{"comment":"The measured observable in Fig. 3 is the interdot electron tunnel rate r (y-axis in Hz), but Section IV and Eq. (B1) treat the fitted slopes as control rates of the tunnel coupling t ('tunnel control rates dlog10(t)/dV_J'). These are not the same quantity: for incoherent interdot tunneling the rate scales approximately as r ∝ t² (Fermi's golden rule), so if the prefactor is weakly voltage-dependent over the measured range then dlog10(r)/dV_J ≈ 2 dlog10(t)/dV_J. Under that standard assumption the reported control slopes (30.2, 10.4, 2.5 dec/V) are a factor of two larger than the tunnel-coupling control slopes, and the exchange rates obtained from Eq. (B1) would be 30, 10, and 2.5 dec/V rather than 60, 21, and 5 dec/V (the qualitative 'only J41 below threshold' conclusion would be unchanged). Since the relation between r and t is never stated, please clarify it; if a golden-rule conversion applies, the claims should consistently refer to control of interdot tunnel rates, with the tunnel-coupling and exchange slopes adjusted accordingly.","section":"Section IV (Fig. 3); Appendix B"}],"minor_comments":[{"comment":"The diagonal gate between P1 and P4 is labelled 'J41' in the main text but 'J14' in the supplementary simulation figures; please use one label consistently, particularly since Figs. 3(d) and 7(c)–(d) are directly compared.","section":"Supplementary Figs. 5–7; main text Figs. 1–3"},{"comment":"The stretched-exponential fit ΔID(f) = ID exp[(−f/r)^n] includes a stretch exponent n, but no fitted n values are reported for any of the three datasets; please report n with its uncertainty, since the extracted r depends on n.","section":"Section IV; Fig. 3(c)"},{"comment":"The exchange control rates (5, 21, 60 dec/V) are quoted without uncertainties; propagating the stated tunnel-rate fit errors (0.2, 0.7, 4.9 dec/V) would clarify how robust the threshold conclusion is.","section":"Section IV"},{"comment":"Several figure captions are garbled or duplicated in the manuscript text: the caption of Fig. 5 repeats the caption of Fig. 2, the caption of Fig. 3 contains a stray sentence about sweeping 'J1 and step frequency,' and the captions of Figs. 6–7 contain redundant fragments. These assembly problems should be fixed in revision.","section":"Figure captions; manuscript assembly"},{"comment":"The novelty statement that 'none have yet demonstrated tunnel coupling control between all quantum dot pairs' in silicon MOS should be verified against the most recent literature, including the 2024/2025 works already cited by the authors (Refs. [19,44,45]); if any of those report interdot coupling control in MOS or compatible arrays, the claim needs qualification.","section":"Introduction; Refs. [19,44,45]"}],"recommendation":"major_revision","confidential_remarks":"The manuscript is genuinely promising and the core device demonstration is sound; my recommendation of major revision is driven by the mismatch between the headline claims and the available data, which is fixable either by adding the J12 tunnel-rate measurement or by recalibrating the claims. Two further issues to keep in mind: (i) the Introduction's 'none have yet' novelty claim should be vetted against the 2025 preprints cited as Refs. [44,45] and against Ref. [19], since I cannot rule out overlap from the reference list alone; and (ii) the factor-of-two issue in Major Comment 3 (tunnel rate versus tunnel coupling) changes the headline numbers but not the qualitative conclusions, and a clear statement of the r–t conversion will settle it. The competing-interests disclosure for Diraq is present and does not affect my technical assessment."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"First thing to know: this paper is a genuine engineering step — a 2x2 silicon MOS dot array with interstitial exchange gates in a four-layer stack, showing pairwise charge stability for all four edges and quantitative tunnel-rate control for three of the four gates. That is new for MOS; prior 2D MOS arrays did not show this. The authors also use their path-integral simulations to connect tunnel-rate lever arms to exchange control, which is useful design guidance. The abstract, however, overstates the result. The 'all nearest-neighbor tunnel couplings' claim is supported quantitatively for J23, J34, J41 only; J12 is shown qualitatively via the charge stability diagram but no tunnel-rate curve is reported. The 'up to 30 decades per volt' is a single-gate maximum (J23). That matters for the headline. The stress-test note is correct on this point, and it is not a manufactured flaw: the text explicitly says 'we repeat the same measurement on J23, J34 and J41,' omitting J12.\n\nThe exchange-rate conversion via Eq. B1 is an approximation (J ≈ 4t^2/U). The authors support it with their own simulations and prior experimental work; it is not circular, but it is model-based. The predicted 5, 21, 60 dec/V exchange rates carry no error bars, and the conclusion that only J41 falls below threshold depends on that approximation. That is a real limitation, though a moderate one.\n\nThe writing is clear, the figures are informative, and the authors are honest about J-dot formation and the SET sensitivity issues. They also note that simulations underestimate the measured tunnel control rates, which is candid. Missing: J12 rate data, error propagation, and a proper data/code release (the 'available upon reasonable request' boilerplate is weak). These are fixable in revision. If the authors either measure J12 or explicitly state that the all-pair claim is qualitative for that edge, and if they add uncertainty estimates for the exchange rates, the paper would be solid. As it stands, the core device demonstration is credible and valuable, but the abstract needs to be reined in.\n\nI'd send this to a serious referee. It is a worthwhile device paper for the spin-qubit community, and the missing J12 point is exactly the kind of thing a referee should catch. For my own reading group, I'd probably mention it as an example of how device papers live and die by their claims.","headline":"A real 2x2 MOS dot array with interstitial gates, but the abstract oversells the tunnel-control claim: J12 is qualitative, and the 30 dec/V figure is one gate only.","tokens_in":15161,"tokens_out":2427,"would_cite":true,"duration_ms":23002,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":["73.21.La","85.35.Gv","03.67.Lx"],"model":"deepseek-v4-flash","headline":"The paper demonstrates a 2×2 silicon MOS array with voltage-tunable tunnel coupling on every nearest-neighbor pair, up to 30 decades per volt, and predicts all but one pair meet the exchange-control rate needed for spin-qubit gates.","keywords":["silicon","quantum dots","MOS","tunability","tunnel couplings","2D quantum dot array","exchange interaction","spin qubits"],"falsifier":"Cool this exact 2×2 device to millikelvin, form spin qubits in the P2–P3 and P3–P4 pairs, and measure the exchange splitting $J$ as a function of $V_{J23}$ and $V_{J34}$ via coherent two-qubit oscillations; then compare the measured $d\\log_{10}(J)/dV_J$ with twice the tunnel-control rates from Fig. 3(d). If the ratio is not close to 2 across the operating range, the predicted exchange rates (60 and 21 decades per volt) and the screening claim would fail.","tokens_in":14089,"feed_emoji":"⚛️","tokens_out":10509,"duration_ms":59791,"temperature":0.7,"pith_summary":"The paper claims a 2×2 silicon metal-oxide-semiconductor (MOS) quantum dot array in which every neighboring pair of dots has a voltage-tunable tunnel coupling, controlled by a dedicated interstitial exchange gate. This matters because previous silicon MOS 2D dot arrays had not demonstrated tunable coupling across all adjacent pairs, and 2D arrays are a necessary step toward error-correctable surface-code spin qubit processors. At 4.2 K the device forms isolated double-dot and triple-dot configurations in every orientation, and direct tunnel-rate measurements show control rates up to 30 decades per volt, with lower rates for gates placed in higher metal layers. The paper further argues that tunnel-rate controllability measured at 4 K predicts exchange controllability, allowing devices to be screened for two-qubit gate suitability without millikelvin spin measurements.","feed_headline":"Silicon 2×2 dot array tunes every neighbor coupling","feed_subtitle":"Demonstrates the gate control needed for two-qubit exchange gates in a 2D silicon spin processor.","key_machinery":"The load-bearing element is the interstitial exchange gate, a narrow electrode placed between two plunger gates that raises or lowers the interdot potential barrier and thereby controls the tunnel coupling $t$. The argument is carried by the four-layer gate stack in which each J-gate sits at a different height (J23 in layer 1, J12/J34 in layer 3, J41 in layer 4), so the measured 30.2/10.4/2.5 decades-per-volt control rates map directly onto gate geometry. The quantitative bridge from tunnel to exchange control is the approximate identity $d\\log_{10}(J)/dV_J \\approx 2\\,d\\log_{10}(t)/dV_J$, which follows from the Hund–Mulliken estimate $J\\approx 4t^2/U$ and is supported here by path-integral simulations and prior experimental data; it converts the 4.2 K tunnel measurements into predicted exchange-control rates without requiring millikelvin spin measurements.","core_discovery":"The paper reports a 2×2 quantum dot array in a silicon MOS gate stack, with four dots formed under plunger gates P1–P4 and one interstitial exchange (J) gate controlling the tunnel barrier between every neighboring pair: J12, J23, J34, and J41. At 4.2 K, charge stability diagrams show well-defined double-dot and triple-dot charge configurations in all four pairwise orientations, demonstrating that each pair can be isolated and operated in the few-electron regime. Direct tunnel-rate measurements give control rates of 30.2±4.9 decades per volt for J23, 10.4±0.7 for J34, and 2.5±0.2 for J41, with J12 sharing the layer-3 geometry of J34; the spread is attributed to the J-gates sitting at different heights and cross-sectional profiles in the four-layer stack. Using the relation $d\\log_{10}(J)/dV_J \\approx 2\\,d\\log_{10}(t)/dV_J$, the paper predicts exchange control rates of about 60, 21, and 5 decades per volt for those gates, concluding that only J41 falls below the roughly 8 decades per volt thought necessary for switching entanglement on and off, and proposing an increased P1–P4 pitch to improve J41.","pith_inferences":["If the 4.2 K tunnel-control screening is adopted, the same measurement could be extended to all four J-gates in future devices as a pass/fail test against the 8 decades-per-volt exchange threshold before spending dilution-refrigerator time.","The systematic loss of tunability for gates in higher metal layers (J41 worst, J23 best) suggests a design rule: place exchange gates as close to the channel as fabrication allows, or increase plunger pitch where high-layer gates are unavoidable; the paper's own simulation points to the pitch lever.","Because the J-gates that form unintended dots at high voltage (J12, J23, J34) define an upper bound on usable exchange bias, an unexplored practical consequence is that the usable tuning window, not just the dec/V slope, will constrain two-qubit gate calibration.","A testable extension of the screening method would be to compare the 4.2 K tunnel-rate prediction against direct exchange spectroscopy from coherent two-qubit gates in the same 2×2 device, which the paper did not perform."],"forward_implications":["A 2×2 silicon MOS dot array can be operated in the few-electron regime in every nearest-neighbor pair, with both double-dot and triple-dot configurations formed and isolated at 4.2 K.","The interstitial gate J23, placed in the lowest metal layer with the widest geometry, tunes the P2–P3 tunnel coupling at 30.2±4.9 decades per volt, the strongest control demonstrated.","Tunnel control rates of 10.4 and 2.5 decades per volt for J34 and J41 imply exchange control rates of about 21 and 5 decades per volt, so only J41 falls below the roughly 8 decades per volt threshold regarded as needed for reliable entanglement switching.","Measuring tunnel-rate controllability at 4.2 K can predict whether a device meets exchange controllability requirements without dilution refrigeration.","Charge sensing visibility is highest for dot pairs perpendicular to the SET current axis, which guides where the charge sensor should be placed relative to the array."],"supporting_citations":[{"why":"Prior measurement of both tunnel and exchange rates in the same silicon MOS device, used to argue that Eq. (B1) holds beyond the simple Hund–Mulliken regime.","marker":"[6]"},{"why":"Supplies the Hund–Mulliken estimate $J\\approx 4t^2/U$ from which the exchange/tunnel control-rate relation is derived.","marker":"[30]"},{"why":"Provides the roughly 8 decades-per-volt exchange-control threshold and the path-integral simulation benchmarked against spin-qubit variability bounds.","marker":"[37]"},{"why":"Provides the path-integral method used to simulate tunnel and exchange couplings for the four-dot system and to support Eq. (B1).","marker":"[40]"},{"why":"Gate-pulsed lock-in charge-sensing technique used to record charge transitions and extract tunnel rates.","marker":"[38]"},{"why":"Establishes the isolated-mode operation used here to form and measure double- and triple-dot configurations.","marker":"[39]"},{"why":"Earlier silicon CMOS 2×2 dot array with integrated charge sensing that did not demonstrate tunnel-coupling control between all pairs, serving as the baseline this work extends.","marker":"[31]"}],"fun_headline_variants":["2x2 silicon dot array tunes all four neighbor links","Silicon 2x2 qubit array: full pairwise coupling control","2D silicon dot array with every pairwise link tunable","Quad silicon dot array: all pair couplings adjustable","Silicon 2x2 dot array: exchange gates tune every link"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The argument's load-bearing assumption is that a change in exchange-gate voltage moves the exchange interaction between two dots about exactly twice as fast as it moves the tunnel coupling, a relation that comes from a simple model and is supported here by previous experiments and simulations rather than by direct exchange measurements on this device.","fun_headline_variants_meta":{"raw":{"variants":["2x2 silicon dot array tunes all four neighbor links","Silicon 2x2 qubit array: full pairwise coupling control","2D silicon dot array with every pairwise link tunable","Quad silicon dot array: all pair couplings adjustable","Silicon 2x2 dot array: exchange gates tune every link"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000759,"raw_usage":{"total_tokens":3396,"prompt_tokens":994,"completion_tokens":2402,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":610,"completion_tokens_details":{"reasoning_tokens":2317}},"tokens_in":610,"tokens_out":2402,"duration_ms":71009,"temperature":1.0,"reasoning_tokens":2317,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-12T15:46:56.232715+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Cool this exact 2×2 device to millikelvin, form spin qubits in the P2–P3 and P3–P4 pairs, and measure the exchange splitting $J$ as a function of $V_{J23}$ and $V_{J34}$ via coherent two-qubit oscillations; then compare the measured $d\\log_{10}(J)/dV_J$ with twice the tunnel-control rates from Fig. 3(d). If the ratio is not close to 2 across the operating range, the predicted exchange rates (60 and 21 decades per volt) and the screening claim would fail.","supporting_citations":[{"cited_title":"Tanttu, W","cited_arxiv_id":null,"evidence_quote":"Prior measurement of both tunnel and exchange rates in the same silicon MOS device, used to argue that Eq. (B1) holds beyond the simple Hund–Mulliken regime."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Provides the roughly 8 decades-per-volt exchange-control threshold and the path-integral simulation benchmarked against spin-qubit variability bounds."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Provides the path-integral method used to simulate tunnel and exchange couplings for the four-dot system and to support Eq. (B1)."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Gate-pulsed lock-in charge-sensing technique used to record charge transitions and extract tunnel rates."},{"cited_title":"Eenink, L","cited_arxiv_id":null,"evidence_quote":"Establishes the isolated-mode operation used here to form and measure double- and triple-dot configurations."},{"cited_title":"Gilbert, A","cited_arxiv_id":null,"evidence_quote":"Earlier silicon CMOS 2×2 dot array with integrated charge sensing that did not demonstrate tunnel-coupling control between all pairs, serving as the baseline this work extends."}],"review_version":1}