{"id":"ce478b50-f10b-4821-8715-f06189321cdc","arxiv_id":"2411.17546","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":5,"one_line_summary":"One reconfigurable inverse-design magnonic device experimentally implements NOT, OR, NOR, AND, NAND and a half-adder at 5.04 GHz by encoding bits in spin-wave amplitude.","lead":"A single reconfigurable chip with 49 current loops was tuned to perform six Boolean logic gates and a half-adder using spin-wave signals instead of electric current. This is a step toward one programmable magnetic device that could handle multiple data-processing tasks without new fabrication.","discovery_kind":"new_application","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Half-adder output C at input 01 sits only 0.11 dB from the 10% logic-0 threshold; a single repeated measurement could flip the bit.","rationale":"The reader's weakest assumption focused on the absence of repeated measurements and error bars as a general concern. I agree with that direction, but the decisive weakness is more specific and more damaging: the half-adder, the flagship result, has a logic-state margin of only 0.11 dB for output C at input '01'. This is not merely a missing error bar; it is a concrete, calculable proximity to the 10% threshold from the paper's own numbers. The contrast ratio of ~9.8 dB is misleading because the gate's correctness is determined by the 90/10 threshold logic, not by the separation between the two output level clusters. The NOR gate has a similar but less extreme issue (1.8 dB margin for its weakest '0' state). These observations reinforce the reader's CONDITIONAL verdict rather than overturning it: the paper should be accepted only after the authors provide repeated measurements or error analysis demonstrating that the half-adder margin is robust. My verdict is therefore UNCHANGED relative to the reader's assessment. I note that the missing AND '10' entry and the unmeasured OR '00' baseline are additional reporting gaps, but the half-adder margin is the single most load-bearing quantitative weakness.","tokens_in":9557,"tokens_out":5028,"duration_ms":48415,"concrete_test":"Re-measure the half-adder for the published optimized current configuration at input state '01' at output C at least 20 times (ideally across power cycles and switch actuations). Compute the mean and standard deviation of S21; if the mean or any substantial fraction of the distribution is above -60.73 dB (the 10% threshold relative to the -50.73 dB reference), the half-adder logic fails. Report the same repeatability for the NOR '11' state, whose margin is only about 1.8 dB.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The half-adder in §II.E is the most complex claimed gate, and its validity is far more fragile than the quoted 9.8 dB contrast suggests. For output C, the optimizer sets the '11' state as the 100% reference at -50.73 dB. The logic-0 criterion is 10% of that maximum, i.e., -60.73 dB. At input state '01', output C is reported as 9.73% transmission, corresponding to -60.84 dB. That is only 0.11 dB below the threshold that separates logic 0 from logic 1. The paper reports a single VNA transmission value per state, with no error bars and no repeated optimization runs. At -60 dB, routine VNA noise, drift, or mechanical-switch reproducibility can easily exceed 0.1 dB, so this margin is not statistically meaningful. A similar but less severe issue affects NOR: the '11' state at 6.6% is about 1.8 dB below the 10% threshold. The central claim—that a functional half-adder was realized—therefore rests on a threshold margin comparable to the measurement uncertainty. The quoted contrast ratios describe output-state separation, but the actual gate correctness is governed by the distance from each output to the 90/10 thresholds, and for the half-adder that distance is razor-thin.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper reports the experimental realization of six logic functions—NOT, OR, NOR, AND, NAND, and a half-adder—on a single reconfigurable inverse-designed magnonic device. The device consists of a 7×7 array of current loops on a YIG film that generate local Oersted fields and scatter spin waves; logic states are encoded in spin-wave transmission amplitude at 5.04 GHz and 25 dBm, with outputs above 90% and below 10% of the maximum transmission treated as logic 1 and 0, respectively. A Direct Search optimizer adjusts the 49 loop currents to maximize objective functions built from these transmission thresholds. The reported contrast ratios between logic states are 34, 53.9, 11.8, 19.7, 17, and 9.8 dB for NOT, OR, NOR, AND, NAND, and the half-adder.","tokens_in":9844,"tokens_out":3415,"duration_ms":34673,"significance":"If the results are reproducible, the paper makes a meaningful experimental advance: it extends inverse design of magnonic devices from linear RF components to nonlinear Boolean logic, and demonstrates that one programmable platform can implement a functionally complete set of gates and a half-adder. The work builds directly on the authors' prior device (ref. 33), and the new contribution is the nonlinear logic functionality and the half-adder demonstration. The reported transmission values mostly satisfy the stated 90/10 criterion, and the paper is candid about the optimization procedure and objective functions. However, the experimental support is incomplete in ways that bear directly on the central claim: single measurements without error bars, a missing AND-state value, an unmeasured OR \"00\" baseline, and a half-adder carry-output margin of only 0.11 dB from the logic threshold.","major_comments":[{"comment":"The half-adder carry output C at input state \"01\" is reported as 9.73% transmission, corresponding to -60.84 dB, while the logic-0 threshold is 10% of the maximum (-60.73 dB, since the 100% reference is -50.73 dB). The margin is therefore only 0.11 dB. Only one VNA transmission value per state is reported, with no error bars or repeated measurements. A standard VNA noise and drift excursion at -60 dB can easily exceed 0.1 dB, so a single repeated measurement could flip this bit. This margin, not the 9.8 dB contrast ratio, governs whether the half-adder truth table is actually satisfied. The authors should provide repeated measurements of this state, an estimate of measurement uncertainty, and ideally repeated optimization runs, to support the claim that the half-adder is realized.","section":"§II.E, Fig. 5(a)"},{"comment":"The AND-gate paragraph lists only three dB values for four input states: \"The transmission percentages of input states \"00\", \"01\", \"10\" and \"11\" ... correspond to -60.99 dB, -64.007 dB and -41.33 dB, respectively.\" One state is missing, so the AND truth table cannot be verified from the reported data. In addition, Eq. (5), the AND objective, contains no T^{\"00\"} term; the \"00\" output is neither optimized nor reported. The authors must supply the missing value and ideally include the \"00\" state in the objective or explain why it is constrained otherwise.","section":"§II.D and Eq. (5)"},{"comment":"The OR-gate contrast ratio of 53.9 dB is computed using -100 dB as the transmission for input state \"00\", with the justification that this is \"the smallest transmission reached in (33)\". This baseline is taken from a prior paper rather than measured for the present device and current configuration. Since state \"00\" is also absent from the OR objective function in Eq. (3), the reported contrast ratio rests on an assumed rather than measured value. The authors should measure the actual leakage/noise floor in situ, or explicitly restate the contrast ratio as a lower bound with the measurement basis.","section":"§II.C"},{"comment":"All logic results are based on single runs of the Direct Search optimizer and single transmission measurements per state, with no repeated measurements, error bars, or independent restarts. Given that the algorithm is stochastic and relies on mechanical switches, the paper does not yet establish run-to-run or time-dependent reproducibility. This is particularly important for the two marginal gates—the half-adder carry output and the NOR \"11\" state at 6.6%, which sits about 1.8 dB below the 10% threshold. Repeating the measurements of the final configurations and reporting the spread would directly address this concern.","section":"§II.B–E and §III.C"}],"minor_comments":[{"comment":"The formula for T^A is difficult to parse as printed: \"T A = 10\nSA\n21−SA\n21,max\n10 × 100\" should presumably be T^A = 10^((S^A_{21} − S^A_{21,max})/10) × 100, with a clear explanation of the dB reference. Please rewrite it in a single, unambiguous expression.","section":"§II.B, Eq. (2)"},{"comment":"The sample thickness is given as \"18-¸ tm-thick\"; this appears to be a character-encoding corruption for \"18-µm-thick\".","section":"§III.A"},{"comment":"The caption for Fig. 2 lists panels \"a\" and \"c\", but the figure shows \"a\" and \"b\" in the main text; the panel labels should be harmonized.","section":"Fig. 2 caption"},{"comment":"The sentence listing AND transmission percentages is grammatically incomplete because it names four states but provides three dB values; this is a data-completeness issue as well as a presentation issue.","section":"§II.D"},{"comment":"The phrase \"outputs A and B\" in the Fig. 3 and Fig. 4 captions should be \"inputs A and B\"; the outputs are labeled C and S.","section":"§II.E"}],"recommendation":"major_revision","confidential_remarks":"The central idea is attractive and the experimental platform is compelling, but the manuscript currently lacks the measurement repeats and error analysis needed to support the half-adder as a realized gate. The 0.11 dB margin in the carry output is the key risk; this is fixable by additional measurements, so I would not reject. I would also ask the editor to ensure that the novelty relative to ref. 33 is clearly delineated in revision, since the device and optimization framework are described there and the present contribution is specifically the nonlinear logic functionality."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Short version: this is the first experiment to implement nonlinear Boolean gates and a half-adder on a single reconfigurable inverse-design magnonic platform. That is the meaningful new result. The individual gates and inverse design in magnonics are not new—refs 27–29 cover those—but combining them on the 7×7 current-loop device from ref 33 is a genuine step.\n\nWhat the paper does well: the feed-line approach for NOT/NOR/NAND is a clean workaround for producing a logic 1 from a no-input state; the objective functions are written out explicitly; the optimization setup is described in enough detail to be reimplemented; and the quoted contrast ratios, where the data are complete, are respectable. The claim is a demonstration, not an independent prediction, so the fact that the output percentages are the same quantities the optimizer maximized is inherent, not circular.\n\nThe soft spots are mostly reporting. There is one VNA transmission per input state, no error bars, and no repeated optimization runs. The AND section appears to list three dB values for four input states, and the OR 00 baseline is not measured—it is taken as −100 dB from the earlier paper, so the 53.9 dB OR contrast is not a measured number for this device. The weakest point is the half-adder. The carry output at input 01 is 9.73% transmission against a 10% threshold—0.11 dB of margin. A single repeat could flip that bit. NOR has a similarly modest margin. Because the thresholds are exactly what the optimizer was asked to satisfy, the paper's evidence for correctness is these single traces.\n\nNone of this kills the central idea: the device can clearly be steered toward these truth tables. But \"realization\" overstates what is shown. No cascading or fan-out is demonstrated, so \"sufficient for a full processor\" is an overreach for now. This is the kind of paper a serious referee should see; the right response is revision with repeated measurements, error bars, raw data, and a complete AND table, not a desk reject.","headline":"First experimental inverse-design magnonic logic gates on a reconfigurable platform, but the half-adder sits ~0.1 dB from its own threshold and single measurements make the central claim thinner than the abstract suggests.","tokens_in":10395,"tokens_out":3413,"would_cite":true,"duration_ms":60890,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"A single reconfigurable magnonic device is inverse-designed to implement NOT, OR, NOR, AND, NAND, and a half-adder at 5.04 GHz using spin-wave amplitude to encode bits.","keywords":["magnonic logic gates","inverse design","spin waves","YIG film","reconfigurable device","Boolean computing","half-adder","current loops"],"falsifier":"Measure the transmission of every logic state repeatedly over time for the optimized current configurations, or rerun the Direct Search optimization from multiple random starting points and check whether each attempt satisfies the 90/10 threshold condition; if variability erases the smaller contrast margins (about 10 dB for the half-adder and NOR), the claimed gate reliability does not hold.","tokens_in":36,"feed_emoji":"🧲","tokens_out":5078,"duration_ms":278660,"temperature":0.7,"pith_summary":"The paper reports the first experimental realization of inverse-designed magnonic logic gates. A single reconfigurable device, a 7x7 array of current loops on a yttrium-iron-garnet film, is optimized by a feedback algorithm to produce the Boolean functions NOT, OR, NOR, AND, NAND, and a half-adder. Bits are encoded in the amplitude of a 5.04 GHz spin wave, with '1' above 90% and '0' below 10% of the maximum transmission. If the demonstration holds, it shows that a single physical platform can be reprogrammed to perform a functionally complete set of logic operations without resorting to electronic components or new fabrication.","feed_headline":"One magnonic device runs six logic gates at 5 GHz","feed_subtitle":"Spin-wave amplitudes encode bits; a current-loop array is reprogrammed to emulate six Boolean functions.","key_machinery":"The key machinery is the 7x7 array of omega-shaped current loops, each producing a local Oersted field of up to ±3.46 mT that shifts the spin-wave dispersion and thereby alters interference in the spin-wave transmission. The Direct Search algorithm walks through the 49 loops one by one, accepting or rejecting random current changes to drive a gate-specific objective function toward 100%. The objective functions combine transmission percentages defined by a 90/10 threshold rule, and for the half-adder they simultaneously constrain two output transducers (sum and carry).","core_discovery":"The central discovery is that an inverse-design procedure, which iteratively adjusts 49 independent loop currents to maximize an objective function, can land on current configurations whose spin-wave interference implements six distinct logic functions on the same YIG-based device. The authors report contrast ratios of 34, 53.9, 11.8, 19.7, 17, and 9.8 dB for NOT, OR, NOR, AND, NAND, and the half-adder, respectively, all measured at 5.04 GHz with 25 dBm input power in the nonlinear spin-wave regime. The NOT, NOR, and NAND gates use a continuously open feed-line to supply a reference signal so that the '0' input state still yields a detectable output.","pith_inferences":["The single-run optimization with no repeated measurements leaves open whether the reported current configurations are robust; a natural extension is to test reproducibility across restarts and over time.","The 90/10 amplitude threshold implies that cascading gates would require careful gain or regeneration, since the output amplitudes vary across gates; the authors do not address fan-out.","The same inverse-design scheme could in principle be used to search for XOR, full adder, or majority gates directly, since the objective-function framework is not specific to the demonstrated functions.","The contrast ratios differ by more than a factor of five across gates, suggesting that some functions (half-adder, NOR) are operating closer to the margin and may be the first to fail under perturbations."],"forward_implications":["A single inverse-designed device can be reprogrammed to serve as different logic gates, so a magnonic processor need not be fabricated per function.","The demonstrated gate set is functionally complete (NOR and NAND are universal), meaning arbitrary Boolean circuits could in principle be built by cascading these gates.","The half-adder shows that multi-output operations can be encoded in one optimization, reducing the gate count compared with assembling XOR and AND separately.","Operation in the nonlinear spin-wave regime at 25 dBm indicates that the same interference mechanism can support amplitude-based logic rather than phase-based logic.","Because all gates run at the same 5.04 GHz frequency, the device is compatible with frequency-multiplexed signal processing."],"supporting_citations":[{"why":"Provides the universal reconfigurable inverse-design device (7x7 current loops on YIG) that this work reuses for logic gates.","marker":"[33]"},{"why":"Introduces the inverse-design approach and Direct Binary Search style optimization that the Direct Search algorithm adapts.","marker":"[27]"},{"why":"Supplies the Direct Binary Search algorithm concept on which the Direct Search optimizer is based.","marker":"[38]"},{"why":"Establishes the nonlinear spin-wave regime at high microwave power that the logic-gate operation relies on.","marker":"[34]"},{"why":"Demonstrates a numerically simulated half-adder based on directional couplers, the baseline this paper's direct half-adder implementation is compared against.","marker":"[17]"},{"why":"Describes the liquid-phase-epitaxy YIG film growth that provides the low-damping sample used here.","marker":"[36]"},{"why":"Documents the broad-wavenumber microstrip transducers used to excite and detect spin waves.","marker":"[37]"}],"fun_headline_variants":["One inverse-designed magnonic chip runs six logic gates","Six magnonic gates from one current-loop array via inverse design","Inverse design yields six non-linear magnonic logic gates at 5 GHz","Single YIG device reprogrammed for NOT, OR, NOR, AND, NAND, half-adder","Magnonic logic: 49 current loops, six Boolean functions, one inverse design"],"cache_read_input_tokens":12544,"weakest_assumption_plain":"The load-bearing premise is that the single run of the Direct Search optimizer yields a current configuration with reproducible logic behavior; with only one transmission value per input state and no error bars, any run-to-run or time-dependent variation comparable to the smallest contrast margins (about 9.8 dB) would break the claimed functionality.","fun_headline_variants_meta":{"raw":{"variants":["One inverse-designed magnonic chip runs six logic gates","Six magnonic gates from one current-loop array via inverse design","Inverse design yields six non-linear magnonic logic gates at 5 GHz","Single YIG device reprogrammed for NOT, OR, NOR, AND, NAND, half-adder","Magnonic logic: 49 current loops, six Boolean functions, one inverse design"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000627,"raw_usage":{"total_tokens":2852,"prompt_tokens":846,"completion_tokens":2006,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":462,"completion_tokens_details":{"reasoning_tokens":1906}},"tokens_in":462,"tokens_out":2006,"duration_ms":14579,"temperature":1.0,"reasoning_tokens":1906,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-12T11:59:57.924117+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Measure the transmission of every logic state repeatedly over time for the optimized current configurations, or rerun the Direct Search optimization from multiple random starting points and check whether each attempt satisfies the 90/10 threshold condition; if variability erases the smaller contrast margins (about 10 dB for the half-adder and NOR), the claimed gate reliability does not hold.","supporting_citations":[{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Introduces the inverse-design approach and Direct Binary Search style optimization that the Direct Search algorithm adapts."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Supplies the Direct Binary Search algorithm concept on which the Direct Search optimizer is based."},{"cited_title":"Wang, et al","cited_arxiv_id":null,"evidence_quote":"Establishes the nonlinear spin-wave regime at high microwave power that the logic-gate operation relies on."},{"cited_title":"Wang, et al","cited_arxiv_id":null,"evidence_quote":"Demonstrates a numerically simulated half-adder based on directional couplers, the baseline this paper's direct half-adder implementation is compared against."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Documents the broad-wavenumber microstrip transducers used to excite and detect spin waves."}],"review_version":1}