{"id":"7d4c7d3d-4c87-4136-be5e-7d3a646334b9","arxiv_id":"2412.07181","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":7.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":4,"one_line_summary":"PachinQo is a co-design framework that compiles general quantum algorithms onto zonal-addressing Rydberg atom computers, reducing simulated runtime and raising estimated success probability.","lead":"A new software framework, PachinQo, co-designs the hardware layout and compiler for a new type of Rydberg atom quantum computer called zonal addressing. In simulations, it cuts circuit runtime by about 20% and boosts a generic algorithm's estimated success probability by 45% compared with a degree-based baseline.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The reported gains hinge on an unvalidated assumption that all initialization/readout trap changes are parallel; if transfers serialize, the 6-trap-change overhead becomes hundreds of milliseconds and the headline 20%/45% improvements collapse.","rationale":"The reader's weakest assumption already identifies the inherited hardware parameters and the parallel trap-change assumption as the key fragility. My stress-test confirms this is the single most load-bearing point: the claimed improvements are computed under a model where every algorithm pays exactly six 125 us trap changes, and this is what makes runtimes like 11.7 ms for 1000 qubits possible. The paper provides no measurement, simulation, or citation showing that all SLM-to-AOD and AOD-to-SLM transfers can be parallelized across the whole array in the proposed dual-cache layout. The concrete test would settle it because it directly quantifies how much of the 20% runtime and 45% ESP advantage comes from the parallel-transfer assumption rather than from the compiler heuristics. I do not see a separate objection that outweighs this one; the framework is open-sourced, the benchmark set is reasonable, and the comparisons to DegreeSplit, OneCache, and TrapChange are meaningful under the stated model. The paper honestly discusses heuristic trade-offs and does not claim experimental validation, so the appropriate outcome remains CONDITIONAL: the quantitative claims should be accompanied by a sensitivity analysis of the parallel trap-change assumption, and ideally by a hardware-informed count of serial transfers for the proposed geometry.","tokens_in":24989,"tokens_out":11299,"duration_ms":123884,"concrete_test":"Add a mode to the released simulator (github.com/positivetechnologylab/PachinQo) that replaces the global-parallel trap-change model with a conservative serialized model: each atom (or at minimum each 4-atom AOD column) transferred from memory SLM to AOD and from AOD to compute SLM/readout costs one 125 us trap change, respecting AOD column ordering. Re-run all 13 benchmarks in Table 2 and compare average circuit runtime and ESP. If QV runtime rises from about 11.7 ms to more than 30 ms, or if 129-qubit TFIM runtime more than doubles, the headline improvements are not robust to this assumption and the paper should be revised to report results under both parallel and serial trap-change models.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central performance claim depends on PachinQo incurring only six trap changes per algorithm, regardless of qubit count. This comes from Sec. 4.2's assertion that all memory-SLM-to-AOD and AOD-to-compute-SLM transfers 'can be run in parallel' because atoms are initially organized into columns, and Sec. 6.3's report that every algorithm uses exactly six trap changes (three for initialization, three for measurement). Table 1 sets trap-change time at 125 us. No hardware demonstration is cited for parallelizing these transfers in the modified dual-cache geometry, and the readout-zone-as-cache change is new to this paper, so inheriting the 125 us value from Bluvstein et al. [9] is not validated. If transfers serialize, the overhead is severe: even at the paper's own limit of 4 atoms per AOD column, a 1000-qubit QV circuit needs at least 250 serial column transfers, i.e., 31.25 ms of trap-change time alone—roughly three times PachinQo's reported 11.7 ms runtime for QV; a 129-qubit circuit serially transferred per atom costs 16.1 ms, comparable to or larger than most reported runtimes. Because ESP includes decoherence and gate-error products, this would also erode the 45% ESP improvement. The paper's internal inconsistency on trap-change cost (Sec. 2 says 25x a CZ; Sec. 4.2 says 156x a CZ) reinforces that this cost model was not carefully cross-checked. If the parallel trap-change assumption fails, the architecture's chief quantitative advantages are not transferable to real hardware.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"PachinQo is a co-design framework for zonal addressing Rydberg atom quantum computers. It proposes a dual-cache architecture (repurposing the readout zone as a second cache), a greedy MaxCut-based grouping of qubits into static SLM traps and mobile AOD columns, and a layer-by-layer compiler that schedules CZ gates, U3 gates, and SWAPs while respecting AOD column-ordering constraints. The evaluation uses a custom simulator with parameters largely taken from Bluvstein et al. and compares against three self-constructed baselines (DegreeSplit, OneCache, TrapChange) on 13 benchmarks. Reported results include a 20% average runtime reduction, 50% fewer SWAPs, and 45% higher estimated success probability versus DegreeSplit.","tokens_in":25443,"tokens_out":9953,"duration_ms":93154,"significance":"The work addresses a genuine gap: prior zonal addressing demonstrations (Bluvstein et al., Stade et al.) target only surface-code-like parallel circuits, and there is no general compilation/co-design framework for this emerging architecture. The paper is commendable for open-sourcing the framework, for reporting compiler overheads on a commodity laptop, and for evaluating a diverse benchmark set up to 1000 qubits. If the hardware cost model is reliable, the runtime and ESP improvements are meaningful. However, the quantitative contributions are entirely simulation-based, and the central cost model has internal inconsistencies and a strong unvalidated parallelism assumption. The framework's qualitative design insights are likely to be useful to the community even if the reported numbers change under a more conservative cost model.","major_comments":[{"comment":"The reported trap-change cost is internally inconsistent. Section 2 states that a trap change takes 25 times as long as a CZ gate, Section 4.2 states that it takes about 156 times as long as a CZ gate, and Section 6.3 states that it takes about 52 times as long as a SWAP gate, which is defined as three CZ gates plus six U3 gates. Using Table 1 (trap change 125 us, CZ 0.8 us, U3 2 us), the correct ratios are 156x a CZ and about 8.7x a full SWAP. These inconsistencies matter because trap-change time is a major factor in the initialization and measurement overhead of PachinQo and a dominant factor in the TrapChange baseline; the runtime comparisons in Figs. 12, 16, and 17 depend on this parameter. The authors should adopt a single, explicitly stated cost model and ensure all ratios are derived from it.","section":"Sec. 2, Sec. 4.2, Sec. 6.3, Table 1"},{"comment":"The claim that only six serial trap changes are needed for every algorithm rests on an unvalidated and likely size-dependent assumption. Section 4.2 states that all memory-to-AOD and AOD-to-SLM transfers 'can be run in parallel' because atoms are initially organized into columns, but no hardware demonstration or reference is given for this capability in the proposed dual-cache geometry, which repurposes the readout zone as a cache. More concretely, Section 5 limits each AOD column to at most 4 atoms and gives zone dimensions that are doubled only for QV and ISL; for a 1000-qubit circuit with roughly 500 SLM-bound atoms, at least 125 AOD columns (or serial batches) would be needed. It is not established that the AOD can contain that many columns or that the parallel transfer can be performed without column-order violations. If these transfers serialize, the six-trap-change count in Fig. 17 becomes a lower bound that scales with qubit count, and the reported runtime and ESP advantages in Figs. 12 and 14 would be eroded, particularly for smaller circuits such as KNN, whose 11.6 ms runtime would be dominated by per-atom transfer times of 125 us each. The paper needs a hardware-based justification or a revised cost model that accounts for AOD capacity limits.","section":"Sec. 4.2, Sec. 5, Sec. 6.3"},{"comment":"The statement that 'PachinQo will never perform more than one SWAP in order to execute a single CZ gate' is asserted without proof and is load-bearing for the complexity bound and for the SWAP-count comparisons. Algorithm 1 assigns initial SLM/AOD groupings but does not guarantee that every CZ whose endpoints end up in the same trap type can be resolved with exactly one SWAP under the AOD ordering and cache constraints described in Sec. 4.4. If more than one SWAP is sometimes required, the O(G(Q_AOD Q_SLM + QG)) complexity analysis and the 50% SWAP reduction over DegreeSplit could both be affected. The authors should provide a proof of this invariant or empirically validate it by reporting the distribution of SWAPs per CZ in their simulations.","section":"Sec. 4.8"},{"comment":"The estimated success probability (ESP) is a product of assumed error rates (gate errors, readout error, T1/T2 decoherence) taken from multiple sources, and the 45% improvement is therefore not a measured quantity but a model output. The paper should state this more prominently in the abstract and conclusion, and it would benefit from a sensitivity analysis over the error parameters: the reported ESP gains could change materially if, for example, the SWAP error (1.51%) or the trap-change time differ on the proposed dual-cache hardware. Without such an analysis, the quantitative headline is difficult to assess.","section":"Sec. 5, Table 1, Figs. 12-14"}],"minor_comments":[{"comment":"The header 'Algoritm' should be 'Algorithm'.","section":"Table 3"},{"comment":"Panel (c) is labeled 'Traingle Grid'; this should be 'Triangle Grid'.","section":"Fig. 18"},{"comment":"The title contains 'Dddressing'; it should be 'Addressing'.","section":"Reference [38]"},{"comment":"The caption contains 'Vaccum Chamber'; it should be 'Vacuum Chamber'.","section":"Fig. 1(b)"},{"comment":"The complexity expression O(G[Q_AOD Q_SLM + Q G]) uses nonstandard bracket notation; it should be written as O(G(Q_AOD Q_SLM + QG)).","section":"Sec. 4.8"},{"comment":"The text says 'For more figures on error and execution times', but it should be 'For more figures on error rates and execution times'; additionally, the description of how T1 and T2 are converted into error rates is missing and should be supplied.","section":"Sec. 5"}],"recommendation":"major_revision","confidential_remarks":"The paper is already published at SIGMETRICS 2025, but for this journal submission the main risk is that the quantitative claims depend on a parallel trap-change assumption that is not validated and may be size-limited. I would ask the authors to either provide experimental evidence or conservative serialized estimates. The internal inconsistency in trap-change timing ratios is easy to fix but suggests the cost model was not carefully cross-checked. Also, the comparison baselines are all derived from the authors' own framework; an independent baseline (e.g., adapting a prior zonal compiler, or a strawman with standard AOD movement) would strengthen external validity."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"The short version: this is the first compiler/architecture framework for general quantum algorithms on zonal-addressing Rydberg systems, and the core ideas are sensible. The evaluation is a self-consistent simulation, but the headline numbers depend on a load-bearing assumption about parallel trap changes that the paper does not validate, and the text contains an internal inconsistency about trap-change cost that should have been caught.\n\nWhat's actually new: prior zonal compilers (Bluvstein 2024, Stade 2024) target surface codes or error-corrected circuits with all-parallel operations. PachinQo handles arbitrary circuits. The dual-cache architecture (using the readout zone as an extra store) plus greedy MaxCut grouping to separate interacting qubits into SLM/AOD groups is a reasonable co-design. The alternating left/right processing direction is a nice touch that avoids column starvation, and the preemptive SWAP decomposition is a clever scheduling trick. The implementation is open source and compiles most benchmarks in under a second. The authors also state design trade-offs honestly in Sec 4.7 rather than overselling.\n\nThe soft spots are real but not fatal to the qualitative contribution. First, the parallel trap-change assumption: Sec 4.2 claims all memory-to-AOD and AOD-to-SLM transfers 'can be run in parallel' because atoms are organized in columns, and Sec 6.3 reports exactly six trap changes per algorithm. That assumption is load-bearing. If transfers serialize, a 1000-qubit QV circuit with at most 4 atoms per AOD column would need at least 250 serial column transfers, costing about 31ms at the paper's own 125us per trap change—roughly three times the reported 11.7ms QV runtime. No hardware test is cited for parallelizing these transfers in the modified dual-cache geometry, and using the readout zone as a cache is new to this paper, so inheriting the 125us value from Bluvstein et al. [9] is not validated. This directly affects both the 20% runtime and the 45% ESP claims.\n\nSecond, the trap-change timing ratio is stated as 25x a CZ in Sec 2, 156x a CZ in Sec 4.2, and 52x a SWAP in Sec 6.3. Those don't reconcile. It's sloppy and suggests the cost model wasn't cross-checked. Third, ESP is a product of assumed gate errors and decoherence, not a measured quantity, and the baselines are built from PachinQo's own components. That's acceptable for a systems simulation, but it means the quantitative figures are conditional.\n\nWho this is for: people working on neutral-atom compilation or quantum architecture co-design. It deserves a serious referee: the problem is timely, the approach is new, and the implementation is reusable. But the authors should be pushed to validate or heavily caveat the parallel trap-change assumption and fix the timing discrepancies.","headline":"PachinQo is a credible first compiler for general algorithms on zonal Rydberg architectures, with a smart dual-cache/MaxCut design, but the headline gains rest on an unvalidated parallel trap-change assumption and the timing ratios in the text don't agree.","tokens_in":25920,"tokens_out":2833,"would_cite":true,"duration_ms":28144,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"PachinQo claims that co-designing a dual-cache zonal Rydberg architecture with a greedy MaxCut compiler makes general quantum algorithms run with 45% higher success probability, 20% less runtime, and 50% fewer SWAPs.","keywords":["Rydberg atom quantum computing","zonal addressing","quantum cache","MaxCut qubit partition","hardware-software co-design","quantum compilation","neutral atom architectures","estimated success probability"],"falsifier":"Run a locally structured circuit such as TFIM or ISL on a zonal Rydberg prototype with two caches flanking compute and independently movable AOD columns, and compare measured wall-clock runtime and SWAP count against a degree-based grouping baseline. If the realized runtime reduction is not around 20% or the SWAP reduction not around 50%, the central co-design claim would be falsified; a second check is whether initialization trap changes across the memory/AOD boundary can actually be performed in parallel in that geometry.","tokens_in":24818,"feed_emoji":"⚛️","tokens_out":6507,"duration_ms":61955,"temperature":0.7,"pith_summary":"PachinQo is a hardware-software co-design framework for Rydberg atom quantum computers that use zonal addressing, an architecture where a compute zone is illuminated by a Rydberg laser while other qubits wait in memory. The authors claim that this architecture, demonstrated so far only for surface-code-style circuits, can be extended to arbitrary quantum algorithms by changing both the hardware and the compiler together: add a second cache on the opposite side of the compute zone, reuse the readout zone as a cache, and let the compiler partition qubits into static and mobile groups with a greedy MaxCut heuristic, move columns between the two caches, and split SWAPs into per-layer pieces. The payoff, across 13 benchmark circuits of 51 to 1000 qubits, is an average 45% higher estimated probability of success, a 20% shorter circuit runtime, and 50% fewer SWAP gates compared with a degree-based grouping baseline. This matters because zonal addressing is a leading scalable Rydberg design, and the result suggests that its usefulness depends on co-designing the layout of zones with the compiler rather than treating compilation as an add-on.","feed_headline":"PachinQo boosts Rydberg circuit success by 45%","feed_subtitle":"Adding a second cache and pairing it with a MaxCut-based compiler cuts runtime 20% and SWAPs 50% on general algorithms.","key_machinery":"The load-bearing object is the zonal addressing layout with a dual quantum cache: a compute zone illuminated by the Rydberg laser, stationary SLM traps inside it, and movable AOD columns that park in either of two caches flanking compute, one of which is also the readout zone. Three mechanisms carry the argument: the greedy MaxCut grouping in Algorithm 1, which maximizes the number of CZ gates whose qubits sit in different device groups; alternating sweep direction and cache side, so AOD columns get balanced access to compute without violating the no-overtaking ordering constraint; and preemptive SWAP decomposition, which spreads a SWAP's three CZ gates and six U3 gates one per layer to keep individual layer runtime short. Together they reduce crosstalk, movement, and serial trap changes.","core_discovery":"PachinQo claims that the bottleneck to running general quantum algorithms on zonal Rydberg machines is not just compilation but the fixed architecture itself. It therefore proposes a dual-cache geometry, a cache on each side of the compute zone with the right cache doubling as the readout zone, and a matching compiler that uses a greedy MaxCut partition to assign qubits to stationary SLM traps or mobile AOD columns so most CZ gates happen between one mobile and one stationary qubit. During execution the compiler sweeps AOD columns from alternate sides, moves idle columns into the opposite cache to avoid crosstalk, and decomposes SWAPs into their component CZ and U3 gates, executing one piece per layer so a SWAP does not stall other gates. In the paper's evaluation this co-design reduces circuit runtime by 20%, SWAP count by 50%, and raises estimated success probability by 45% on average over a degree-based grouping method, across 13 circuits of 51 to 1000 qubits.","pith_inferences":["If the co-design result transfers to hardware, the readout-zone-as-cache trick implies that idle measurement hardware can be repurposed as transport infrastructure, a principle that could reduce area overhead in other reconfigurable qubit platforms.","The failure of degree-based grouping on locally structured circuits such as Ising and TFIM suggests that for many near-term algorithms the relevant partition is interaction locality, not per-qubit degree; a similar connectivity-aware heuristic may benefit routing in other shuttling architectures.","Preemptive SWAP decomposition is effectively software pipelining of a routing operation, and the same one-gate-per-layer scheduling could be tested as a general compiler pass for architectures where SWAPs are not atomic.","Because performance is nearly independent of SLM grid geometry in the simulation, the framework opens a cheap knob: algorithm-specific atom arrangement can be chosen to match circuit structure without recompilation."],"forward_implications":["On the paper's 13 benchmark circuits (51 to 1000 qubits), co-design lowers average circuit runtime by 20% and SWAP count by 50% relative to a degree-based grouping baseline.","Estimated probability of success improves by 45% on average in the paper's error model, directly because fewer SWAPs and shorter runtimes reduce error accumulation.","The dual-cache geometry alone buys a 24% runtime reduction over a single-cache version by cutting total movement by 32.3% and avoiding column starvation, while ESP is within 6%.","Using SWAPs instead of trap changes during execution cuts serial trap changes by 43% on average and runtime by 19% versus a trap-change variant.","Compilation stays lightweight, with a median of 296.4 milliseconds on a laptop, and the compiler needs no retuning when the static SLM atom grid is changed, so the same framework can be matched to different architecture layouts."],"supporting_citations":[{"why":"Defines the zonal addressing architecture and supplies the grid dimensions, trap-change time, and AOD movement parameters the simulator inherits.","marker":"[9]"},{"why":"Provides the AOD transport model, movement-speed and coherence-time values used in the cost and error models.","marker":"[10]"},{"why":"Supplies QASMBench circuits including the 1000-qubit quantum volume benchmark used in the evaluation.","marker":"[25]"},{"why":"Supplies ArQTiC benchmark circuits used alongside QASMBench for the 13-algorithm evaluation.","marker":"[7]"},{"why":"Formulates the MaxCut problem that PachinQo's greedy grouping heuristic approximates.","marker":"[12]"},{"why":"Qiskit is used to read QASM circuits and transpile them into the U3/CZ basis that PachinQo compiles.","marker":"[3]"}],"fun_headline_variants":["PachinQo lifts Rydberg success 45%","Co-design boosts Rydberg odds 45%","PachinQo: 45% better Rydberg quantum success","Rydberg co-design: 45% success, 20% less runtime","PachinQo cuts SWAPs 50%, raises success 45%"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The result stands on the assumption that the hardware timing constants measured on existing zonal Rydberg machines, trap-change time, AOD movement speed, and zone dimensions, along with the assumption that all initialization trap changes can be run in parallel, remain valid in the proposed dual-cache geometry; if either fails on real hardware, the reported runtime and success-probability gains would not carry over.","fun_headline_variants_meta":{"raw":{"variants":["PachinQo lifts Rydberg success 45%","Co-design boosts Rydberg odds 45%","PachinQo: 45% better Rydberg quantum success","Rydberg co-design: 45% success, 20% less runtime","PachinQo cuts SWAPs 50%, raises success 45%"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000167,"raw_usage":{"total_tokens":1225,"prompt_tokens":878,"completion_tokens":347,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":494,"completion_tokens_details":{"reasoning_tokens":250}},"tokens_in":494,"tokens_out":347,"duration_ms":3668,"temperature":1.0,"reasoning_tokens":250,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-11T19:03:40.897933+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Run a locally structured circuit such as TFIM or ISL on a zonal Rydberg prototype with two caches flanking compute and independently movable AOD columns, and compare measured wall-clock runtime and SWAP count against a degree-based grouping baseline. If the realized runtime reduction is not around 20% or the SWAP reduction not around 50%, the central co-design claim would be falsified; a second check is whether initialization trap changes across the memory/AOD boundary can actually be performed in parallel in that geometry.","supporting_citations":[{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Defines the zonal addressing architecture and supplies the grid dimensions, trap-change time, and AOD movement parameters the simulator inherits."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Provides the AOD transport model, movement-speed and coherence-time values used in the cost and error models."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Supplies QASMBench circuits including the 1000-qubit quantum volume benchmark used in the evaluation."},{"cited_title":"ArQTiC: A full-stack software package for simulating materials on quantum computers","cited_arxiv_id":"2106.04749","evidence_quote":"Supplies ArQTiC benchmark circuits used alongside QASMBench for the 13-algorithm evaluation."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Formulates the MaxCut problem that PachinQo's greedy grouping heuristic approximates."}],"review_version":1}