{"id":"b898a106-3ae5-48bb-b158-c973468dc13f","arxiv_id":"2412.08017","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":4,"one_line_summary":"A 130 nm CMOS ASIC with 1143 p-bits successfully factorized 6-bit numbers using random bits from voltage-controlled MTJs, with simulated extensions to 20 bits.","lead":"This paper builds a custom 130 nm ASIC that uses 1143 probabilistic bits to factor integers, pulling random numbers from a separate chip of voltage-controlled magnetic tunnel junctions. It shows working 6-bit factorization and argues that combining CMOS logic with these MTJ entropy sources could scale to millions of bits on one chip.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The central claim requires that the raw, un-XORed V-MTJ bit stream be random enough for Eq. 1, but the paper's NIST data show it is not, leaving the 6-bit factorization as insufficient evidence for a working integrated entropy source.","rationale":"The reader's weakest assumption identifies exactly the same load-bearing premise: the raw, un-XORed V-MTJ bit stream must provide adequate entropy for correct p-bit updates, even though the only NIST-passing data are obtained after XOR4. I agree with that assessment. The paper explicitly states that the PIM ASIC received raw bits without XOR layers, and the NIST results show only 2/11 tests passing on the raw stream. The PLU's use of 16 raw bits to form each noise sample means that even modest bit bias or correlation changes the sampled distribution, and the reported single-instance 6-bit factorization is too weak to establish that the system is sampling the intended Ising distribution. This concern does not refute the demonstration; the 67.5% success rate and the fabricated ASIC are meaningful evidence that the CMOS p-bit architecture works. But the entropy-source claim, which is central to the title and abstract, is not independently established. The reader's conditional verdict is therefore the right level of confidence: the work is promising, but the raw entropy assumption needs direct validation before the full claim can be accepted.","tokens_in":15126,"tokens_out":3807,"duration_ms":43605,"concrete_test":"Record the exact raw bit sequence that was sent to the ASIC during a reported 8192-iteration factorization run. Build a bit-accurate simulator of the PLU LUT and p-bit update from Section IV, and replay the run twice: once with the recorded raw bits and once with an ideal uniform random source, keeping all annealing parameters identical. If the correct-state fractions for (5,7) and (7,5) are statistically equivalent, the raw entropy concern is resolved; if the raw-bit run degrades materially, the experimental claim must be qualified as relying on a biased source.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The paper's central claim depends on the bit stream fed to the ASIC providing samples from the uniform distribution used in the p-bit update of Eq. 1. The paper reports that the raw V-MTJ stream passed only 2/11 NIST tests, while the fully passing stream was obtained only after two XOR4 layers, i.e., from bits that were not the ones sent to the ASIC during factorization. The PLU consumes 16 raw bits per p-bit update to form a tanh-distributed sample, so any bias, drift, or correlation in those bits shifts the effective update distribution and changes the annealing behavior. The 67.5% success on the single 6-bit instance 35, with a single V-MTJ device, does not distinguish a correctly sampling Ising machine from a deterministic annealer driven by a weak or biased noise source. Since the scaling projection to millions of probabilistic bits relies on V-MTJs as trustworthy entropy sources for the CMOS p-bits, this gap is load-bearing and not addressed by the reported NIST results.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The manuscript reports a 130 nm CMOS ASIC implementing 1143 probabilistic bits for integer factorization, driven by a voltage-controlled MTJ (V-MTJ) entropy source that generates random bits on demand via the voltage-controlled magnetic anisotropy effect. The authors show that the experimental system factors the number 35 in 8192 iterations, with 67.5% of final states being the two valid factor pairs, and present NIST randomness results for the V-MTJ bit stream, which passes all 11 tests only after two XOR4 stages. They also simulate a 20-bit factorization using a modified design not implemented on the current chip, and they use synthesized 45 nm and 7 nm designs plus assumed V-MTJ cell areas to project scalability toward millions of p-bits.","tokens_in":15312,"tokens_out":7051,"duration_ms":75774,"significance":"If the entropy-quality gap is closed, this is a meaningful integration step: it is, to my knowledge, the first fabricated ASIC-level probabilistic Ising machine co-designed with an MTJ entropy source, and the paper includes concrete engineering details such as a synchronous p-bit architecture, a 30 nm V-MTJ, a comparison table with prior CMOS+MTJ platforms, and a measured 6-bit factorization. The authors are candid about the I/O bottleneck and about the distinction between measured and projected performance. However, the experimental support for the central claim is narrow: one V-MTJ, one factorization instance, and no repeated trials, while the entropy source as used during the factorization did not pass NIST randomness tests. The scaling projections are clearly labeled as projections but rest on assumed cell sizes and synthetic PDK densities.","major_comments":[{"comment":"The ASIC received raw V-MTJ bits, not the XOR4-processed stream, yet only the XOR4 stream passes NIST STS (11/11 vs. 2/11 for raw). Because Eq. (1) draws r from a uniform distribution on (-1,1), a biased or correlated raw stream changes the effective update distribution implemented by the PLU. The single 67.5%-plurality histogram for the factorization of 35 therefore does not establish that the V-MTJ supplied entropy of adequate quality. Please report the bias, autocorrelation, and drift of the bit sequence actually delivered to the ASIC during factorization runs, compare results with and without XOR post-processing, and show either that the raw-stream statistics are adequate or that the update rule is robust to the measured deviations.","section":"Methods, Table E1; §V, Fig. 6d"},{"comment":"The experimental evidence is one V-MTJ device, one problem instance (35), and one 8192-iteration annealing run. The reported 67.5% valid-state rate is a plurality without error bars or a statistical significance test, and it does not distinguish a correctly sampling Ising machine from a weakly stochastic or biased annealer. Please add repeated independent trials, multiple devices, and a statistical comparison (e.g., bootstrap or chi-square) of the experimental state distribution against the simulated distribution for the same J and h.","section":"§V, Fig. 6d; Table 1"},{"comment":"The text states that the PLU circuit 'sampled from the energy distribution of the Ising Hamiltonian defined by the J matrix and h vector' (Sec. IV). This is a distributional claim, but only the ground-state histogram of one factorization problem is shown. At fixed temperature the p-bit state distribution should be compared with the Boltzmann distribution of the implemented J/h for a small instance; without that check, the experimental data support only the weaker claim that the network reaches the low-energy states.","section":"Sec. IV; Eq. (1)"}],"minor_comments":[{"comment":"There are typographical spacing errors ('large number s' in the abstract, 's of' in Sec. I); please proofread the manuscript.","section":"Abstract; Sec. I"},{"comment":"Figures 6b–6d would be more useful if the captions gave the total number of trials and the exact percentage for each reported plurality or majority.","section":"Fig. 6"},{"comment":"The description of the XOR post-processing is ambiguous: please state the stream length after each stage and clarify whether XOR4 consumes four original bits or two XOR2 outputs.","section":"Methods, Table E1"},{"comment":"The data availability statement should be more specific; raw V-MTJ bitstreams and per-trial factorization outcomes are needed to assess the statistical claims.","section":"Data availability"},{"comment":"Reference [39] does not appear to be cited in the body text; please check the citation numbering.","section":"References"}],"recommendation":"major_revision","confidential_remarks":"The raw-entropy issue is the main barrier to accepting the central claim as stated; it is fixable by additional characterization and experiments, so I recommend major revision rather than rejection. The paper is a solid integration demonstration but currently overstates the level of validation. The scaling projections should be treated as scenario estimates, not validated performance."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"First things first: the chip is real, the 6-bit factorization is reproducible across 8192 trials with 67.5% valid final states, and the paper is honest about its limitations. The genuinely new piece is a custom 130 nm CMOS ASIC implementing 1143 p-bits that receives random bits from a V-MTJ TRNG through a PCB. Earlier MTJ-based PIMs used CPUs, FPGAs, or MCUs; a co-designed ASIC with a spintronic entropy source is a first for this class, and the synchronous, sparse-connectivity design is solid engineering. The open-source PDK flow and the measured 0.43 pJ/bit for the V-MTJ are useful concrete numbers. The scaling projections are speculative but clearly labeled as such, and the authors do not oversell them.\n\nThe main soft spot is the entropy source. The raw V-MTJ bit stream passed only 2/11 NIST tests; the stream that passes all 11 is after XOR4, which is not what the ASIC used. The PLU consumes 16 raw bits per p-bit update to approximate the tanh sampling in Eq. 1, so any bias or correlation shifts the effective update rule and the annealing trajectory. The paper explicitly states that the bits supplied to the ASIC did not go through XOR layers, and the Methods explain the raw stream's bias. That gap is load-bearing for the claim that this is a sampling Ising machine rather than a deterministic annealer driven by a skewed noise source. One could argue NIST STS is stricter than needed for p-bit updates—and I'd be open to that—but the onus is on the authors to show the raw stream still supports the intended distribution. They don't.\n\nAlso, all experiments used one V-MTJ device and one problem instance (35), with no error bars or repeated device statistics. The valid states form a plurality, not a majority. That is fine for a proof-of-concept, but it limits the strength of the claim. And the title says \"integrated\" while the V-MTJ is wire-bonded on a separate PCB; monolithic integration is only projected.\n\nWho is this for? Researchers in spintronics, unconventional computing, and hardware for Ising machines will want to read it. It deserves a serious referee. The main request should be: show the raw-stream statistics and either demonstrate sufficient uniformity for Eq. 1 or add an XOR stage to the PIM path and re-measure. I'd accept it with major revision on those grounds.","headline":"Real fabricated probabilistic ASIC driven by V-MTJ entropy, but the raw-bit bias gap keeps the result conditional.","tokens_in":15933,"tokens_out":2316,"would_cite":true,"duration_ms":25519,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"An ASIC with 1,143 probabilistic bits, fed by voltage-controlled magnetic tunnel junctions, solves integer factorization and projects to millions of p-bits.","keywords":["probabilistic Ising machine","p-bits","voltage-controlled magnetic anisotropy","magnetic tunnel junction","true random number generator","integer factorization","invertible logic","CMOS ASIC"],"falsifier":"Feed the same 6-bit factorization trials with the V-MTJ's raw bit stream and with its XOR4-processed stream, and compare the solution distributions: if the raw-stream success rate drops below the paper's measured 67.5% or the energy minima no longer match the correct factors, the raw entropy quality is insufficient.","tokens_in":14878,"feed_emoji":"🧲","tokens_out":4721,"duration_ms":41538,"temperature":0.7,"pith_summary":"The paper demonstrates a fabricated 130 nm ASIC that implements a probabilistic Ising machine for integer factorization using 1,143 probabilistic bits, with random bits supplied by a voltage-controlled magnetic tunnel junction (V-MTJ) rather than a software or CMOS random number generator. The V-MTJ is thermally stable at rest and produces a random bit on demand when a 10 ns voltage pulse temporarily collapses its energy barrier. The authors show that the combined system solves 6-bit factorization problems, with the two correct factor pairs appearing in 67.5% of trials, and they argue that co-designing CMOS with V-MTJ entropy sources overcomes a key scaling bottleneck. If the approach scales as projected, it offers a path to single-chip probabilistic computers with millions of p-bits for hard combinatorial optimization.","feed_headline":"Spintronic ASIC with 1,143 p-bits factors integers","feed_subtitle":"Voltage-controlled magnetic tunnel junctions supply on-demand random bits, with a scaling path to millions of p-bits.","key_machinery":"The load-bearing mechanism has three parts: the p-bit update rule $m_i(t+1)=\\mathrm{sgn}[\\tanh(I_i/T)+r]$ with $I_i = h_i + \\sum_j J_{ij} m_j$, implemented digitally by a probabilistic logic unit (PLU) that maps 16 random bits to a sample from a scaled hyperbolic-arctangent distribution; the V-MTJ entropy source, where the voltage-controlled magnetic anisotropy effect lowers the energy barrier so the free layer relaxes in-plane and then re-enters one of two perpendicular states at random when the 10 ns pulse ends; and invertible logic gates built from AND, half-adder, and full-adder p-bit networks, whose ground states are the valid truth-table entries and which run equally well forward (multiplication), backward (factorization), or in division mode.","core_discovery":"The central discovery is a working hybrid probabilistic computer in which a custom CMOS ASIC and a spintronic entropy source are co-designed: the ASIC implements 1,143 p-bits whose update rule samples the distribution of an Ising Hamiltonian, and a single voltage-controlled MTJ, driven by 10 ns pulses, provides the stochastic bits that make the p-bits random. Because the V-MTJ is engineered with a high standby energy barrier and switches randomly only while the voltage pulse is applied, it can generate random bits on demand at high speed without the fine-tuned low-barrier devices required by stochastic-MTJ approaches. The authors validate the system on 6-bit integer factorization, report simulated 20-bit factorization, and estimate that porting the design to 45 nm and 7 nm nodes yields dense factorizers whose area scales toward millions of integrated p-bits.","pith_inferences":["A direct experimental check would feed the same ASIC with XOR4-processed bits and compare success rates; the paper's argument depends on raw bits being adequate even though only the XORed stream passes NIST tests.","The single demonstrated 6-bit problem (35 = 5 × 7) is one instance; a broader sample of semiprimes would separate architecture capability from instance-specific luck.","The area projections ignore PLU and random-number-generator area in serial designs; the authors acknowledge this, but for parallel-update designs the added area is nontrivial (12–18% in their estimates), so the 'millions of p-bits' figure is an upper bound for serial operation.","The V-MTJ is currently external and wire-bonded; until monolithic integration is shown, the claimed path to millions of p-bits rests on fabrication assumptions rather than measured results."],"forward_implications":["If the approach scales as projected, a single CMOS+V-MTJ chip could host millions of probabilistic bits, making Ising-machine solvers dense enough for practical combinatorial optimization problems.","Using several V-MTJs in parallel would move the throughput bottleneck from the entropy source to the CMOS logic, since p-bits can be updated in parallel with only modest area overhead.","The same invertible-logic architecture can perform multiplication and division as well as factorization, since the J matrix and h vector are fixed for a given bit width and only the clamped variables change.","V-MTJ entropy sources remove the need for the small, finely tuned energy barriers of stochastic MTJs, which should improve device-to-device uniformity and manufacturability in large arrays.","The synchronous ASIC approach consumes far less energy per random bit than FPGA or microcontroller implementations, per the comparison table."],"supporting_citations":[{"why":"Supplies the previous V-MTJ probabilistic computing work and device stack that this paper extends to a full ASIC.","marker":"[37]"},{"why":"Provides the sub-volt switching demonstration and large VCMA coefficient used for the present V-MTJ design.","marker":"[60]"},{"why":"Defines the p-bit update rule and the invertible logic concept on which the factorizer is built.","marker":"[30]"},{"why":"Establishes the theoretical basis for stochastic p-bits as invertible logic whose ground states are valid truth tables.","marker":"[49]"},{"why":"Sets integer factorization using stochastic MTJs as the benchmark problem and the approach this work improves upon.","marker":"[6]"},{"why":"Provides the superparamagnetic Ising machine architecture used as the main comparison point in the PIM table.","marker":"[33]"},{"why":"Supplies the NIST statistical test suite used to evaluate the randomness quality of the V-MTJ bit stream.","marker":"[65]"},{"why":"Provides the predictive 7 nm PDK used for the scaling projections to advanced nodes.","marker":"[66]"}],"fun_headline_variants":["On-demand spintronic randomness powers hybrid factoring chip","1,143 probabilistic bits factor integers on hybrid chip","Voltage-pulsed MTJs feed entropy to probabilistic ASIC","Co-designed CMOS and MTJs enable scalable probabilistic computing"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The raw, un-XORed V-MTJ bit stream, which fails most NIST randomness tests, still provides random bits of sufficient quality for the p-bit update rule to sample the correct distribution.","fun_headline_variants_meta":{"raw":{"variants":["On-demand spintronic randomness powers hybrid factoring chip","1,143 probabilistic bits factor integers on hybrid chip","Voltage-pulsed MTJs feed entropy to probabilistic ASIC","Co-designed CMOS and MTJs enable scalable probabilistic computing"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000501,"raw_usage":{"total_tokens":2466,"prompt_tokens":979,"completion_tokens":1487,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":595,"completion_tokens_details":{"reasoning_tokens":1422}},"tokens_in":595,"tokens_out":1487,"duration_ms":10487,"temperature":1.0,"reasoning_tokens":1422,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-11T18:18:50.784271+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Feed the same 6-bit factorization trials with the V-MTJ's raw bit stream and with its XOR4-processed stream, and compare the solution distributions: if the raw-stream success rate drops below the paper's measured 67.5% or the energy minima no longer match the correct factors, the raw entropy quality is insufficient.","supporting_citations":[{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Supplies the previous V-MTJ probabilistic computing work and device stack that this paper extends to a full ASIC."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Provides the sub-volt switching demonstration and large VCMA coefficient used for the present V-MTJ design."},{"cited_title":"Y ., Sutton, B","cited_arxiv_id":null,"evidence_quote":"Defines the p-bit update rule and the invertible logic concept on which the factorizer is built."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Provides the superparamagnetic Ising machine architecture used as the main comparison point in the PIM table."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Supplies the NIST statistical test suite used to evaluate the randomness quality of the V-MTJ bit stream."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Provides the predictive 7 nm PDK used for the scaling projections to advanced nodes."}],"review_version":1}