{"id":"2bea02f7-d350-450f-90fa-253dd9662369","arxiv_id":"2412.08302","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":5,"one_line_summary":"Quantum dots in a commercial 22 nm FD-SOI CMOS device can be formed, counted, and detuned using common-mode source/drain voltage and barrier gates, with QTCAD simulation qualitatively matching measurements.","lead":"A commercial 22 nanometer CMOS chip, cooled to 1 K, can trap electrons in one or two quantum dots using only ordinary gate voltages and a shared source-drain voltage. This shows that standard chip manufacturing and simulation could be used to design future quantum dot qubit arrays before fabrication.","discovery_kind":"new_application","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The claimed confinement inversion rests on simulated dot locations that transport data alone cannot verify; with 58 equally valid calibration sets in Appendix A, the between-gate double-dot regime is not shown to be robust.","rationale":"The paper is honest about its calibration and supplies genuine experimental evidence of one- and two-dot behavior: the charge-stability transitions for VQT1 = 0.33/0.34 V versus 0.35 V and the bias-triangle pairs in Sec. 6.3 are difficult to explain without at least one/two tunnel-coupled dots. However, the title and introduction make a stronger spatial claim—confinement under versus between gates—and the measured data do not locate the dots. The location rests on a QTCAD prediction whose parameter selection is explicitly degenerate (58 valid sets in Appendix A), and the paper does not show that the five-gate predictions are stable across that degeneracy. The proposed test would settle this: if the between-gate configuration persists across all equally valid calibrations, the concern is resolved; if not, the central claim should be weakened to dot-count control without the between-gate inversion. This supports the reader's CONDITIONAL verdict and does not change it.","tokens_in":12685,"tokens_out":6515,"duration_ms":67741,"concrete_test":"Re-run the five-gate QTCAD flat-band and detuning simulations for all 58 valid parameter sets from Appendix A (or a Latin-hypercube subset spanning the lever-arm spread). Record for each set: (i) the flat-band conduction/non-conduction boundary, (ii) whether the single-dot ground state lies under QT1 and the double-dot ground states lie between QT0/QT1 and QT1/QT2, (iii) the predicted detuning lever arms versus VQT0/VQT2. Compare with the measured boundary and the 0.2701 eV/V lever arm. If any equally valid set moves the double-dot ground states under the gates, or shifts the flat-band boundary by more than the experimental resolution, the spatial claim is not robust; the paper should then separate the experimentally verified dot-count evidence from the simulated dot-location evidence.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The paper's central novelty is the spatial claim that dots form either under or between the barrier gates and that the location can be inverted by biasing (Introduction; title). The experiments—flat-band sweeps (Sec. 6.1), charge stability diagrams (Sec. 6.2), and bias triangles (Sec. 6.3)—demonstrate the number of dots and their coupling, but they do not directly locate the dots. Section 6.1 states that a double dot is 'expected' in the bottom-left corner 'by comparing with simulation results,' so the between-gate assignment is entirely a model output. That model is calibrated on one minimum-size transistor: of 9702 parameter combinations, 58 passed the conduction-band criterion, and the final choice was based on matching a single Coulomb-diamond lever arm (Appendix A). The same parameters are then transferred to the five-gate array without re-fitting, and the 58 valid alternatives are not checked for consistency at the array level. Because the model is underconstrained, equally good fits to the calibration transistor could predict different flat-band boundaries, different dot locations, or different double-dot lever arms. If the between-gate configuration is not stable across the valid parameter sets—or disappears when disorder/stress (neglected in Sec. 2) are included—the confinement inversion claim lacks experimental grounding. This is a load-bearing gap, not a cosmetic one: the title's central phenomenon is a spatial prediction, and the transport data alone cannot distinguish it from a conventional under-gate double dot.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper presents a calibrated QTCAD model of a five-gate quantum dot array fabricated in a commercial 22 nm FD-SOI process, together with 1 K RF-reflectometry measurements. The model is calibrated on a minimum-size transistor (Appendix A) and predicts flat-band operation modes, formation of single or double quantum dots under or between gate electrodes, and effective plunger-like detuning via barrier gate voltages. Experimental results include flat-band sweeps, charge stability diagrams showing a VQT1-controlled single-to-double dot transition, and bias triangle pairs. The authors claim agreement between simulation and experiment, including a lever arm of 0.261 eV/V (simulated) versus 0.2701 eV/V (measured).","tokens_in":12918,"tokens_out":5793,"duration_ms":54031,"significance":"The manuscript addresses a timely topic—scalable qubit architectures in industry-standard CMOS—and provides a concrete device demonstration. Its strengths include a non-trivial quantitative comparison (the lever arm), a clear falsifiable prediction of single/double dot regimes, and the use of an independently calibrated parameter set rather than fitting the QDA data. However, the central spatial claim (dots confined between gates, with confinement inversion) is only indirectly verified by transport data, and the calibration's robustness is not established. The paper would be significantly strengthened by an ensemble analysis of the 58 valid parameter sets and by explicitly delineating which predictions are quantitatively, qualitatively, or only theoretically supported.","major_comments":[{"comment":"The title and Introduction claim 'full electrical control over the location of the quantum dots, either underneath or between the gate electrodes' and 'confinement inversion'. However, the transport measurements in Sec. 6 do not directly determine where the dots are located relative to the gates. In Sec. 6.1, the assignment of the double-dot region is explicitly made 'by comparing with the simulation results in Fig. 2(a)' rather than by an experimental observable. Flat-band sweeps, charge stability diagrams, and bias triangles demonstrate the number of dots and their coupling, but not whether the dots sit under QT1 or between QT0/QT1 and QT1/QT2. Thus the central spatial prediction is not experimentally verified; it is an interpretation of the model. This gap should be stated explicitly and the abstract's 'verification of all model predictions' should be softened accordingly.","section":"Sec. 6.1 and Introduction"},{"comment":"The calibration procedure yields 58 valid parameter sets from 9702 combinations, with the final choice based on matching a single Coulomb-diamond lever arm of the minimum-size transistor. The other 57 valid sets are not used to test the robustness of the QDA predictions. Since the model parameters (nsd, EWg, EWbg, nbg, spacer permittivity) are transferred to the five-gate array without re-fitting, equally good calibrations of the test transistor could yield different flat-band boundaries, different dot locations, or quantitatively different double-dot lever arms. The paper should show, for the ensemble of valid parameter sets, the spread in the predicted flat-band classification boundaries and in the double-dot lever arm, and confirm that the between-gate double-dot regime persists. Without this, the experimental agreement with one selected parameter set does not establish the predictive power claimed.","section":"Appendix A"},{"comment":"The bullet list states that mechanical stress in the silicon channel is neglected and that this 'can introduce a noticeable offset between the biasing voltages predicted by simulation and those used in the experiment.' The same section notes that charge disorder at interfaces is expected. These effects are not merely third-order: the flat-band boundaries in Fig. 2(a) and the dot-location classification in Tab. 3 depend on precise band-edge alignment between gate and inter-gate regions. The authors should estimate the expected voltage shifts from stress and disorder and show whether the between-gate double-dot regime survives such shifts, or explicitly limit their predictions to the disorder-free idealization.","section":"Sec. 2 (model assumptions)"},{"comment":"The phrase 'experimental verification of all model predictions' (Abstract, restated in Conclusions) overstates the evidence. The quantitative verification is limited to one lever arm (Sec. 4: 0.261 eV/V compared with 0.2701 eV/V), while the flat-band partitioning and charge stability diagrams are qualitative comparisons. The spatial dot-location predictions are not directly verified at all. The abstract and conclusions should be revised to describe which predictions are quantitatively confirmed, which are qualitatively supported, and which remain simulation-based.","section":"Abstract and Conclusions"}],"minor_comments":[{"comment":"The voltage definitions use primed and unprimed symbols (for example, V'_QR0 versus V_QR0) without an explicit statement that unprimed values are referenced to the source, although this is implied in the text. Please define this convention in the table caption.","section":"Table 1"},{"comment":"The term 'leverarm' is used as a single word; standard usage is 'lever arm', and this should be made consistent throughout the text.","section":"Sec. 4"},{"comment":"The caption states that measurements are shown for three values of VQT1 (0.33 V, 0.34 V, 0.35 V), but the panels (a)-(f) do not indicate which VQT1 value corresponds to which panel. Adding the value in each panel or in the caption will improve readability.","section":"Fig. 5"},{"comment":"The lever arm comparison of 0.261 eV/V with 0.2701 eV/V is stated to rely on 'supplementary materials' for the Coulomb diamond measurement and extraction method. It would be helpful to reference the specific appendix or figure where this is shown, as the appendices do not currently display the extraction.","section":"Sec. 4"},{"comment":"Reference [29] (arXiv:1202.6681) is cited for the lever arm extraction method; please verify that the published version is cited and that the method is briefly described in the text.","section":"Introduction"}],"recommendation":"major_revision","confidential_remarks":"The paper fits the journal's scope and the experimental dataset is valuable. The main concern is that the headline claim of spatial control (dots between gates, confinement inversion) is supported only by an under-constrained calibration. I would urge the editor to request the ensemble analysis across the 58 valid parameter sets before publication, as this is the key missing piece that would convert the qualitative claim into a robust one. The abstract and conclusion should also be aligned with the actual level of experimental verification."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Here's my read. The paper reports electrostatic single and double quantum dots in a commercial 22 nm FDSOI process, controlled by a common-mode source/drain voltage plus barrier gates, with no dedicated plungers. That combination is genuinely new in this commercial platform, and the use of a calibrated QTCAD model transferred from a minimum-size transistor to a five-gate array is the right approach. The lever-arm prediction for the double-dot detuning, 0.261 eV/V, matches the measured 0.2701 eV/V closely; that is a real quantitative point in its favor. The flat-band partitioning, charge-stability diagrams, and bias triangles are all consistent with single- and double-dot formation, and the authors are upfront about neglected mechanical stress and charge disorder.\n\nThe soft spots are significant but not fatal. The abstract overclaims: 'experimental verification of all model predictions' is not supported. The only quantitative comparison is that lever arm; the rest are qualitative classifications. More importantly, the paper's central novelty—confinement inversion, i.e., dots forming between gates rather than under them—is inferred entirely from simulation. Transport data alone cannot locate the dots. The calibration on the minimum-size transistor yields 58 valid parameter sets, and the authors pick the closest to one Coulomb-diamond lever arm. They do not check whether those other valid sets still predict the between-gate regime in the five-gate array. That gap is real, and the stress-test note is right to flag it. It is not fatal: the double-dot signatures are solid, and the lever-arm agreement gives some confidence in the model. But the spatial claim needs a sensitivity analysis across the valid calibration sets.\n\nAlso, no code, parameter files, or raw data are provided, which limits reproducibility. The bias triangles are on a 'similar' device, not the exact one in the main measurements—minor, but should be clarified.\n\nWho is this for? People working on CMOS-based quantum-dot qubits, especially those interested in simulation-driven design in commercial processes. They will want to read it despite the overclaim. It deserves a serious referee. The authors should be asked to temper the abstract, add a robustness analysis of the calibration choices, and provide raw data. With those changes it could be a useful contribution.","headline":"Solid experimental demonstration of plunger-free quantum-dot control in a commercial 22 nm FDSOI process, with one real quantitative lever-arm match; the headline spatial claim of confinement inversion is simulated, not directly measured, and needs a robustness check.","tokens_in":13576,"tokens_out":3910,"would_cite":true,"duration_ms":40463,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"Forming and controlling single and double quantum dots in a commercial 22 nm FD-SOI CMOS channel is possible with common-mode and barrier-gate voltages alone.","keywords":["quantum dots","FD-SOI CMOS","common-mode control","electrostatic confinement","quantum dot array","cryogenic TCAD simulation","charge stability diagrams","bias triangles"],"falsifier":"Measure the flat-band charge-stability map of the same five-gate device at 1 K and compare the slope separating conducting from non-conducting states and the $V_{\\mathrm{QT0}}$/$V_{\\mathrm{QT2}}$ lever arm on dot energies with the simulated values; a deviation beyond the calibration uncertainty, or a single-dot pattern where the model predicts a double dot, would falsify the claim.","tokens_in":12447,"feed_emoji":"⚛️","tokens_out":8124,"duration_ms":78619,"temperature":0.7,"pith_summary":"This paper sets out to show that a standard commercial 22 nm fully depleted silicon-on-insulator (FD-SOI) CMOS transistor, with no changes to the foundry process, can host electrostatically defined quantum dots. The claim is that a common-mode voltage applied to source and drain, together with a back-gate voltage, forms the dots, and that the barrier-gate voltages determine whether one or two dots appear and where they sit. Because the device has no dedicated plunger electrodes between gates, the paper proposes that the barrier gates themselves act as effective plungers for detuning the dot energy levels. The authors support this with a calibrated cryogenic simulation of the conduction band and with 1 K measurements showing flat-band partitioning, charge-stability diagrams, and bias-triangle pairs. If correct, this would make commercial CMOS a practical route to scalable semiconductor qubit arrays without custom fabrication.","feed_headline":"Commercial CMOS chip forms controllable quantum dots at 1 K","feed_subtitle":"Standard 22 nm FD-SOI confines and detunes quantum dots using only common-mode and gate voltages.","key_machinery":"The load-bearing object is a calibrated cryogenic technology-computer-aided-design (TCAD) model of the device, which solves the Poisson and self-consistent Poisson–Schrödinger equations to compute the conduction band, single-electron wavefunctions, lever arms, and sequential tunnelling. Calibration is performed on a minimum-size single-gate 22 nm FD-SOI transistor whose single Coulomb diamond fixes the doping, work functions, and spacer permittivity, and these parameters are then transferred to the five-gate array without re-fitting. The model is used to build a flat-band classification of device states, and the key control identity is the common-mode voltage $V_{\\mathrm{CM}} = (V_{\\mathrm{QR0}}' + V_{\\mathrm{QR1}}')/2$, which acts as a global plunger, while the barrier-gate voltages $V_{\\mathrm{QT0}}$ and $V_{\\mathrm{QT2}}$ serve as local plungers for detuning the two dots.","core_discovery":"The paper's central discovery is confinement inversion in a five-gate FD-SOI quantum dot array: by sweeping the common-mode voltage $V_{\\mathrm{CM}}$ against the equal barrier-gate voltage $V_{\\mathrm{QT}}$, the conduction band can be classified into four states—conductive, wells between gates, wells under gates, and non-conductive. In the two-dot state, quantum dots form between adjacent barrier gates, and the voltages $V_{\\mathrm{QT0}}$ and $V_{\\mathrm{QT2}}$ act as independent plungers for the left and right dots, with a simulated lever arm of about 0.261 eV/V that matches the measured value of about 0.2701 eV/V. Raising the central barrier voltage $V_{\\mathrm{QT1}}$ converts the double dot into a single dot, and the measured charge-stability diagrams and bias-triangle pairs confirm the predicted single- and double-dot regimes at 1 K.","pith_inferences":["If this control scheme holds in other 22 nm FD-SOI nodes, the per-qubit gate count could drop because plunger electrodes and their routing are unnecessary, easing the wiring bottleneck in large arrays.","The confinement inversion between wells under gates and wells between gates is a natural switch between a single-qubit mode and a tunnel-coupled two-qubit mode, so the same device might serve both storage and coupling without redesign.","A testable extension is to measure charge noise or spin decoherence as the back gate moves the dot away from the top silicon-oxide interface; the paper hints this could reduce the charge noise seen in its older-generation data."],"forward_implications":["A commercial, unmodified 22 nm FD-SOI process can host electrostatically defined single and double quantum dots at 1 K without dedicated plunger electrodes.","The number of dots is controlled by one voltage: increasing the central barrier-gate voltage $V_{\\mathrm{QT1}}$ switches the device from a double-dot to a single-dot charge-stability pattern.","Energy-level detuning of the double dot is achieved by sweeping $V_{\\mathrm{QT0}}$ and $V_{\\mathrm{QT2}}$, with a lever arm of about 0.26 eV/V that is consistent between simulation and experiment.","The calibrated TCAD workflow can predict quantum-dot operating regions before fabrication, which the paper presents as a route to design and improve commercial CMOS qubit arrays."],"supporting_citations":[{"why":"supplies the cryogenic TCAD simulation toolkit used for all Poisson and Schrödinger calculations","marker":"[16]"},{"why":"provides the cryogenic TCAD modelling method for gated quantum dots","marker":"[17]"},{"why":"applies 3D quantum TCAD to interpret FD-SOI quantum dot transport, the direct predecessor of this calibration","marker":"[18]"},{"why":"supports the TCAD assumptions on p-doped polysilicon gates and explains why mechanical stress is neglected","marker":"[19]"},{"why":"defines the charge-stability diagrams and bias-triangle signatures used to identify single and double quantum dots","marker":"[23]"},{"why":"supplies the radio-frequency reflectometry technique used for dispersive charge sensing","marker":"[22]"},{"why":"documents the 22 nm FD-SOI process with back-biasing capability that the device is built in","marker":"[4]"}],"fun_headline_variants":["Common-mode voltage inverts quantum dot confinement in CMOS","CMOS dots flip confinement with common-mode voltage","FD-SOI CMOS forms and detunes quantum dots at 1 K","Confinement inversion in CMOS quantum dots controlled by common-mode voltage","Barrier gate toggles CMOS quantum dots between single and double"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The whole prediction depends on parameters calibrated on one minimum-size single-gate transistor being transferred unchanged to the larger five-gate array, while the model neglects mechanical stress and charge disorder; if those effects shift voltages significantly, the predicted dot positions and the claimed confinement inversion would not reproduce.","fun_headline_variants_meta":{"raw":{"variants":["Common-mode voltage inverts quantum dot confinement in CMOS","CMOS dots flip confinement with common-mode voltage","FD-SOI CMOS forms and detunes quantum dots at 1 K","Confinement inversion in CMOS quantum dots controlled by common-mode voltage","Barrier gate toggles CMOS quantum dots between single and double"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000965,"raw_usage":{"total_tokens":4085,"prompt_tokens":898,"completion_tokens":3187,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":514,"completion_tokens_details":{"reasoning_tokens":3102}},"tokens_in":514,"tokens_out":3187,"duration_ms":23741,"temperature":1.0,"reasoning_tokens":3102,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-11T17:57:43.645962+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Measure the flat-band charge-stability map of the same five-gate device at 1 K and compare the slope separating conducting from non-conducting states and the $V_{\\mathrm{QT0}}$/$V_{\\mathrm{QT2}}$ lever arm on dot energies with the simulated values; a deviation beyond the calibration uncertainty, or a single-dot pattern where the model predicts a double dot, would falsify the claim.","supporting_citations":[{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"supplies the cryogenic TCAD simulation toolkit used for all Poisson and Schrödinger calculations"},{"cited_title":"Introducing Technology Computer-aided Design (TCAD): Fundamentals, Simulations and Applications (Pan Stanford Publishing Pte","cited_arxiv_id":null,"evidence_quote":"supports the TCAD assumptions on p-doped polysilicon gates and explains why mechanical stress is neglected"},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"defines the charge-stability diagrams and bias-triangle signatures used to identify single and double quantum dots"}],"review_version":1}