{"id":"5cb1908a-953a-4ba0-9dfd-99aed8e4d808","arxiv_id":"2412.15888","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":4.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":3,"one_line_summary":"SAPPI-1 and SAPPI-2 are serial IMPLY approximate full adders that save 39 to 41 percent steps and 39 to 42 percent energy versus exact addition while preserving image and MNIST accuracy for partial approximation.","lead":"Two new memristor-based approximate adders, SAPPI-1 and SAPPI-2, cut the number of computation steps by 39 to 41 percent and energy by 39 to 42 percent in ripple-carry adders while introducing small arithmetic errors. They are tested in image processing and MNIST neural-network tasks, where the errors stay acceptable for partial approximation.","discovery_kind":"extension","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Energy-saving claim depends on isolated-cell SPICE energies; a shared-line serial IMPLY crossbar may not have additive per-bit energy.","rationale":"The central claim pairs a step-count reduction with an energy reduction. The step-count reduction of 39%-41% follows directly from the algorithmic step counts (4 or 5 steps per approximate bit versus 22 for the exact adder) and is therefore robust to device modeling. The energy reduction, however, is the weaker half: it is obtained by summing per-full-adder energies from isolated LT-SPICE simulations, which may not capture the physics of a full serial crossbar where every operation drives a shared line and where additional memristors contribute parasitic and sneak-path dissipation. The reader's weakest assumption identified exactly this additivity and device-transfer issue, and I agree. The concern does not by itself force rejection, because the step-count argument is strong and the relative savings may survive a more realistic crossbar model; it does require an additional validation step before the quantitative energy claim can be accepted. The paper also contains real internal inconsistencies, notably Eqs. (1)-(4) not matching the truth tables, but those do not directly threaten the measured step/energy comparison as much as the missing crossbar-level energy validation does. I therefore keep the reader's CONDITIONAL verdict unchanged but recommend the crossbar-level energy check as the decisive experiment.","tokens_in":11478,"tokens_out":24567,"duration_ms":225867,"concrete_test":"Build an 8-bit serial IMPLY crossbar in SPICE using the same VTEAM parameters, shared resistor RG, and 30 us pulses, with 19 memristors for the exact/SAPPI-2 configuration and 23 for SAPPI-1. Run the mixed 4/8 RCA (4 SAPPI bits plus 4 exact bits) over a representative sample of input pairs, measuring total supply energy per addition. Compare the measured total with the sum predicted by Eqs. (5)-(6). If the measured energy implies a savings versus the exact 176-step baseline that differs by more than 10 percentage points from the claimed 39%-42%, the additive energy model is invalid; if it matches, the energy claim is supported.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The 39%-42% energy reduction is computed from Eqs. (5)-(6), which use per-full-adder energy values measured in LT-SPICE for isolated cells: 0.7980 nJ for SAPPI-1, 1.0919 nJ for SAPPI-2, and 4.8250 nJ for the exact adder. In the serial IMPLY topology, all memristors share a common row/word-line resistor, so every IMPLY or FALSE step applies voltages across the whole array. Sneak-path currents, shared-line capacitance, and the extra work memristors needed by SAPPI-1 (2n+k+3 vs 2n+3) are not included in the isolated-cell simulations. The total energy of an n-bit RCA is therefore not necessarily the sum of these per-bit values. The paper's own footnote reports unexplained simulation discrepancies versus published values for [23] and [32], leaving the baseline calibration unverified. If a realistic crossbar adds per-step overhead that is not proportional to active-cell count, the measured energy savings versus the exact adder could be materially below 39%-42%, even though the 39%-41% step reduction is algorithmic and likely robust.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"This manuscript proposes two approximate full adders, SAPPI-1 and SAPPI-2, for serial memristive IMPLY logic. SAPPI-1 uses 4 steps per bit and stores the Sum in a work memristor while preserving the A and B operands; SAPPI-2 uses 5 steps per bit and stores the Sum in the A memristor. The authors verify all eight input combinations with LT-SPICE using the VTEAM model under up to +-30% resistance variation, report per-cell energy and step counts, and combine them in linear RCA formulas to claim 39%-41% step and 39%-42% energy reductions against an exact serial adder. They then evaluate partially approximated RCAs in three image-processing tasks using PSNR/MSSIM and in FC-NN/CNN classifiers on MNIST, reporting application-level energy and step savings while maintaining accuracy.","tokens_in":11685,"tokens_out":7317,"duration_ms":66519,"significance":"If the step and energy claims survive scrutiny in a realistic crossbar setting, the contribution is useful: a very short 4-step per-bit serial IMPLY adder with an acceptable error profile for image processing, plus one of the first demonstrations of approximate IMPLY adders in CNN inference. The algorithmic step count reduction is well defined and independent of device models, and the SPICE verification with resistance variation is a concrete strength. The paper is also honest in reporting that its re-simulations of baseline circuits do not match the published values. The main obstacles are the incorrect Boolean equations for Sum and the unvalidated additive energy model, both of which must be fixed before the headline quantitative claims can be accepted.","major_comments":[{"comment":"Equation (1) states Sum = B -> A = AB. In Boolean algebra B -> A is not AB but not-B or A, and the step sequence in Table II actually implements M = not(A) or not(B) = NAND(A,B), which is what the truth table shows. Equation (3) is likewise inconsistent with Table III: step 5 writes C' -> A, which yields Sum = A or not(C), not AB + C + A. The authors should correct these Boolean expressions and the notation B -> A, since the step sequences and truth tables are otherwise self-consistent.","section":"Eq. (1) and Eq. (3), Section III-B/III-C"},{"comment":"The energy claims rest on per-bit energies measured from isolated two-memristor cells and then summed linearly over k approximate and n-k exact bits. In a real serial IMPLY crossbar, cells share word-line and bit-line drivers, so every IMPLY or FALSE step also charges shared lines and can create sneak-path currents that are absent in isolated-cell LT-SPICE runs. The footnote in Table VII already reports unexplained discrepancies between the authors' re-simulations and the published values for [23] and [32]. Because the 39%-42% energy reduction is a headline result, the authors should either simulate a multi-bit crossbar or provide a concrete overhead model demonstrating that shared-line effects do not materially change the claimed savings.","section":"Section V-A, Eqs. (5)-(6)"},{"comment":"The paper states that the proposed approach is the first adder algorithm that maintains all input states after the operation. This is not literally true: SAPPI-1 overwrites the carry input C in step 4, and SAPPI-2 additionally overwrites A in step 5. If the claim refers only to the A and B operands, it should be stated that way; as written, it overstates the property.","section":"Section III-A and Introduction"},{"comment":"The application-level energy and step savings for the CNN inference (296 mJ, 1.33 billion steps) and for image processing are computed by extrapolating per-bit adder savings through the shift-and-add multiplier, but the paper does not describe the calculation or account for the cost of loading operands, storing partial products, or moving data between memristors in the serial topology. The authors should provide the derivation for these application-level numbers, or clearly state which overheads are excluded, so that the ML and image-processing savings are reproducible.","section":"Section VII-B and Table VIII"}],"minor_comments":[{"comment":"The time axis label reads 'Time in s', but the simulations use 30 us pulses; the label should be 'Time in us' or the axis should be rescaled.","section":"Figs. 2 and 3"},{"comment":"The text in Section III-B says an n-bit addition using only SAPPI-1 requires 3n+1 memristors, while Section V-C and Table VII report 2n+k+3 memristors for a mixed RCA; these counts should be reconciled with a clear definition of n and k.","section":"Section III-B and Section V-C"},{"comment":"References [20] and [35] appear to be the same paper and should be merged or distinguished.","section":"References"},{"comment":"The sentence 'our approach is not able to reach the 30dB threshold of PSNR with 5/8 approximated adders' should specify that this refers to the evaluated image-processing tasks, since the ML experiments still show acceptable accuracy at some approximation degrees.","section":"Section VI-B"},{"comment":"The text gives accuracy thresholds but not the exact accuracy values or the formula used to compute energy savings for the FC-NN and CNN experiments; adding a short description of the calculation and a table of the accuracy numbers would improve reproducibility.","section":"Section VII and Fig. 5"}],"recommendation":"major_revision","confidential_remarks":"The paper's central step-count contribution is clear and likely sound, but the energy comparison currently depends on the authors' own re-simulations of the baselines, and the paper admits it cannot explain why those differ from the published values. That is a reproducibility risk that should be resolved before publication. The strong presence of self-authored baselines is not disqualifying, but it makes the unexplained discrepancy more consequential."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Two new serial IMPLY approximate full adders, SAPPI-1 and SAPPI-2, with 4 and 5 steps per bit. That step count is genuinely lower than the cited SIAFA (8) and SAFAN (7), and the SPICE verification is solid: all eight input combinations, with up to ±30% resistance deviation, match the intended truth tables. The step reduction over the exact serial adder is algorithmic and will hold up. The energy-savings claim, however, is softer than the abstract suggests. The 39%-42% figure comes from summing isolated-cell LT-SPICE energies (Eqs. 5-6). In a real serial IMPLY crossbar, all cells share row/word lines, so per-step energy need not be additive; sneak paths and line capacitance could dilute the savings. The paper neither models this nor discusses it. The stress-test note on this point lands.\n\nThe paper also has a few self-inflicted wounds. The boolean equations in Section III are wrong: Eq. (1) says Sum = B→A = AB, but B→A is ¬B∨A; Eq. (2) similarly mis-simplifies (B→A)→C as AB+C. The truth tables and step sequences are correct — this is a derivation error, but it sits at the heart of the paper and must be fixed. The 'first adder that maintains all input states' claim is overstated: C is overwritten; only A and B are preserved. And the SoA comparison rests on re-simulated baselines that disagree with the published values, with the authors unsure why. That honesty is commendable, but it leaves the 9-13% energy improvement over SAFAN uncalibrated.\n\nWhat the paper does well: the designs are simple, the error analysis for partially approximated RCAs is sensible, and the application studies (image addition, grayscale, Gaussian blur, MNIST CNN) show the adders work at practical approximation levels. No code or netlists are provided, which is a reproducibility gap but not fatal.\n\nWho this is for: researchers in memristive stateful logic and approximate in-memory arithmetic. The step-count contribution is real and worth building on. I would send it to peer review with heavy revision required: correct the equations, tone down the 'first' claim, and either model crossbar energy or explicitly scope the energy numbers as isolated-cell estimates. The core idea is plausible; the presentation and the energy modeling need work.","headline":"Two new serial IMPLY approximate adders with real step-count wins, but the energy-savings claim rests on an isolated-cell model and the boolean equations have errors that need fixing.","tokens_in":12292,"tokens_out":4284,"would_cite":false,"duration_ms":35224,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"This paper claims that two serial IMPLY-based approximate full adders, SAPPI-1 and SAPPI-2, cut ripple-carry adder steps by 39%–41% and energy by 39%–42% while keeping image quality and MNIST accuracy intact.","keywords":["IMPLY logic","memristor","approximate computing","in-memory computing","full adder","ripple carry adder","image processing","MNIST"],"falsifier":"Build an 8-bit ripple-carry adder with four SAPPI-1 (or SAPPI-2) low bits and four exact bits on a real integrated memristive crossbar, run all 65,536 input pairs, and compare the total cycle count and energy to the exact 22n-step adder; if the measured savings is below 39% in either steps or energy, because of extra carry-propagation cycles, signal restoration, or non-additive per-bit energy, the paper's central quantitative claim is refuted.","tokens_in":2030,"feed_emoji":"🧮","tokens_out":3112,"duration_ms":110753,"temperature":0.7,"pith_summary":"This paper tries to establish that approximate computing and memristor-based in-memory computing can be combined in a single adder design without sacrificing the quality of real workloads. It proposes two serial IMPLY-based approximate full adders, SAPPI-1 and SAPPI-2, which, when placed in the low bits of a ripple-carry adder, use 39%–41% fewer steps and 39%–42% less energy than the exact serial IMPLY adder. The point of caring is that addition is the workhorse of image processing and neural-network inference, so a cheap approximate adder could reduce the energy and latency of those applications while living inside memory, avoiding the Von Neumann bottleneck. The paper supports this with circuit-level LT-SPICE simulations, error metrics, image-processing quality metrics, and MNIST case studies.","feed_headline":"Approximate IMPLY adders cut energy and steps by 40 percent","feed_subtitle":"The SAPPI adders keep PSNR above 30 dB and MNIST accuracy intact with up to half the RCA approximated.","key_machinery":"In the serial IMPLY topology, one IMPLY or FALSE operation runs per cycle and the second operand is overwritten. SAPPI turns this overwrite into the computation: reset the work memristor $M$ to 0 (FALSE), then $A \\to M$ gives $\\overline{A}$, then $B \\to M$ gives $\\overline{AB}$ (the Sum for SAPPI-1), then $M \\to C$ gives $AB + C$ (the carry-out for both). SAPPI-2 adds a fifth step, $C' \\to A$, which stores the Sum in the A-memristor and changes the error pattern so that the '001' mistake is partially mitigated. The key object is the reusable work memristor plus the carry-in memristor that is overwritten once, giving a defined error rate of 1/8 for Cout and 4/8 for Sum.","core_discovery":"The central discovery is that the destructive overwrite behavior of IMPLY logic can itself be used as a design resource rather than a liability. By sequentially implicating the two input memristors into a reset work memristor, the algorithms form the sum as a NAND of the inputs in four steps (SAPPI-1) or five steps (SAPPI-2), and form the carry-out by implicating that intermediate result into the carry-in memristor. The deliberate approximation is concentrated: the carry-out is wrong only for the input pattern '001', and the sum is wrong in four of eight input combinations. SAPPI-1 preserves both input states after the operation, which the authors describe as the first IMPLY adder to do so, at the cost of extra work memristors; SAPPI-2 writes the sum into the A-memristor, which matches the exact serial algorithm's interface. The paper claims these designs beat the exact adder by 39%–42% in energy and 39%–41% in steps, beat the state-of-the-art approximate IMPLY adders by 9%–13% in energy and 7%–10% in steps, keep PSNR above 30 dB in three image-processing tasks with up to half of the RCA approximated, and preserve MNIST accuracy in a CNN with up to four approximated adders.","pith_inferences":["The paper does not explore composing SAPPI with error-correction or prediction circuits: since the only carry error is the '001' pattern, a cheap decoder could detect and fix most of the damage, potentially extending the acceptable approximation degree beyond 4/8.","If the additive energy model holds on integrated devices, the same percentage savings should carry over to wider adders and to multipliers, so a natural next check is measuring a full 32-bit RCA or a multiplier in an integrated memory array rather than extrapolating from per-bit simulation.","Because SAPPI-1 preserves both operands, it may enable iterative in-memory algorithms such as accumulation or averaging that reuse the same inputs many times; the paper only demonstrates single-pass addition and multiplication, leaving this potential implicit.","The trade-off between SAPPI-1's lower energy per bit and SAPPI-2's better error metrics at high approximation degrees suggests a runtime-selectable knob within the same adder family, which could be tuned per bit based on application sensitivity."],"forward_implications":["In an n-bit ripple-carry adder with k approximated low bits, SAPPI-1 gives $4k + 22(n-k)$ steps and SAPPI-2 gives $5k + 22(n-k)$ steps, versus $22n$ for the exact adder, yielding the claimed 39%–41% step savings.","For image addition and grayscale conversion, both algorithms keep PSNR above 30 dB with up to 4/8 approximated adders; for Gaussian smoothing, the threshold is reached with up to 8/20 approximated adders.","In MNIST classification with a partially approximated 20-bit RCA inside a shift-and-add multiplier, a fully connected network keeps accuracy up to six approximated adders and a LeNet-5-style CNN up to four approximated adders, with SAPPI-1 saving up to 296 mJ (21%) and 1.33 billion steps (20%) per CNN inference.","Because SAPPI-1 preserves both input memristor states, the same input data can be reused for later computations without reloading, which prior IMPLY adder designs cannot do.","The approximation degree is reconfigurable per run because IMPLY adders are algorithm-defined, so the same hardware can trade accuracy for efficiency depending on the application's error tolerance."],"supporting_citations":[{"why":"Supplies the exact serial IMPLY full-adder algorithm whose 22n steps and $2n+3$ memristors are the baselines the paper improves upon.","marker":"[19]"},{"why":"Supplies the VTEAM simulation parameters and the SIAFA approximate adders used as state-of-the-art comparisons for energy, steps, and area.","marker":"[23]"},{"why":"Supplies SAFAN, the fastest and most energy-efficient SoA approximate serial adder that SAPPI is compared against for the 7%–10% fewer steps and 9%–13% energy improvement claims.","marker":"[32]"},{"why":"Supplies the SPICE implementation of the VTEAM memristor model used for all circuit-level simulations.","marker":"[33]"},{"why":"Supplies the discrete-device memristor parameters that the VTEAM model is fitted to in the simulations.","marker":"[34]"},{"why":"Establishes material implication (IMPLY) as a stateful logic operation on memristors, the operation family the adders are built from.","marker":"[6]"},{"why":"Provides the 30 dB PSNR threshold used to judge whether the approximate image-processing results are acceptable.","marker":"[31]"},{"why":"Supplies the LeNet-5-inspired CNN architecture used for the MNIST machine-learning case study.","marker":"[39]"}],"fun_headline_variants":["Memristor IMPLY adders cut energy and steps 40%","Approximate memristor adders: 40% energy and step savings","SAPPI adders: 40% less energy, 40% fewer steps","In-memory computing adders save 40% energy and steps","IMPLY adders approximate for 40% efficiency gain"],"cache_read_input_tokens":14464,"weakest_assumption_plain":"The savings figures assume that the energy and step counts of a whole ripple-carry adder are just the sums of the per-bit values, with no extra work when a carry passes between slices, and that the behavior measured on discrete memristors carries over to integrated devices; the authors note integrated devices should be faster and use less power, but the 39%–42% numbers depend on that transfer.","fun_headline_variants_meta":{"raw":{"variants":["Memristor IMPLY adders cut energy and steps 40%","Approximate memristor adders: 40% energy and step savings","SAPPI adders: 40% less energy, 40% fewer steps","In-memory computing adders save 40% energy and steps","IMPLY adders approximate for 40% efficiency gain"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000661,"raw_usage":{"total_tokens":3100,"prompt_tokens":1103,"completion_tokens":1997,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":719,"completion_tokens_details":{"reasoning_tokens":1900}},"tokens_in":719,"tokens_out":1997,"duration_ms":14643,"temperature":1.0,"reasoning_tokens":1900,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-11T11:00:14.456026+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Build an 8-bit ripple-carry adder with four SAPPI-1 (or SAPPI-2) low bits and four exact bits on a real integrated memristive crossbar, run all 65,536 input pairs, and compare the total cycle count and energy to the exact 22n-step adder; if the measured savings is below 39% in either steps or energy, because of extra carry-propagation cycles, signal restoration, or non-additive per-bit energy, the paper's central quantitative claim is refuted.","supporting_citations":[{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Supplies the exact serial IMPLY full-adder algorithm whose 22n steps and $2n+3$ memristors are the baselines the paper improves upon."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Supplies the VTEAM simulation parameters and the SIAFA approximate adders used as state-of-the-art comparisons for energy, steps, and area."},{"cited_title":"Asgari et al","cited_arxiv_id":null,"evidence_quote":"Supplies SAFAN, the fastest and most energy-efficient SoA approximate serial adder that SAPPI is compared against for the 7%–10% fewer steps and 9%–13% energy improvement claims."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Supplies the SPICE implementation of the VTEAM memristor model used for all circuit-level simulations."},{"cited_title":"Last accessed Feb 2024","cited_arxiv_id":null,"evidence_quote":"Supplies the discrete-device memristor parameters that the VTEAM model is fitted to in the simulations."},{"cited_title":"Borghetti et al","cited_arxiv_id":null,"evidence_quote":"Establishes material implication (IMPLY) as a stateful logic operation on memristors, the operation family the adders are built from."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Provides the 30 dB PSNR threshold used to judge whether the approximate image-processing results are acceptable."},{"cited_title":"Lecun et al","cited_arxiv_id":null,"evidence_quote":"Supplies the LeNet-5-inspired CNN architecture used for the MNIST machine-learning case study."}],"review_version":1}