{"id":"35c3d0e1-c86b-4657-b208-faf3b6627d32","arxiv_id":"2501.05667","paper_version":2,"verdict":"REJECT","confidence":"MODERATE","novelty_score":4.0,"correctness_risk":"high","formal_verification":"none","parameter_count":5,"one_line_summary":"A GNN-based global placer that imitates DREAMPlace placements and fine-tunes per circuit, claiming speedups and quality gains that are partly contradicted by its own tables.","lead":"TransPlace uses a graph neural network to generate chip layouts for circuits with millions of components, then refines them with a traditional optimizer. The authors report faster placement with less congestion and better timing than a standard placer, but the gains appear to depend on per-circuit tuning and the tables do not always match the abstract.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Claimed gains may stem from per-circuit fine-tuning, not transferable GNN knowledge; the GNN-only ablation is unrouteable, so the comparison does not isolate the learned contribution.","rationale":"The reader's weakest assumption was that DREAMPlace default settings versus TransPlace's per-circuit fine-tuning confounds the comparison; I agree this is the load-bearing vulnerability. The paper's central contribution is transferable learning, not a better optimizer. Section 2.5 and Eq. 31 show fine-tuning is a standard analytic placement objective (wirelength plus ePlace-style density); Section 3.1 claims the GNN is trained on DREAMPlace outputs. The only place the learned representation can help is the initialization before fine-tuning and perhaps the per-circuit offsets. But Tables 7-10 reveal the offsets and optimizer hyperparameters are tuned per test design. Because DREAMPlace is not given the same tuning budget, the comparison conflates 'learned warm start' with 'extra per-circuit hyperparameter search.' Table 11 is decisive evidence that the inductive stage is not independently competitive: without fine-tuning, overflow increases dramatically and large circuits fail to route. Thus the headline result rests on the fine-tune stage, whose settings are not controlled.\n\nI add a second concrete concern about train/test integrity. The authors never state which five DAC2012 circuits are used for training, and Table 3 reports on ten DAC2012 designs; the ISPD2015 set includes mgc_superblue12/14/16/19, likely related to DAC2012 superblue12/14/16/19. If any of those are in the training set, the 'unseen circuits' claim is unverified on those rows. This does not replace the tuning confound but makes disclosure essential.\n\nThe abstract's 5% wirelength claim is not supported by the tables; Tables 1-2 averaged ratios are 0.98 for RWL (2% better), with numerous circuits worse. This supports the reader's conclusion that the paper overstates results, but the most load-bearing issue remains the confounded comparison.\n\nI do not question the legitimacy of the technical components: Netlist Graph, Cell-flow, and TPGNN are interesting, and the optimality analyses in Appendix D are useful. The problem is evidentiary. As written, the central transferable-superiority claim is not isolated from the tuned optimizer. The proposed controlled comparison would settle whether the learned initialization contributes anything beyond a random start with the same per-circuit tuning budget.","tokens_in":22658,"tokens_out":5142,"duration_ms":50299,"concrete_test":"Give DREAMPlace exactly the per-circuit settings in Tables 7-9 (same learning rate, density weight, iteration limit, theta, and initial Delta_x/Delta_y) starting from random initialization, and compare OVFL, RWL, and runtime on every ISPD2015/ISPD2019 test circuit. If DREAMPlace matches or beats TransPlace under equal tuning, the GNN warm start is not the source of the claimed speedup or quality gains; if TransPlace still wins, the transferable-knowledge claim survives this particular attack.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central claim is that a GNN trained on five DREAMPlace placements can transfer to unseen circuits and beat DREAMPlace. The decisive assumption is that the quality advantage comes from the learned inductive placement. The paper's own evidence undercuts this. TransPlace's final output is a DREAMPlace-style optimizer (NAG, Eq. 31) warm-started by the GNN and run with per-circuit hyperparameters: Tables 7-10 give different learning rates (1e-4 to 3e-1), density weights (8e-9 to 8e-3), iteration limits (150 to 2000), RePlAce_UPPER_PCOF, theta, and hand-set initial offsets Delta_x/Delta_y for every test design, while DREAMPlace runs with default settings. Table 11 shows that without fine-tuning, TransPlace's inductive output has overflow up to 1.8 million (vs. 5-41 for DREAMPlace) and often fails to route, so the GNN alone is far worse. Therefore every claimed OVFL/RWL/RT improvement could be produced by the aggressively tuned fine-tune stage rather than by transferable placement knowledge. A secondary concern is train/test integrity: the five DAC2012 training circuits are never named, while Table 3 evaluates ten DAC2012 designs and ISPD2015 contains superblue netlists with the same names; without a disclosed split, the 'unseen circuit' claim is unverified. The abstract's 5% wirelength reduction is also inconsistent with the tables' 0.98 average ratio and many rows where RWL is worse.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"TransPlace is a two-stage global placement framework. The first stage uses a graph neural network (TPGNN) applied to a hierarchical 'Netlist Graph' and a 'Cell-flow' DAG to predict relative cell positions in an SE(2)-invariant representation, after training on a few DREAMPlace-generated placements. The second stage, 'Circuit-adaptive Fine-tuning', refines the inductive placement by gradient-based optimization of wirelength and density objectives with Nesterov acceleration. The paper claims that TransPlace can place unseen circuits with 1.2x speedup, 30% less congestion, 9% better timing, and 5% shorter wirelength compared to state-of-the-art analytical placers, and that it is the first learning-based approach for large-scale global placement in continuous space.","tokens_in":22989,"tokens_out":4590,"duration_ms":39978,"significance":"If the claims were supported, TransPlace would be a significant contribution to learning-based VLSI placement: it combines a scalable hierarchical graph representation, a novel cell-flow relative-position encoding, and a complexity-optimal decoding scheme, with an open-source implementation. The algorithmic ideas are well motivated and the authors provide complexity arguments for the graph construction and message passing. However, the central empirical claim—that a GNN trained on a few DREAMPlace placements transfers to unseen circuits and beats the algorithm that generated its training data—is not established by the evidence. The comparison is clouded by per-circuit tuned fine-tuning, the GNN-only ablation fails to route, and the headline wirelength numbers are inconsistent with the tables.","major_comments":[{"comment":"The abstract claims a 5% wirelength reduction, but the average RWL ratios in Table 1 and Table 2 are 1.00 (i.e., identical to DREAMPlace), and Table 1 contains multiple circuits where TransPlace is worse (e.g., mgc_des_perf_1: 1.81 vs. 1.70; mgc_des_perf_b: 2.59 vs. 2.38; mgc_fft_1: 0.70 vs. 0.65). Table 3 shows a 12% average improvement on DAC2012, but even there TransPlace is worse on superblue2 and superblue19. The headline 5% figure is therefore not supported by the reported results and should be reconciled.","section":"Abstract and §3.1, Tables 1–3"},{"comment":"The comparison with DREAMPlace is unfair. For each test design, TransPlace's fine-tuning uses individually selected learning rates (ranging from 1e-4 to 3e-1), density weights (8e-9 to 8e-3), iteration limits (150 to 2000), and hand-set initial offsets (Delta_x and Delta_y), as shown in Tables 7–10, while DREAMPlace runs with default settings (Appendix E.2). Because the GNN is trained on DREAMPlace placements and the fine-tuning stage minimizes the same wirelength and density objectives that DREAMPlace optimizes, any observed improvement over DREAMPlace could arise entirely from the per-circuit tuning rather than from transferable knowledge. The paper must either apply the same per-circuit tuning to DREAMPlace or provide an ablation showing that TransPlace's advantage persists when both methods receive identical optimization budgets.","section":"§2.5 and Tables 7–10"},{"comment":"The ablation study shows that without fine-tuning, TransPlace's inductive output has overflow up to 1,828,433 (versus 5–41 for DREAMPlace) and often fails to route (entries marked '-'). The text in Appendix G states that 'fine-tuning is crucial to guarantee reasonable placement.' This directly contradicts the abstract's claim that TransPlace 'learns to place millions of mixed-size cells' and that the reported improvements stem from transferable placement knowledge. The GNN-only component is far worse than the baseline, so the reported wins must be attributed to the optimization stage, not to the learned inductive placement.","section":"Appendix G, Table 11"},{"comment":"The five training circuits are not named. Table 3 evaluates ten DAC2012 circuits named superblue2–superblue19, and ISPD2015 contains superblue11_a, superblue12, superblue14, superblue16_a, and superblue19. Without a disclosed list of which five circuits were used for training, the claim that the evaluation circuits are 'unseen' cannot be verified, and there is a risk of train/test leakage. Please provide the exact training set and confirm that none of the test designs overlap with it.","section":"§3.1 (training circuits)"},{"comment":"Table 4 shows that TransPlace improves TNS/WNS on average, but routed wirelength is worse on 4 of 8 circuits and the average rWL ratio is 1.01 (1% worse). The timing improvements are obtained with per-circuit hyperparameters (Table 10) and a timing-driven fine-tuning procedure similar to DREAMPlace 4.0, so the isolation problem identified above applies here as well. The '9% better timing' claim should be reported with the associated wirelength regression and with an explicit statement of the fine-tuning cost.","section":"Table 4 and §3.2"}],"minor_comments":[{"comment":"The abstract claims a 1.2x speedup, but Table 5 reports an average speedup of 1.49x on ISPD2015. Please reconcile these numbers or state which benchmark the abstract refers to.","section":"Abstract and Table 5"},{"comment":"The overlap ratio eta is reported as 1.1262, 1.1257, and so on, which is greater than 1. The definition of eta as the ratio of the sum of branch net counts to the original net count should be clarified, since a value above 1 suggests net duplication rather than overlap.","section":"Table 6"},{"comment":"In Algorithm 2, line 12 adds (v, v) to F, which appears to be a self-loop and is inconsistent with Definition 2.2's guarantee that no loop will be found in F. This is likely a typo and should be corrected to (v', v) or similar.","section":"Algorithm 2"},{"comment":"Reference [50] is cited as the DAC2012 benchmark but is titled 'ISPD 2019 Initial Detailed Routing Contest and Benchmark with Advanced Routing Rules.' Please correct the reference or use the proper DAC2012 citation.","section":"References"},{"comment":"Figure 1 is difficult to read: the fine-tuning loop in part (b) is not clearly separated from the inductive placement stage, and the message-passing arrows are dense. A higher-level flow diagram with clear stage boundaries would improve readability.","section":"Figure 1"}],"recommendation":"reject","confidential_remarks":"The reader's report and the stress-test note align with my reading of the manuscript. The central claim of transferable placement knowledge is not supported because (i) the per-circuit fine-tuning hyperparameters in Tables 7–10 give TransPlace an unfair advantage over default DREAMPlace, (ii) the GNN-only ablation in Table 11 is unrouteable, and (iii) the headline wirelength improvement is contradicted by the tables. These issues are load-bearing and cannot be fixed by minor revisions; they undermine the paper's main contribution. The paper could potentially be reframed as a warm-starting method for analytical placers, but that would be a different claim from the one made."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Colleague,\n\nQuick take on TransPlace (2501.05667). The core ideas are worth a look: hierarchical Netlist Graph, cell-flow DAG with SE(2)-invariant relative encoding, and a two-stage design that warm-starts a DREAMPlace-style optimizer. That combination is genuinely new—no one else has scaled a learned inductive placer to million-cell mixed-size circuits in continuous space. The complexity analysis is clean, and the ablation in Table 11 is honest: without fine-tuning, the GNN alone can't route most designs.\n\nThe soft spots, though, are load-bearing. The abstract's 5% wirelength claim is not in the tables. On ISPD2015 and ISPD2019, TransPlace's RWL is on average slightly worse than DREAMPlace (ratio 0.98, meaning ~2% worse). The 30% congestion reduction and 1.2x speedup are better supported, but the speedup comes from the full pipeline, not the GNN alone.\n\nThe bigger issue is the comparison. Fine-tuning uses per-circuit learning rates, density weights, iteration limits, and hand-set initial offsets (Tables 7-10), while DREAMPlace runs with defaults. Table 11 shows the GNN-only output is unrouteable, so every quality gain after fine-tuning could come from the tuned optimizer, not from transferable placement knowledge. The paper doesn't compare against the authors' own RoutePlacer, which already does routability-aware GNN placement. And the five training circuits are never named, so we can't verify the 'unseen circuit' claim.\n\nNone of this makes the paper worthless. The representation learning ideas are solid, and the congestion improvements are real on several large designs. But the headline claims need to be reframed and the experiments re-run with DREAMPlace given the same per-circuit tuning budget, plus a proper train/test split and a RoutePlacer comparison.\n\nI'd send this to a serious referee if it were a new submission—there's enough substance to warrant revision rather than a desk reject. For your reading group, it's a useful case study in how per-instance hyperparameter tuning can confound a comparison. I wouldn't cite the empirical claims as evidence for transferable placement, though.","headline":"A genuinely novel GNN placement architecture with real congestion gains, but the quality claims are confounded by per-circuit fine-tuning and the wirelength headline doesn't match the tables.","tokens_in":23577,"tokens_out":5168,"would_cite":false,"duration_ms":43368,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"A GNN trained on a few preplaced circuits can place unseen million-cell chips in continuous space, faster and with less congestion, timing delay, and wirelength than the placer that generated its training data.","keywords":["EDA","circuit design","global placement","graph neural network","transferable placement","SE(2)-invariant representation","cell-flow","netlist graph"],"falsifier":"Apply the per-circuit hyperparameters from Tables 7–10 to the baseline placer itself, or drop the fine-tuning stage and compare the raw inductive output with the baseline; if the tuned baseline performs as well or better, the claimed transfer gains are not substantiated.","tokens_in":29,"feed_emoji":"⚡","tokens_out":10758,"duration_ms":194458,"temperature":0.7,"pith_summary":"TransPlace sets out to prove that global placement—the step in chip design that arranges millions of cells on a die to minimize wire length, congestion, and delay—can be learned once and transferred to new circuits instead of being re-optimized from scratch for every design. The paper trains a graph neural network on a few placements produced by a GPU-accelerated analytical placer, then uses the trained network to produce an initial placement for an unseen netlist in one forward pass, followed by a short analytical fine-tuning pass that adapts to that circuit's terminals and density constraints. On four standard benchmarks the authors report that this two-stage procedure places new circuits about 1.2 times faster while reducing congestion by 30%, timing degradation by 9%, and wirelength by 5%. If those numbers hold, placement stops being a per-design optimization chore and becomes a learnable warm start, which would matter directly for the speed and quality of modern chip design flows.","feed_headline":"One GNN places new million-cell chips 1.2x faster","feed_subtitle":"Trained on a few high-quality layouts, it transfers to new chips with 30% less congestion and 9% less timing delay.","key_machinery":"Cell-flow: a directed acyclic graph of relative cell positions, built by breadth-first search from fixed terminals through nets, in which each directed edge stores the position of one cell relative to another. This is the object that makes transfer feasible: the encoding $\\boldsymbol{\\rho}, \\Delta\\theta$ is invariant to global rotation and translation, so the model learns layout structure rather than absolute coordinates. Around it sit the Netlist Graph, which preserves full cell–net–pin topology and is coarsened hierarchically with hypergraph partitioning for scalability; TPGNN, the paper's message-passing architecture over both graphs; and the two-stage coarse-to-fine strategy that finishes with wirelength and density fine-tuning. The decoding step is linear in the number of pins, which the paper argues is optimal.","core_discovery":"TransPlace is presented as the first learning-based framework for global placement at the scale of millions of mixed-size cells in continuous space. Its central claim is that a GNN trained only on a handful of preplaced circuits can inductively place unseen circuits and outperform the analytical placer that generated the training data. The model does not predict coordinates directly; it predicts the SE(2)-invariant relative encoding—distance $\\rho$ and deflection $\\Delta\\theta$—along a cell-flow DAG built from the netlist, then decodes those into absolute positions by averaging paths that start from fixed terminals. A circuit-adaptive fine-tuning stage then refines the solution against wirelength and electrostatic density objectives. The authors report improvements over the baseline placer across routability-oriented and timing-oriented benchmarks, including transfer to timing metrics even though the training labels came from routability-driven placements.","pith_inferences":["An extension the paper does not test is whether training labels from several different placers or technology nodes would make the transferred prior more robust; a natural experiment would compare models trained on one versus multiple label sources.","Because the representation is SE(2)-invariant, the model may also tolerate rotated or mirrored layouts in deployment, but the paper does not demonstrate this directly.","The contribution is really the combined inductive-plus-fine-tuning system; an editorial reading is that the GNN's role is to supply a high-quality initialization, while the analytically grounded fine-tuning pass performs the final constraint satisfaction."],"forward_implications":["For each new circuit, the inductive stage provides a warm start that already contains transferable placement structure, so optimization begins from a better point rather than from scratch.","The reported 1.2x speedup and 30% congestion reduction would translate directly into shorter design cycles and fewer routing failures in a physical-design flow.","Because the learning objective is routability-driven but the reported gains include timing, the method implies that a single placement prior can improve multiple design metrics simultaneously.","The near-linear decoding complexity means the approach remains usable as circuits grow to millions of cells, a scale where prior learning-based approaches stopped at floorplanning."],"supporting_citations":[{"why":"The analytical placer whose outputs serve as training labels and as the main baseline TransPlace must outperform.","marker":"[31]"},{"why":"Supplies the electrostatic density formulation and optimizer used in the circuit-adaptive fine-tuning stage.","marker":"[22]"},{"why":"Provides the hypergraph partitioner used to coarsen netlists into hierarchical Netlist Graphs.","marker":"[45]"},{"why":"The timing-driven version of the baseline placer and the source of momentum-based net weighting used in timing fine-tuning.","marker":"[29]"},{"why":"Defines the benchmark with the TNS, WNS, and NVP metrics used for the cross-objective timing evaluation.","marker":"[24]"},{"why":"An earlier GNN-based placer whose message-passing design TPGNN adapts for circuit-aware placement.","marker":"[18]"},{"why":"The global router used to compute the routed wirelength and overflow metrics for the routability evaluation.","marker":"[54]"}],"fun_headline_variants":["GNN trained on a few chips places new million-cell layouts 1.2x faster","Transferable GNN cuts congestion 30% and timing delay 9% on unseen chips","One GNN model masters chip placement from a few examples, then transfers","First GNN to place million-cell chips from just a few training layouts"],"cache_read_input_tokens":25600,"weakest_assumption_plain":"The comparison assumes the baseline placer runs with default settings while each TransPlace circuit receives hand-set learning rates, density weights, iteration limits, and initial offsets; if those per-circuit settings were removed or granted equally to the baseline, the claimed speedup and quality gains could shrink or disappear.","fun_headline_variants_meta":{"raw":{"variants":["GNN trained on a few chips places new million-cell layouts 1.2x faster","Transferable GNN cuts congestion 30% and timing delay 9% on unseen chips","One GNN model masters chip placement from a few examples, then transfers","First GNN to place million-cell chips from just a few training layouts"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000281,"raw_usage":{"total_tokens":1630,"prompt_tokens":880,"completion_tokens":750,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":496,"completion_tokens_details":{"reasoning_tokens":663}},"tokens_in":496,"tokens_out":750,"duration_ms":7071,"temperature":1.0,"reasoning_tokens":663,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-10T21:12:33.550952+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Apply the per-circuit hyperparameters from Tables 7–10 to the baseline placer itself, or drop the fine-tuning stage and compare the raw inductive output with the baseline; if the tuned baseline performs as well or better, the claimed transfer gains are not substantiated.","supporting_citations":[{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Supplies the electrostatic density formulation and optimizer used in the circuit-adaptive fine-tuning stage."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Provides the hypergraph partitioner used to coarsen netlists into hierarchical Netlist Graphs."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Defines the benchmark with the TNS, WNS, and NVP metrics used for the cross-objective timing evaluation."},{"cited_title":"RoutePlacer: An End-to-End Routability-Aware Placer with Graph Neural Network","cited_arxiv_id":"2406.02651","evidence_quote":"An earlier GNN-based placer whose message-passing design TPGNN adapts for circuit-aware placement."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"The global router used to compute the routed wirelength and overflow metrics for the routability evaluation."}],"review_version":1}