{"id":"96bf0e5d-b1c7-4215-abf8-6c53f0ef6479","arxiv_id":"2501.05877","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":4.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":2,"one_line_summary":"A CVD graphene floating-gate transistor demonstrates continuous conductance tuning and multiple synaptic functions using technology-compatible materials.","lead":"The paper reports a graphene transistor that mimics biological synapse behavior, with continuous conductance states and synaptic functions like paired-pulse plasticity. It matters because the device uses chip-industry-compatible materials, potentially easing integration of neuromorphic hardware.","discovery_kind":"extension","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Charge-injection mechanism is inferred from hysteresis and leakage data only; no direct measurement or control excludes other sources of the synaptic dynamics.","rationale":"The reader correctly identifies the unmeasured charge state as the weakest link. My read of the paper confirms that all evidence for electron injection/emission is indirect: transfer-curve splitting, gate-leakage current, and the time decay of drain current after pulses. None of these uniquely determines the charge reservoir. The paper's own text asserts the mechanism ('The physical mechanism of Dirac point splitting is related to...'; 'the intrinsic mechanism of conductance change is the charge state dynamics of the floating gate and interface traps') without independent verification. Since the central claim includes the design-driven mechanism, not just the observed device function, this is load-bearing. However, the concern does not overturn the measured phenomenology; it limits the strength of the mechanistic and design claims. Therefore the CONDITIONAL verdict stands unchanged, pending a control experiment and ideally direct charge or potential measurement.","tokens_in":6808,"tokens_out":3010,"duration_ms":32586,"concrete_test":"Fabricate a reference transistor identical in stack and geometry but with the TiN floating gate either omitted or shorted to the back gate, and repeat the SET/RESET and pulse-train protocols of Figs. 2 and 3. If comparable hysteresis, relaxation, and spike-rate-dependent conductance changes persist, the floating-gate charge-injection mechanism is not the dominant cause of the observed synaptic dynamics.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The paper's central claim—that the biorealistic conductance dynamics arise from gradual electron injection/emission into the floating gate and interface traps—rests on indirect evidence. The split Dirac point, hysteresis, and gate-leakage currents in Figs. 1(e) and 2 are consistent with charge trapping, but the authors do not directly measure the charge state of the floating gate or the trap population, and they provide no control device (e.g., a floating-gate-free transistor) or temperature/sweep-rate dependence to rule out alternative mechanisms. High-k oxides such as Al2O3 and HfO2 can host mobile ions and polarization effects; adsorbate redistribution or measurement artifacts could also produce the observed relaxation and PPF/PPD-like responses. Since the abstract explicitly attributes the 'virtually continuous' conductance levels to gradual injection/emission, and the paper claims that 'device geometry and interface properties can be designed' to optimize the memory window, an unvalidated mechanism weakens the design-driven claim even if the observed phenomenology is real. The mechanism discussion in Fig. 1(c) and the sentence describing 'the intrinsic mechanism of conductance change' are assertions rather than measurements, so the central mechanistic assumption remains unsecured.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper reports a three-terminal graphene floating-gate transistor, with a W/HfO2/TiN/Al2O3/graphene stack, and demonstrates several synaptic functions: pulse-amplitude and pulse-duration dependent plasticity, paired-pulse facilitation/depression, and spike-rate dependent plasticity. The authors attribute the device dynamics to gradual electron injection and emission into the floating gate and interface traps, and they show that shifting the Dirac point via controlled adsorbate doping allows reading at zero gate voltage. The central claim is that this technology-compatible device exhibits biorealistic, tunable plasticity with a virtually continuous range of conductance levels.","tokens_in":6992,"tokens_out":4175,"duration_ms":41534,"significance":"If the claims hold, the device is a useful addition to the synaptic-transistor landscape because it uses comparatively standard materials, a three-terminal architecture that avoids sneak-path problems, and direct experimental demonstration of several synaptic functions without reliance on fitted models. The zero-gate-voltage read scheme and the systematic comparison of two channel geometries are positive design contributions. However, the paper's significance is currently limited by the absence of device-to-device statistics, endurance and retention data, and direct verification of the proposed charge-trapping mechanism; the 'biorealistic' claim rests on qualitative analogy and on inferred, rather than directly measured, internal state dynamics.","major_comments":[{"comment":"The attribution of the conductance dynamics to gradual electron injection/emission into the floating gate and interface traps is inferred only from hysteresis, gate-leakage currents, and pulse-response relaxation. No control device without a floating gate, no temperature dependence, no sweep-rate dependence, and no direct measurement of the gate charge or trap population is provided. Because the abstract and the design-optimization claim explicitly rest on this mechanism, the authors should either add such control experiments or substantially temper the mechanistic language.","section":"Fig. 1(c) and the paragraph after Fig. 1(e)"},{"comment":"The paper states that 'Dirac point splitting causes the increase of the memory window,' yet the reported memory windows are 4.2 V for the 5-µm channel and 3.7 V for the 10-µm channel, while the 10-µm channel is described as having more prominent splitting. This apparent inconsistency needs an explanation, and the units of the memory-window values should be stated explicitly. Without this, the central design rule that geometry controls the memory window is not convincingly established.","section":"Figs. 1(e) and 2 and the memory-window discussion"},{"comment":"All electrical data appear to come from a single representative device or a single measurement; no error bars, no device-to-device variation, and no sample-size information are reported. Claims such as 'memory window reaches 4.2 and 3.7' and 'virtually continuous range of multiple conductance levels' require at least statistics over several devices, especially since the paper argues that the device geometry and interface state can be designed for optimized performance.","section":"Figs. 2 and 3 and the conclusion"},{"comment":"The introduction lists 'spike transition from short term plasticity (STP) to long term plasticity (LTP)' among the demonstrated functions, but the paper only shows relaxation to stationary values after single pulses and frequency-dependent responses. No experiment explicitly demonstrates a transition from short-term to long-term plasticity as a function of spike count or train duration. This claimed synaptic function is therefore not supported by the presented data.","section":"Fig. 3 and the STP-LTP discussion"},{"comment":"No endurance or retention data are presented, although the paper claims 'long-term memory' and describes the stationary conductance levels as stable. For a synaptic device intended for hardware neuromorphic systems, repeated write/erase cycling and retention over relevant timescales are essential. The absence of these data leaves the practicality claim unverified.","section":"Fig. 3 and the conclusion"}],"minor_comments":[{"comment":"The phrase 'channel lengths were 5 and 10 µm2' contains a typo; the area unit should be removed, leaving '5 and 10 µm'.","section":"Device fabrication paragraph"},{"comment":"The memory-window values '4.2 and 3.7' are given without units; presumably they are in volts, and this should be stated.","section":"Memory-window paragraph after Fig. 1(e)"},{"comment":"The text refers to '[Fig. 1(d)]' when discussing transfer characteristics and the read voltage of -3 V; the intended reference appears to be Fig. 1(e).","section":"Paragraphs referring to Fig. 1(e)"},{"comment":"The phrase 'not splitted' should be 'not split', and the notation for source-drain voltage should be consistent throughout (e.g., VSD rather than 'source-drain voltage equals to').","section":"Fig. 1(e) and Fig. 2"},{"comment":"The term 'all-technology-compatible' is not defined; the manuscript should specify which technology node or fabrication environment is meant, since CVD graphene transfer and e-beam evaporation are not standard CMOS front-end processes.","section":"Introduction and conclusion"},{"comment":"The statement that the memory window is 'close to its limit for graphene at room conditions' is unsupported by any reference or quantitative criterion; a citation or a definition of that limit is needed.","section":"Discussion of the memory-window limit"}],"recommendation":"major_revision","confidential_remarks":null},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Short take: this is a legitimate, well-executed device paper, and the split Dirac point design is the most interesting thing in it. Don't buy the mechanism story as proven, but the phenomenology looks real.\n\nWhat's new: not the first graphene synapse or 2D floating-gate synapse, but the combination of CVD graphene, W/HfO2/TiN/Al2O3 stack, and a floating gate that covers only part of the channel gives a transfer curve with two Dirac points. That split lets them push the memory window close to graphene's room-temperature limit and, by keeping adsorbates, shift the window so reading happens at zero gate voltage. Those are concrete, useful engineering tricks. They then show the expected set of synaptic functions — PADP, PDDP, PPF/PPD, SRDP, STP-to-LTP — with clean-looking pulse measurements and a sensible story about relaxation between pulses and therefore frequency dependence.\n\nWhat's soft: the device-to-device and run-to-run evidence is thin. No error bars, no endurance, no retention, no statistics across devices. The 'virtually continuous conductance levels' is supported by a family of I–V curves, but there's no count of distinct states or linearity check. More importantly, the paper attributes the dynamics to gradual electron injection/emission into the floating gate and interface traps. That's a plausible—indeed standard—model for this kind of stack, and the leakage currents and split Dirac points are consistent with it. But it remains an inference. No control device (e.g., same stack without a floating gate), no temperature or sweep-rate series, no direct charge measurement. High-k oxides can move ions and adsorbates could in principle contribute, so the mechanistic claim as stated ('the intrinsic mechanism is...') goes further than the evidence. The stress-test note is right on this, though I'd call it a soft spot rather than a fatal one: the device-level demonstrations don't depend on the exact trap/ion partition.\n\nCitation pattern is fine, including the prior graphene memristive synapse and 2D floating-gate work. The paper doesn't oversell with respect to those; it claims incremental but solid engineering.\n\nWho it's for: anyone working on three-terminal synaptic devices or graphene neuromorphic hardware. It deserves regular peer review, with requests for statistics and at least one control experiment before acceptance. I'd read the revised version.","headline":"Solid three-terminal graphene synapse with a genuinely useful split-Dirac-point design; the mechanism story needs controls, but the device work deserves peer review.","tokens_in":7567,"tokens_out":2259,"would_cite":false,"duration_ms":23732,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"A graphene floating-gate transistor built from industry-compatible materials achieves nearly continuous conductance states and biorealistic synaptic timing, reproducing paired-pulse and spike-rate plasticity.","keywords":["graphene synaptic transistor","floating-gate memory","neuromorphic hardware","synaptic plasticity","paired-pulse facilitation","spike-rate dependent plasticity","short-term plasticity","CVD graphene"],"falsifier":"Fabricate a control transistor identical except without the TiN floating gate, or with the floating gate electrically shorted to the back gate; if it still shows the same magnitude of hysteresis and the same pulse-rate-dependent relaxation, then floating-gate charge storage is not the cause. Alternatively, directly probe the floating-gate voltage with a high-impedance contact after a SET/RESET pulse and check that its change tracks the observed conductance relaxation on the same timescale.","tokens_in":6620,"feed_emoji":"🧠","tokens_out":7429,"duration_ms":67272,"temperature":0.7,"pith_summary":"This paper sets out to show that a synaptic transistor can be made from industrially compatible materials—CVD graphene on an $\\mathrm{HfO_2}$/TiN/$\\mathrm{Al_2O_3}$ gate stack—and still behave like a biological synapse. The device stores charge gradually in a floating gate and in oxide-graphene interface traps, giving a virtually continuous set of conductance levels rather than discrete states. Its temporal relaxation after voltage pulses mirrors the short-term dynamics of real synapses, and it reproduces paired-pulse facilitation/depression, spike-rate-dependent plasticity, and the transition from short-term to long-term plasticity. The authors further show that device geometry and graphene surface state can be engineered to enlarge the memory window and shift the read point to zero gate voltage, reducing power consumption. If correct, this places a three-terminal, leak-resistant synapse within reach of standard semiconductor fabrication.","feed_headline":"Graphene transistor mimics synapse timing with continuous weights","feed_subtitle":"A floating gate and oxide traps give gradual conductance states and short- and long-term plasticity.","key_machinery":"The central object is a floating-gate field-effect transistor with a graphene conduction channel: a W back gate, $10\\,\\mathrm{nm}$ $\\mathrm{HfO_2}$ blocking oxide, TiN floating gate, $5\\,\\mathrm{nm}$ $\\mathrm{Al_2O_3}$ tunnel oxide, and CVD monolayer graphene, with the floating gate shorter than the channel so that only part of the channel is gated by it. That geometry splits the Dirac point into two features and widens the memory window, while the engineered asymmetry of the transfer curve places the largest memory window at $V_{\\mathrm{READ}}=0$. The mechanism carrying the argument is the slow, gradual charging and discharging of the floating gate and of traps at the graphene/$\\mathrm{Al_2O_3}$ interface: tunneling or thermionic emission transfers electrons into these reservoirs under a positive pulse and removes them under a negative pulse, so conductance relaxes on a timescale that mimics synaptic biochemistry.","core_discovery":"The central claim is that a three-terminal transistor with a graphene channel and a floating-gate stack exhibits a virtually continuous spectrum of conductance states whose time evolution is governed by gradual injection and emission of electrons into the floating gate and interface traps. This internal charge dynamics gives the device an intrinsic short-term memory that interacts with incoming spikes, so the final conductance depends on pulse amplitude, duration, rate, and history, not just on the last pulse. The paper reports memory windows of $4.2$ V for a $5\\,\\mu\\mathrm{m}$ channel and $3.7$ V for a $10\\,\\mu\\mathrm{m}$ channel, split Dirac points caused by the two differently gated channel regions, and the emulation of pulse-amplitude and pulse-duration dependent plasticity, paired-pulse facilitation/depression, spike-rate dependent plasticity, and the short-term to long-term plasticity transition. Because the read and write paths are separated by the gate electrode, the device avoids the sneak-path leakage that plagues two-terminal memristor arrays.","pith_inferences":["A direct test not reported in the paper: measuring the floating-gate potential with a high-impedance contact or Kelvin probe after SET/RESET pulses would confirm whether the conductance drift is indeed caused by stored electron charge rather than by mobile ions or adsorbate motion; the authors attribute the effect to electron injection and emission without directly measuring the charge state.","If the mechanism is as claimed, the tunnel oxide thickness and floating-gate length give two independent knobs to set the relaxation time constant, which could be tuned separately from the conductance range—a possible route to devices with programmable short-term memory timescales.","The observed asymmetry between positive and negative pulses implies that spike-timing-dependent plasticity protocols would need to be calibrated differently for potentiation and depression; this could be exploited by using one polarity for emulation and the other for reset, a design choice the paper mentions but does not elaborate."],"forward_implications":["A three-terminal synapse built this way can be packed into crossbar-like arrays without the selector devices needed to suppress sneak paths in two-terminal memristor arrays, since the gate separates programming and readout.","The demonstrated memory window and near-continuous conductance levels make the device suitable for analog weight storage in hardware neural networks, with enough levels for multibit rather than binary weights.","Because the read voltage can be set to zero for the adsorbate-shifted devices, the same synaptic function can be obtained at lower power consumption than symmetric devices that must be biased during read.","The dependence of the final conductance on pulse amplitude, duration, and frequency means the same physical device can implement several plasticity rules, so a single array could support different learning protocols.","Encapsulation after preheating removes ambient adsorbates and yields stable, symmetric transfer curves, indicating the behavior is intrinsic to the charge-storage stack rather than to environmental doping."],"supporting_citations":[{"why":"Benchmark graphene memristive synapse showing high-precision analog conductance, which this work extends to a technology-compatible floating-gate transistor.","marker":"[17]"},{"why":"Supplies the standard explanation of hysteresis in graphene transistors via charge trapped in the adjacent oxide, which the paper invokes for its memory window.","marker":"[18]"},{"why":"Prior ferroelectric second-order memristor with internal depolarization dynamics, used as the earlier example of intrinsic temporal behavior.","marker":"[7]"},{"why":"Demonstrated a biorealistic second-order memristor through internal ionic dynamics, providing the benchmark for paired-pulse and rate-dependent plasticity.","marker":"[4]"},{"why":"A 2D-material floating-gate synaptic device with linear weight update, the closest floating-gate precursor to this work.","marker":"[11]"},{"why":"A Si FET synaptic device with short-term and long-term plasticity using a high-k gate stack, establishing the three-terminal synaptic transistor approach.","marker":"[14]"}],"fun_headline_variants":["Graphene synaptic transistor tunes weights continuously","Biorealistic graphene synapse with gradual conductance","Technology-compatible synapse mimics brain's timing","Graphene transistor shows short- and long-term memory","Continuous synaptic weights from a graphene floating gate"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The load-bearing premise is that the gradual conductance changes come from electrons being slowly injected into and released from the buried floating gate and oxide interface traps; the paper does not directly measure the charge on the floating gate or the trap population, so a different origin for the hysteresis—such as mobile ions, atmospheric adsorbates, or measurement artifacts—would undercut the claimed biorealistic mechanism.","fun_headline_variants_meta":{"raw":{"variants":["Graphene synaptic transistor tunes weights continuously","Biorealistic graphene synapse with gradual conductance","Technology-compatible synapse mimics brain's timing","Graphene transistor shows short- and long-term memory","Continuous synaptic weights from a graphene floating gate"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000779,"raw_usage":{"total_tokens":3430,"prompt_tokens":916,"completion_tokens":2514,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":532,"completion_tokens_details":{"reasoning_tokens":2445}},"tokens_in":532,"tokens_out":2514,"duration_ms":18361,"temperature":1.0,"reasoning_tokens":2445,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-10T21:05:31.870747+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Fabricate a control transistor identical except without the TiN floating gate, or with the floating gate electrically shorted to the back gate; if it still shows the same magnitude of hysteresis and the same pulse-rate-dependent relaxation, then floating-gate charge storage is not the cause. Alternatively, directly probe the floating-gate voltage with a high-impedance contact after a SET/RESET pulse and check that its change tracks the observed conductance relaxation on the same timescale.","supporting_citations":[{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Benchmark graphene memristive synapse showing high-precision analog conductance, which this work extends to a technology-compatible floating-gate transistor."},{"cited_title":"Mikheev , author A","cited_arxiv_id":null,"evidence_quote":"Prior ferroelectric second-order memristor with internal depolarization dynamics, used as the earlier example of intrinsic temporal behavior."},{"cited_title":"Kim , author C","cited_arxiv_id":null,"evidence_quote":"Demonstrated a biorealistic second-order memristor through internal ionic dynamics, providing the benchmark for paired-pulse and rate-dependent plasticity."},{"cited_title":"Park , author M","cited_arxiv_id":null,"evidence_quote":"A 2D-material floating-gate synaptic device with linear weight update, the closest floating-gate precursor to this work."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"A Si FET synaptic device with short-term and long-term plasticity using a high-k gate stack, establishing the three-terminal synaptic transistor approach."}],"review_version":1}