{"id":"2b5a3b8d-a3b9-4448-a4d4-545130e29f16","arxiv_id":"2501.14083","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":2,"one_line_summary":"A large-area digital SiPM with 72.5% fill factor reads individual photon hits with 10 ns timing through a four-signal serial interface.","lead":"A new digital silicon photomultiplier chip combines single-photon avalanche diodes with digital readout on one 8 by 9 millimeter die, keeping 72.5 percent of the area light-sensitive. It reads out every photon hit serially with four signals, so many chips can be chained into large detector planes for dark matter experiments.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The central rare-event application claim rests on vendor-supplied cryogenic DCR/crosstalk numbers that are not measured on this chip; a cold dark-count/crosstalk characterization is needed to establish suitability for liquid noble gas detectors.","rationale":"The reader's conditional verdict is appropriate. I looked for a more internal inconsistency and found the S2 burst handling tension between Section 2.3's statement that 'every set hit flipflop is read out' and Section 4's statement that pixels waiting for readout are blind; however, the paper explicitly flags the S2 impact as needing simulation, so it is a known limitation rather than a hidden flaw. The more load-bearing assumption is the cryogenic DCR/crosstalk figure from the vendor. Section 1 sets DCR ≤ 0.01 Hz/mm² as a hard requirement for the target experiments, and the abstract's application claim rests entirely on Section 4's unpublished vendor numbers. The chip's own tests do not address cold operation, and the vendor data are from a different test chip. If that assumption fails, the design cannot serve its stated purpose no matter how well the digital readout works. This is not a dispute with consensus; it is an unverified quantitative input. A cold DCR/crosstalk measurement on this specific chip would settle it. The verdict should remain conditional: the paper is a sound design and functional-test contribution, but the headline rare-event capability is not yet demonstrated.","tokens_in":11258,"tokens_out":7610,"duration_ms":75525,"concrete_test":"Mount a fabricated die in a light-tight cryostat, cool it to 165 K (liquid xenon) and 87 K (liquid argon), bias all SPADs at the nominal high voltage, and run the intended calibration sequence including masking of noisy SPADs as described in Section 2.1. Acquire dark data for at least one hour per temperature at the full 50 MHz readout clock, then compute the post-masking dark count rate per mm² and the adjacent-pixel coincidence rate within the 10 ns time bin as an estimate of crosstalk. The concern lands if the measured DCR is not compatible with the Section 4 values of 0.02 Hz/mm² at LXe and 0.01 Hz/mm² at LAr, or if crosstalk is substantially larger than the quoted 4%.","verdict_should_be":"UNCHANGED","load_bearing_attack":"Section 4 states that the Fraunhofer IMS technology 'offers SPADs optimized for cold operation with a dark count rate of only ≈0.02 Hz per mm² at liquid Xenon temperature and ≈0.01 Hz/mm² at liquid Argon temperature', with crosstalk ≲4%, citing a paper in preparation. These numbers are the quantitative foundation for the abstract's claim that the chip 'may be used in experiments that need to detect rare scintillation events': if the real DCR of these specific large SPADs at 165 K or 87 K is even a few times higher, the dark-noise coincidence rate in a large detector plane would overwhelm the S1 signal. The chip's own tests in Section 3 are room-temperature wafer-prober checks that demonstrate digital control and light-induced hits; they do not measure DCR, crosstalk, PDE, or timing at operating temperature. The vendor figures come from a different test chip and an unpublished manuscript, so they cannot be assumed to transfer automatically to this 8×9 mm die with its particular SPAD size, shared N-wells, and surrounding CMOS. If the DCR assumption is met, the design is a useful contribution; if not, the central rare-event application claim fails. A secondary, explicitly acknowledged limitation is the S2 burst readout in Section 4, where 'pixels waiting for readout are blind for new hits' and the impact 'needs to be studied by simulations'; however, the DCR question is more fundamental because it determines whether the chip can detect S1 at all.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The manuscript presents the design and first functional tests of a large-area digital SiPM chip fabricated in a 350 nm CMOS/SPAD process. The chip has an active area of about 8 mm × 8.7 mm, divided into 32 × 30 pixels, each containing nine individually maskable SPADs; the pixel electronics and readout are fully digital, requiring only four signals (CLK, CMD, SERIN, SEROUT) and supporting daisy-chaining of multiple chips. The reported fill factor is 72.5%, and a module concept gives about 69–71% sensitive area. The authors describe the pixel circuit, matrix readout, serial readout protocol, command encoding, and chip-control scheme in detail. First wafer-prober tests demonstrate digital control, serial bit transfer, and light-induced hits using a metal mask. The discussion claims the technology is suitable for liquid noble gas detectors because of low cryogenic dark count rate and low crosstalk, citing vendor test-chip data, and identifies readout limitations for S2 bursts that remain to be simulated.","tokens_in":11552,"tokens_out":3741,"duration_ms":35539,"significance":"If the underlying SPAD technology indeed provides the quoted cryogenic dark count rates (about 0.02 Hz/mm² in LXe and 0.01 Hz/mm² in LAr) and crosstalk below 4%, then this chip architecture could enable large detector planes with roughly 70% photosensitive area, far simpler cabling, and no analog front-end electronics, which is a meaningful step toward a scalable alternative to PMTs in liquid noble gas experiments. The design contains several useful innovations: the defect-density-based fill-factor optimization in Eq. (1), the grouping of nine individually disabled SPADs into one logical pixel, the ultra-compact shared logic for four pixels, and a fully serial readout and control protocol that supports chip identification and configuration through the data stream. The paper is honest about its current status, reporting only qualitative room-temperature tests and clearly flagging known limitations, but the central application claim nevertheless rests on unmeasured cryogenic parameters.","major_comments":[{"comment":"The abstract's claim that the chip 'may be used in experiments that need to detect rare scintillation events' rests entirely on vendor-supplied cryogenic dark count rates (about 0.02 Hz/mm² at LXe temperature and 0.01 Hz/mm² at LAr temperature) and crosstalk of about 4% from a paper in preparation, not on measurements of this chip. Since the introduction itself sets a DCR requirement of ≤ 0.01 Hz/mm², the feasibility argument is load-bearing. If the actual DCR of these large SPADs at 165 K or 87 K is a few times higher, the dark-noise coincidence rate in a large detector plane would overwhelm the S1 signal. The paper should either present cryogenic DCR and crosstalk data for this specific chip or explicitly rephrase the application claim as conditional on future characterization. As written, the abstract overstates readiness.","section":"Section 4 and Abstract"},{"comment":"The first chip test results are qualitative wafer-prober checks performed at a few MHz. They demonstrate that the digital control, serial readout, and light-induced hit generation work, but they do not quantify dark count rate, photon detection efficiency, timing resolution, or crosstalk, even at room temperature. Given that the title advertises 'Single Photon Detection in Liquid Noble Gas Detectors', a room-temperature DCR measurement and a calibration of the 10 ns timestamp would materially substantiate the central functionality; without them, the paper validates the digital architecture, not the single-photon detection performance asserted in the title.","section":"Section 3"},{"comment":"Two known limitations are acknowledged but not analyzed: (i) hits that arrive in a column after the first hit but before readout receive a timestamp that is too early, and (ii) during S2 burst readout, pixels waiting for readout are blind to new hits. The text states that the impact 'needs to be studied by simulations', which is honest, but these limitations are not mentioned in the abstract or the conclusions. For a design paper with application claims, the abstract should at least note that burst-mode efficiency remains to be verified, otherwise readers may assume the readout is fully lossless at high occupancy.","section":"Sections 2.3 and 4"}],"minor_comments":[{"comment":"The figure caption says '10 random defects per mm²' for the left illustration, but the right plot shows curves for 0, 1, and 10 defects/mm²; please state explicitly which value the illustration uses.","section":"Section 2.1, Fig. 2"},{"comment":"The choice of grouping nine SPADs into one logical pixel is motivated by defect tolerance and circuit reduction, but the average pixel size of 250 × 291 μm² and the individual SPAD active area are not given; please provide the per-SPAD dimensions.","section":"Section 2.1"},{"comment":"In the description of the hit flip-flop, the hit signal is said to be connected to the 'clock input' of an edge-triggered flip-flop. It would be clearer to state explicitly whether the hit signal is the clock or a data/set signal, since the text later says the flip-flop is 'set' by a hit.","section":"Section 2.2"},{"comment":"The comparison with the Hamamatsu R11410 PMT quotes a best hexagonal packing fill factor of ≤ 64.3%. Please double-check this number: using the stated diameters (76 mm outer, 65 mm active) and hexagonal packing of circles, the sensitive-area fraction is approximately 66%, so the quoted value may be slightly pessimistic.","section":"Section 4.1, footnote 1"},{"comment":"The bandwidth estimate of 1.8 Mhits/s for one serial chain assumes 50 MHz clock and 28-bit packets; the text correctly notes that the actual chip-to-chip protocol includes empty/full packet arbitration, but it would be helpful to state explicitly that this is an upper bound that does not account for packet overhead in a daisy chain.","section":"Section 4"}],"recommendation":"major_revision","confidential_remarks":"This is a solid design paper with a clear and well-documented architecture, but its headline application claim is currently supported only by vendor test-chip data, not by measurements on the presented chip. The paper would be acceptable after major revision if the authors either add cryogenic DCR/crosstalk measurements or appropriately scope the claim in the abstract and conclusions. The design details are credible and the first tests are a reasonable starting point, but the paper currently sits between a design description and a detector characterization paper; choosing one framing consistently would strengthen it."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Colleague,\n\nQuick take: this is a well-executed, honestly reported chip design paper. The genuinely new thing is the architecture — a 32x30 pixel digital SiPM on an 8x9 mm die, 72.5% fill factor, with all control and data moving over four CMOS signals (CLK, CMD, SERIN, SEROUT). The pulse-width-encoded command scheme and the daisy-chaining with packet injection are clever and should make fielding large detector planes much simpler than PMTs or analog SiPMs.\n\nThe design rationale is sound. The trade-off between SPAD size and defect-induced fill factor loss is treated with a simple but plausible model; grouping 9 SPADs per logical pixel with individual disable is a good compromise. The layout is deeply optimized, and the paper shows real evidence: the chip was fabricated, and wafer-prober tests demonstrate digital read/write, chip ID programming, and position-sensitive light detection through a mask. That is legitimate first-level verification.\n\nNow the soft spots, in proportion to how soft they are. The paper's motivation for liquid noble gas detectors rests on dark count rate and crosstalk numbers from vendor test chips at cryogenic temperature — cited as 'paper in preparation' and not measured on this device. That is a load-bearing assumption, and the paper's own words ('may be used') are appropriately hedged, but a reader should not mistake the current state for verified performance. The wafer-prober tests are qualitative and at MHz speeds; no DCR, PDE, crosstalk, or timing resolution is measured yet. The S2 burst behavior — pixels blind during readout, potentially corrupted timestamps — is explicitly left for simulation, which is honest but means that part is unverified. These are real gaps, but they are not hidden, and they do not undermine the design contribution.\n\nThe citation pattern is fine; the authors draw on relevant PMT, SiPM, and cryogenic readout literature without overclaiming. They also correctly compare their fill factor against PMT packing.\n\nWho is this for? Instrumentation physicists working on large-area photodetector planes for noble liquid detectors or anyone building scalable SPAD readout. It deserves a serious referee: the architecture is novel, the measurements are early but appropriate for a JINST submission, and the limitations are disclosed. I would recommend publishing after the authors either add cryogenic characterization or more explicitly mark the DCR assumption as external, and ideally after an S2 simulation or a clear plan for it. Engage with it; it is a useful data point for the field.\n\nBest,\n[You]","headline":"A solid and honest engineering paper on a large-area digital SiPM with a genuinely clever four-wire serial readout; the cryogenic DCR numbers are vendor-supplied, not measured, which is the one big caveat.","tokens_in":12096,"tokens_out":1512,"would_cite":true,"duration_ms":17367,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":["85.60.Gz","29.40.Vj"],"model":"deepseek-v4-flash","headline":"This paper presents a prototype \"digital SiPM\" that reaches a 72.5% photo-sensitive fill factor on an 8x9 mm die and writes every photon hit as an x-y-t packet on a single serial line.","keywords":["digital SiPM","single-photon avalanche diode (SPAD)","liquid noble gas detectors","liquid xenon","liquid argon","dark count rate","fill factor","serial digital readout"],"falsifier":"Cool the fabricated chip to liquid-xenon and liquid-argon temperatures, bias the SPADs at the intended overvoltage, and measure the dark count rate per square millimeter and the nearest-neighbour crosstalk fraction; if the measured rate is materially above about $0.02$ per second per square millimeter at liquid-xenon temperature or about $0.01$ at liquid-argon temperature, or crosstalk exceeds about 4%, the noise-coincidence background would dominate the rare-event signal and the central feasibility claim would fail.","tokens_in":11039,"feed_emoji":"⚡","tokens_out":14066,"duration_ms":120484,"temperature":0.7,"pith_summary":"Dark matter and neutrino searches in liquid noble gases need square-meter-scale arrays of single-photon detectors, and today those arrays are built from photomultiplier tubes with bulky analog electronics, many cables, and radioactivity concerns. This paper presents a prototype \"digital SiPM\" that replaces that chain with one CMOS die: $32\\times30$ pixels of avalanche photodiodes cover 72.5% of the active area, and every photon hit is read out as a position and a $\\sim\\!10$-nanosecond timestamp through a purely digital serial interface. The authors' central claim is that these chips can be daisy-chained into detector planes with about 70% photo-sensitive fill factor using only four CMOS signals per chain, and that the SPAD technology's cryogenic dark count rate (about $0.02~\\mathrm{Hz/mm^2}$ in liquid xenon, $0.01~\\mathrm{Hz/mm^2}$ in liquid argon) keeps noise coincidences below the rare-event signal. First wafer-probe tests confirm the serial protocol, register configuration, and masked single-photon imaging; full cryogenic characterization and high-rate burst behavior are stated as next steps.","feed_headline":"Single-photon detector chip reaches 72.5% fill factor, needs 4 wires","feed_subtitle":"Daisy-chained chips form ~70%-fill-factor planes for liquid noble gas experiments with 10-ns photon timing.","key_machinery":"The load-bearing mechanism is the purely serial, packet-based readout chain together with the matrix scanner. Instead of analogue sums, every pixel reports through a wired-NOR and a hit flip-flop; column and row priority encoders turn any pattern of fired pixels into address words, and a global Gray counter timestamps hits with $\\sim10~\\mathrm{ns}$ granularity. A 28-bit serial packet uses a leading high level plus a flag: an empty packet can be claimed by any chip in the chain, which flips the flag and inserts its own 10-bit position, 10-bit time, and 6-bit chip ID. The design also uses a fill-factor formula, trading SPAD side length against the probability that a defect makes a SPAD unusable, to choose pixel geometry and to justify individual SPAD disable lines.","core_discovery":"On the paper's own terms, the discovery is that a large-area digital SiPM can combine high fill factor, single-photon sensitivity, and a fully digital readout without amplifiers or ADCs. Each of the $32\\times30$ logical pixels contains nine individually disable-able SPADs whose ORed hits set a flip-flop; a column-wise time latch captures the arrival time from a Gray counter, and a state machine scans only active columns and rows, writing $(x,y,t)$ words into a FIFO. Output uses a fixed 28-bit serial packet: a chip with data flips the empty packet flag and inserts its own position, time, and chip-ID payload, so daisy-chained chips merge onto one serial line at up to 1.8 million hits per second. The die has 72.5% photo-sensitive fill factor, and the authors estimate that wire-bonded or TSV/bump-bonded modules can reach plane fill factors of about 69–71%, which they compare with the 64.3% maximum packing of 3-inch PMTs. The first measurements, taken on a wafer prober, show the digital chain and register access working and confirm hit detection under a masked light spot.","pith_inferences":["The empty-packet mechanism is naturally unfair to downstream chips under heavy load; allocating empty slots in a weighted round-robin would make the bandwidth per chip predictable without changing the packet format.","The readout chain is wavelength-agnostic, so the same packet architecture could be reused with SPAD processes tuned for visible or infrared single-photon counting, not just VUV liquid-noble scintillation.","A detector-level trigger that reads out only candidate time windows would reduce S2-burst blind time and timestamp corruption, since the chip currently records continuously regardless of occupancy.","If the quoted cryogenic dark count rates hold, the dominant background in such a detector would shift from photodetector dark noise to radioactive backgrounds from materials and surfaces, which would change future material-selection priorities."],"forward_implications":["Liquid noble gas detector planes can be assembled from many daisy-chained chips with one serial chain, reducing the number of cables, amplifiers, and ADCs compared with PMT-based designs.","At a 50 MHz clock, one serial chain saturates at 1.8 million hits per second, while the expected background of S1 events plus dark counts is only about 100 thousand hits per second per square meter.","An S2 burst of about 1000 photons takes roughly 0.5 milliseconds to read out, and pixels waiting for readout are blind during that time; the authors propose adding double hit buffering if simulations show this loss matters.","Module designs with through-silicon vias and bump bonding could cover a plane at about 71% photo-sensitive fill factor, above the ~64.3% maximum for hexagonally packed 3-inch PMTs.","Because each SPAD can be disabled individually, a fatal defect costs only one ninth of a pixel area, which is what makes the large-pixel layout robust at realistic defect densities."],"supporting_citations":[{"why":"It establishes the dark matter search application and the sparsity of the events, which set the requirements on dark count rate and hit throughput.","marker":"[1]"},{"why":"It reviews liquid noble gas detectors and their scintillation wavelengths, defining the operating environment for which the chip is designed.","marker":"[2]"},{"why":"It describes a current PMT-based dark matter experiment whose system the new detector plane is intended to replace.","marker":"[6]"},{"why":"It documents the radioactive background contribution of PMTs, which motivates the silicon alternative.","marker":"[9]"},{"why":"It reports cryogenic characterization of SiPMs, supporting the feasibility of low dark count rates at low temperature.","marker":"[10]"},{"why":"It demonstrates VUV-sensitive SiPMs for xenon scintillation light, supporting the UV sensitivity and cold operation assumptions.","marker":"[11]"},{"why":"It presents very large analog SiPM arrays with aggregated output, the architecture whose amplifiers and ADCs the digital readout replaces.","marker":"[14]"},{"why":"It supplies the PMT diameter and active-area dimensions used to compute the 64.3% maximum packing fill factor that the module design aims to beat.","marker":"[17]"}],"fun_headline_variants":["Single-photon digital SiPM hits 72.5% fill factor, 4-signal readout","Daisy-chainable digital SiPM plane: ~70% fill factor for noble-gas detectors","Chip merges SPADs and CMOS to log 10-ns photon hits serially","Large-area digital SiPM: 32×30 pixels, 1.8M hits/s, 4 wires","High-fill-factor digital SiPM for dark matter searches uses 4 CMOS lines"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"Everything rests on the foundry SPADs really having the quoted dark count rate of about $0.02$ events per second per square millimeter at liquid-xenon temperature and $0.01$ at liquid-argon temperature, with under 4% crosstalk; if real dark counts are higher, random coincidences would swamp the rare-event signature the chip is designed to catch.","fun_headline_variants_meta":{"raw":{"variants":["Single-photon digital SiPM hits 72.5% fill factor, 4-signal readout","Daisy-chainable digital SiPM plane: ~70% fill factor for noble-gas detectors","Chip merges SPADs and CMOS to log 10-ns photon hits serially","Large-area digital SiPM: 32×30 pixels, 1.8M hits/s, 4 wires","High-fill-factor digital SiPM for dark matter searches uses 4 CMOS lines"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000274,"raw_usage":{"total_tokens":1652,"prompt_tokens":970,"completion_tokens":682,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":586,"completion_tokens_details":{"reasoning_tokens":559}},"tokens_in":586,"tokens_out":682,"duration_ms":5342,"temperature":1.0,"reasoning_tokens":559,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-10T15:22:33.116168+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Cool the fabricated chip to liquid-xenon and liquid-argon temperatures, bias the SPADs at the intended overvoltage, and measure the dark count rate per square millimeter and the nearest-neighbour crosstalk fraction; if the measured rate is materially above about $0.02$ per second per square millimeter at liquid-xenon temperature or about $0.01$ at liquid-argon temperature, or crosstalk exceeds about 4%, the noise-coincidence background would dominate the rare-event signal and the central feasibility claim would fail.","supporting_citations":[{"cited_title":"Dark Matter Search with liquid Noble Gases","cited_arxiv_id":"1206.2169","evidence_quote":"It establishes the dark matter search application and the sparsity of the events, which set the requirements on dark count rate and hit throughput."},{"cited_title":"Chepel and H","cited_arxiv_id":null,"evidence_quote":"It reviews liquid noble gas detectors and their scintillation wavelengths, defining the operating environment for which the chip is designed."},{"cited_title":"Aprile for the XENON Collaboration","cited_arxiv_id":null,"evidence_quote":"It documents the radioactive background contribution of PMTs, which motivates the silicon alternative."},{"cited_title":"Razeto et al","cited_arxiv_id":null,"evidence_quote":"It presents very large analog SiPM arrays with aggregated output, the architecture whose amplifiers and ADCs the digital readout replaces."},{"cited_title":"Lung et al","cited_arxiv_id":null,"evidence_quote":"It supplies the PMT diameter and active-area dimensions used to compute the 64.3% maximum packing fill factor that the module design aims to beat."}],"review_version":1}