{"id":"9c1504ae-a03e-4e3d-ad96-a5251f81ec5f","arxiv_id":"2502.04524","paper_version":4,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":5.0,"correctness_risk":"high","formal_verification":"none","parameter_count":6,"one_line_summary":"An 8x4 CMO/HfOx ReRAM array is characterized to show low programming noise and stable states, and simulations project this technology enables both analog inference and on-chip training.","lead":"This paper reports a conductive-metal-oxide/HfOx ReRAM array that combines analog inference and simulated on-chip training, claiming low programming noise and stable multi-bit states. The work is a device-level advance, but the all-in-one training claim rests on simulations rather than a full hardware demonstration.","discovery_kind":"extension","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The 'all-in-one' claim rests on simulated training: MNIST/LSTM accuracies come from aihwkit, not from the 1T1R array; no on-chip training loop is demonstrated.","rationale":"I focused on the training pillar rather than the 10-year extrapolation because the extrapolation affects the magnitude of the inference advantage, whereas an undemonstrated training loop undermines the paper's central 'all-in-one' novelty. The manuscript is transparent about the simulation status: Fig. 6 results are labeled 'HW-aware simulation of analog training' (Methods 4.7) and use a fitted generalized soft-bounds model, not measurements from the 8x4 array. The array-level contribution in Section 2.3.1 is limited to open-loop pulse characterization (Fig. 5), necessary but not sufficient evidence for on-chip training. The reader's extrapolation concern is valid and important: Fig. 4e extrapolates one week of relaxation with a linear fit in log(t) to 10 years, and the headline 3x/20x improvements depend on it; I treat it as a secondary issue that also needs explicit caveats. The reader's note about prior combined demonstrations, if accurate, also weakens the novelty framing but is secondary to the missing hardware training evidence. I do not recommend rejection: the device data (forming yield, 32 states, low programming noise, open-loop response) are a genuine engineering contribution, and code is provided for the simulations. The conditional verdict should require clear separation of measured results from simulated projections and, ideally, a small hardware training demonstration before 'all-in-one' is claimed. This is consistent with the reader's CONDITIONAL verdict, so no verdict change is needed.","tokens_in":25248,"tokens_out":9712,"duration_ms":90976,"concrete_test":"Train a small fully connected network (e.g., two layers, binarized MNIST subset) on the actual 8x4 CMO/HfOx array using the AGAD algorithm with the open-loop pulse scheme of Fig. 5 and compare final accuracy with the aihwkit simulation of Fig. 6b using the same experimentally extracted device parameters. Agreement within 1-2% would validate the simulated training pillar; a large gap would show that the central 'on-chip training' claim is not yet demonstrated.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central differentiator of this paper—a single BEOL-integrated CMO/HfOx platform that performs both on-chip training and long-term inference—is supported for inference by array measurements, but the training pillar is only simulated. Section 2.3.2 ('Tiki-Taka training simulations') and Methods 4.7 ('HW-aware simulation of analog training') make this explicit: the MNIST and LSTM accuracies in Fig. 6 are produced by the aihwkit generalized soft-bounds model fitted to the 32-device open-loop pulse responses of Fig. 5, not by training on the 8x4 array. The abstract's statement that 'training accuracy closely matching the software equivalent is achieved' therefore presents a simulation projection as a demonstrated capability. This matters because the paper's framing ('has yet to be reported', Section 1) claims a first unified demonstration; without a hardware training result, the all-in-one claim reduces to measured device parameters favorable for training plus a model-based prediction. The model may miss array-level effects present in a real training loop—weight-update accumulation under open-loop pulses, ADC/DAC quantization during gradient reads, IR drop during transposed MVMs, conductance drift between updates, and absence of verification—none of which are validated against an actual on-chip training experiment.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper reports an 8x4 BEOL-integrated CMO/HfOx ReRAM array in a 1T1R configuration and uses it to support claims of an 'all-in-one' analog AI platform for both on-chip training and long-term inference. Measured results include forming statistics, quasi-static switching with 8W polarity, 35 programmable conductance levels, low programming noise, one-week conductance relaxation data, and open-loop pulse-response statistics. System-level claims are obtained by hardware-aware simulations in IBM's aihwkit: 64x64 MVM accuracy projections up to 10 years after programming, and MNIST/LSTM training accuracy using the AGAD algorithm. The paper positions these simulations as evidence that the same array can support both training and inference acceleration.","tokens_in":25589,"tokens_out":3362,"duration_ms":37330,"significance":"If the central claims were fully supported, the work would be a valuable device-platform demonstration: low programming noise (sub-0.1 uS), 32+ distinguishable states, BEOL integration in a 1T1R array, and open-loop response statistics are useful for the analog in-memory computing community. The explicit reporting of fitted model parameters and code availability are strengths. However, the headline system-level contributions are model extrapolations rather than measured array-level results, so the significance as an 'all-in-one accelerator demonstration' is currently prospective rather than demonstrated.","major_comments":[{"comment":"The claim of demonstrated on-chip training is not supported by hardware measurements. The MNIST and LSTM results in Fig. 6 are produced by aihwkit simulations using the generalized soft bounds model fitted to the 32-device open-loop pulse responses of Fig. 5; Methods 4.7 explicitly states 'HW-aware simulation of analog training.' No training loop was executed on the 8x4 array. The abstract's statement that 'training accuracy closely matching the software equivalent is achieved' presents a simulation projection as an experimental achievement. Please either add measured array-level training results or reframe the abstract, Section 1, and Table 1 so that the training pillar is described as a hardware-calibrated simulation, not a demonstration.","section":"Abstract; Section 2.3.2; Methods 4.7"},{"comment":"The 10-year MVM projection is an unsupported extrapolation. The extended relaxation characterization covers one week at a single representative conductance (50 uS), and the insets of Fig. 4e fit the mean and standard deviation as linear functions of log time. The assumption that this trend continues for 10 years is not physically justified in the manuscript, and no uncertainty band is given. Because the headline factor-of-20 and factor-of-3 improvements over Wan et al. are derived from this extrapolation, the 10-year inference claim currently rests on an unvalidated fitting assumption. Please either restrict the retention claims to the measured timescale, provide a physics-based justification with uncertainty quantification, or add longer-term experimental data.","section":"Section 2.2.2; Fig. 4e; Methods 4.6.2"},{"comment":"The comparison to Wan et al. [9] compares a simulation against an experiment. The Wan et al. RMSE of approximately 0.58 is stated to be experimentally determined, whereas the CMO/HfOx RMSE of 0.03 at 1 s and 0.2 at 10 years is generated by aihwkit with a dedicated phenomenological noise model fitted to this work's device data. The simulation conditions also differ in array size, programming scheme, and the specific quantization and IR-drop settings. This is therefore not a controlled head-to-head benchmark. Please state these differences explicitly and describe the factor-of-20/3 claims as projected, model-based improvements rather than demonstrated advantages.","section":"Section 2.2.2; Fig. 4f"},{"comment":"The MVM and training simulations are in-sample evaluations of the same fitted device models, which limits their predictive force. The programming noise coefficients (Fig. 3e), the relaxation coefficients (Fig. 4e), and the generalized soft bounds parameters (Methods 4.7.1) are all extracted from the same measured device responses that are then used as simulation inputs. The resulting accuracy numbers therefore encode the fitted assumptions rather than independently validating the model. Please add a clear statement that the simulations are calibrated projections, and ideally validate the model on held-out devices or on an actual 64x64 array if the extrapolated claims are retained.","section":"Methods 4.6; Methods 4.7; Fig. 4f"}],"minor_comments":[{"comment":"The claim that relaxation is independent of the programmed conductance is supported by one-hour data spread across the range and by one-week data at a single state (50 uS). Please clarify in the text that the state independence has not been verified on the one-week timescale across the full conductance window.","section":"Section 2.2.2; Fig. 4c/4d"},{"comment":"The NSR definition in Eq. (3) is written as sigma_DeltaGsp / DeltaGsp, but the text reports values around 90%. Please define whether this is a percentage ratio and clarify the normalization used in the reported metric.","section":"Section 2.3.1; Eq. (3)"},{"comment":"Equation (4) appears malformed: 'nabla . Je = nabla . (sigma(-nabla V) = 0' has a misplaced equality. It should presumably read 'nabla . (sigma(-nabla V)) = 0' or equivalent. Please correct.","section":"Methods 4.2; Eq. (4)"},{"comment":"The manuscript uses '8W' and 'C8W' switching polarity without defining the notation in the figure captions or in the text. Please add a definition, since these terms are not self-explanatory to all readers.","section":"General"},{"comment":"The column 'Model Fidelity' is not defined by a quantitative metric. Since the table is used to benchmark the device model, please state how 'Medium' and 'High' are assessed, or provide a numerical fidelity score.","section":"Table 1"},{"comment":"The figure caption states that the simulations consider 'experimental programming noise, conductance relaxation, limited input/output quantization and IR-drop,' but the Discussion later states that read noise is not included. Please add a note in the caption and in the text to avoid ambiguity about which measured non-idealities are included.","section":"Section 2.2.2; Fig. 4f caption"}],"recommendation":"major_revision","confidential_remarks":"The device characterization and model fitting are careful and publishable, but the paper's framing substantially overstates what is demonstrated. The 'all-in-one' claim depends on simulated training and on a 10-year extrapolation from one week of relaxation data. I recommend major revision. If the authors can add a genuine hardware training demonstration or clearly reposition the paper as a device-aware simulation study with explicit caveats, the contribution would be appropriate for the journal. The current abstract, however, should not be accepted as written."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"First thing to know: this is a solid device paper wearing an overclaiming coat. The array-level characterization of CMO/HfOx ReRAM—8W polarity in 1T1R cells, 100% forming yield, 35 states, programming noise under 100 nS—is careful, well-documented, and a real step forward for this material system. The relaxation measurements and the MVM simulations that include programming noise, quantization, and IR drop are done honestly, with the models clearly derived from measured data.\n\nThe soft spot is the headline. The 'all-in-one' claim—on-chip training and inference on one platform—is not supported by the experiments. Training is simulated in aihwkit using parameters fitted to the open-loop pulse data; no on-chip training loop was run. The abstract's \"training accuracy closely matching the software equivalent is achieved\" presents a simulation as a demonstrated capability. That needs to be fixed. The 10-year inference projection also comes from a linear fit to one week of relaxation data; again, that's a projection, not a measurement. And the abstract's claim that a unified platform 'has yet to be reported' ignores Wan et al.'s RRAM chip, which did on-chip training and inference; this paper itself cites it but calls it inference-only, which is inaccurate.\n\nNone of this sinks the device contribution. The low programming noise, the state-independent relaxation, and the 8W polarity are real and useful. The paper deserves a serious referee and, after major revision, publication—but only if the authors clearly separate measured results from simulated projections, correct the prior-art framing, and soften the 10-year claims.\n\nI would bring it to a reading group to discuss the gap between device metrics and system claims, but I wouldn't cite the training results.","headline":"Solid device characterization wrapped in an overclaiming all-in-one narrative: training is simulated, not measured, and prior art is mischaracterized.","tokens_in":26154,"tokens_out":3727,"would_cite":true,"duration_ms":38344,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"A single CMO/HfO$_x$ ReRAM array can train neural networks on-chip and then retain weights for long-term inference, with matrix-vector-multiplication error lower by a factor of 20 at one second and 3 at ten years than prior analog memory.","keywords":["in-memory computing","analog ReRAM","CMO/HfOx","on-chip training","inference acceleration","conductance relaxation","weight transfer","1T1R array"],"falsifier":"Age the same programmed 50 $\\mu$S states for several additional months, and in parallel at elevated temperature such as 85 °C mapped back to room temperature, then test whether the mean drift and standard-deviation growth still lie on the log-time lines that produced the ten-year distributions. As a separate check, rerun the paper's $64\\times 64$ matrix-vector protocol with the reference chip's published device and drift parameters under identical 6-bit/8-bit quantization and readout conditions; if the reference RMSE under those conditions comes out materially below the 0.58 the paper uses as its baseline, the reported improvement factors would shrink by the same proportion.","tokens_in":25040,"feed_emoji":"⚡","tokens_out":20166,"duration_ms":175974,"temperature":0.7,"pith_summary":"The paper claims that a single memory technology can cover the whole analog-AI pipeline — on-chip training, weight retention, and long-term inference — on the same chip, something no previously reported platform has done. The devices are conductive-metal-oxide/HfO$_x$ resistive memory cells arranged as one-transistor-one-resistor units in the back-end-of-line of a 130 nm CMOS process, switching below 1.5 V and programmable into more than 32 distinguishable conductance states with programming noise between 10 and 100 nS. Hardware-aware simulations of a $64\\times 64$ tile project a matrix-vector-multiplication root-mean-square error of 0.03 one second after programming and 0.2 after ten years, which the authors report as improvements by a factor of 20 and 3 over a published ReRAM compute-in-memory chip. The same array, driven by identical open-loop pulses, shows gradual bidirectional conductance updates, and hardware-aware simulations of the AGAD algorithm built on those measured statistics reach 96.9% accuracy on MNIST against a 98.3% floating-point baseline, with comparable perplexity on an LSTM text task. If these results hold, an autonomous AI system could train itself on the chip and then keep running inference for years without separate digital training hardware.","feed_headline":"One ReRAM array does on-chip training and 10-year inference","feed_subtitle":"On one 64x64 core, matrix-multiply error drops 20x at one second; training lands within 1.4 points of software.","key_machinery":"The central object is the conductive-metal-oxide layer inserted between the top electrode and the HfO$_x$ switching layer, operated in filamentary mode so that charge transport is trap-to-trap tunneling described by a Mott-Gurney hopping model. The CMO layer confines the electric field and temperature at the filament tip, so resistive switching proceeds by radial redistribution of oxygen vacancies in a defect sub-band of the CMO, yielding the gradual bidirectional conductance updates that training needs. Two further choices carry the argument: re-optimizing the switching polarity from counter-eightwise to eightwise so the NMOS selector in each one-transistor-one-resistor cell can control the fast set transition, and an identical-pulse closed-loop programming scheme whose measured noise-versus-iteration trade-off feeds the inference simulations. The ten-year projection itself rests on a measured relaxation law — after programming, the mean of a conductance state drifts down and its standard deviation grows, both approximately linearly with the logarithm of elapsed time and nearly independent of the programmed value — extrapolated from one week of data, and on a hardware-aware simulation stack that folds in programming noise, relaxation, 6-bit/8-bit input/output quantization, and IR drop.","core_discovery":"On the paper's own terms, the finding is that the engineered conductive-metal-oxide layer in an otherwise conventional HfO$_x$ ReRAM stack produces a cell that satisfies the conflicting requirements of analog training and analog inference in the same array. For inference, closed-loop programming with fixed-amplitude pulses yields an almost ideal weight transfer — programming noise of 10 to 100 nS across a 10 to 90 $\\mu$S window, more than 32 stable states, and less than 10% overlap between adjacent state distributions after 10 minutes — and a relaxation process whose mean shift and distribution width grow linearly with log time and are nearly independent of the programmed conductance, which is what allows the ten-year accuracy projection. For training, the same cells respond to an open-loop identical-pulse scheme with gradual, bidirectional conductance changes across the whole array, averaging 22 states, a 61% symmetry-point skew toward depression, and a 90% noise-to-signal ratio at the symmetry point. Simulated AGAD training on these measured statistics reaches 96.9% test accuracy on MNIST against a 98.3% floating-point baseline, and near-baseline perplexity on a two-layer LSTM next-token task, which the paper takes as evidence that the platform scales from fully connected networks to sequence models. The unifying claim is that one one-transistor-one-resistor array, integrated in the back-end-of-line of a standard CMOS process with switching below 1.5 V, carries both capabilities, making a continuously retraining analog AI core physically plausible.","pith_inferences":["The paper's own numbers allow a near-free compensation scheme that it does not explicitly propose: since the mean relaxation drift is about $-0.7$ $\\mu$S and nearly state-independent, a single per-tile bias or a fixed post-programming wait-and-measure step could cancel most of the projected drift.","The log-time relaxation law is the long pole of the whole project; accelerated aging at elevated temperature (the paper cites under 4% drift after 72 hours at 85 °C for a similar stack) could validate or refute the ten-year projection in weeks rather than a decade.","The paper leaves open how repeated open-loop weight updates during on-chip retraining perturb already-programmed neighboring cells in a larger tile; if that disturbance is small, the training and inference demonstrations merge into a single continuous learning loop, which is the implicit end-goal of the all-in-one concept."],"forward_implications":["If the ten-year relaxation extrapolation holds, a programmed CMO/HfO$_x$ tile can serve untended for roughly a decade: the simulated $64\\times 64$ matrix-vector RMSE stays at 0.2 without refresh, re-programming, or digital compensation.","At short timescales the dominant matrix-vector error is input/output quantization (6-bit/8-bit), not the devices, so higher-resolution converters attached to the same array would push inference accuracy well below the reported RMSE.","On-chip training with the AGAD algorithm on the measured device statistics reaches 96.9% on MNIST, within 1.4 points of floating point, and near-baseline LSTM perplexity, so the same core is a credible training accelerator rather than an inference-only memory.","Because the technology is back-end-of-line integrated in a standard 130 nm CMOS process with sub-1.5 V switching, the all-in-one core can sit alongside conventional digital logic, and in larger $512\\times 512$ tiles the accuracy bottleneck shifts to IR drop on the wires rather than device non-idealities."],"supporting_citations":[{"why":"Supplies the reference ReRAM compute-in-memory chip whose experimentally determined matrix-vector RMSE of about 0.58 is the baseline for the claimed factor-of-20 and factor-of-3 improvements.","marker":"[9]"},{"why":"The parallel stochastic pulse-train scheme for in-memory outer-product weight updates that the open-loop training characterization is designed to support.","marker":"[20]"},{"why":"Defines the Tiki-Taka training algorithm whose relaxed device-symmetry requirements motivate the open-loop pulse characterization.","marker":"[21]"},{"why":"Provides the AGAD learning algorithm used for the hardware-aware training simulations, including its tolerance of imprecise reference conductances.","marker":"[23]"},{"why":"Earlier device-level demonstration that CMO/HfO$_x$ meets the criteria for Tiki-Taka training; this work extends it to a full back-end-of-line-integrated 1T1R array.","marker":"[24]"},{"why":"The analytical trap-to-trap tunneling model of the CMO/HfO$_x$ switching mechanism that this work adapts to eightwise polarity inside the 1T1R cell.","marker":"[26]"},{"why":"A phase-change-memory array result used as the comparison point for the claim that CMO/HfO$_x$ programming noise is more than an order of magnitude lower.","marker":"[34]"}],"fun_headline_variants":["Analog AI chip: same ReRAM array trains and infers","ReRAM core handles training and 10-year inference","All-in-one analog AI: on-chip training plus inference","64x64 ReRAM beats software in training, infers for years","Unified ReRAM array: continuous learning, long-term recall"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The load-bearing premise is that conductance relaxation measured for one week, with the mean and standard deviation fitted as linear functions of the logarithm of elapsed time, keeps following those same lines for ten years; if the drift slows, accelerates, or becomes dependent on the programmed state on longer timescales, the projected ten-year matrix-vector accuracy and the claimed factor-of-3 advantage lose their support.","fun_headline_variants_meta":{"raw":{"variants":["Analog AI chip: same ReRAM array trains and infers","ReRAM core handles training and 10-year inference","All-in-one analog AI: on-chip training plus inference","64x64 ReRAM beats software in training, infers for years","Unified ReRAM array: continuous learning, long-term recall"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000608,"raw_usage":{"total_tokens":2932,"prompt_tokens":1142,"completion_tokens":1790,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":758,"completion_tokens_details":{"reasoning_tokens":1705}},"tokens_in":758,"tokens_out":1790,"duration_ms":12660,"temperature":1.0,"reasoning_tokens":1705,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-08T22:24:40.163555+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Age the same programmed 50 $\\mu$S states for several additional months, and in parallel at elevated temperature such as 85 °C mapped back to room temperature, then test whether the mean drift and standard-deviation growth still lie on the log-time lines that produced the ten-year distributions. As a separate check, rerun the paper's $64\\times 64$ matrix-vector protocol with the reference chip's published device and drift parameters under identical 6-bit/8-bit quantization and readout conditions; if the reference RMSE under those conditions comes out materially below the 0.58 the paper uses as its baseline, the reported improvement factors would shrink by the same proportion.","supporting_citations":[{"cited_title":"Frontiers in Neuroscience10 (2016) https://doi.org/10.3389/fnins.2016.00333","cited_arxiv_id":null,"evidence_quote":"The parallel stochastic pulse-train scheme for in-memory outer-product weight updates that the open-loop training characterization is designed to support."},{"cited_title":"Frontiers in Neuroscience14(2020) https://doi.org/10.3389/fnins","cited_arxiv_id":null,"evidence_quote":"Defines the Tiki-Taka training algorithm whose relaxed device-symmetry requirements motivate the open-loop pulse characterization."},{"cited_title":"Nano Letters24(2024) https://doi.org/10.1021/acs.nanolett.3c03697","cited_arxiv_id":null,"evidence_quote":"Earlier device-level demonstration that CMO/HfO$_x$ meets the criteria for Tiki-Taka training; this work extends it to a full back-end-of-line-integrated 1T1R array."},{"cited_title":"Nanoscale Horiz.9, 775–784 (2024) https://doi.org/10.1039/D4NH00072B","cited_arxiv_id":null,"evidence_quote":"The analytical trap-to-trap tunneling model of the CMO/HfO$_x$ switching mechanism that this work adapts to eightwise polarity inside the 1T1R cell."}],"review_version":1}