{"id":"2163adb5-64f2-41b4-95a2-0c2ee75679e6","arxiv_id":"2502.08692","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":4.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":4,"one_line_summary":"A case study showing how knowledge distillation, pruning, and quantization let a small LSTM run on a low-end FPGA, with three split configurations trading off latency, power, and resource usage.","lead":"This paper deploys a compressed LSTM network on a low-cost FPGA for river water quality forecasting, testing three ways of splitting the model between the device and a server. It quantifies the trade-offs between speed, power, and resource use, but the split-learning training loop itself is not implemented or measured.","discovery_kind":"new_application","skeptic_critique":{"model":"deepseek-v4-flash","headline":"The deployed FPGA accelerator's accuracy is never measured: Table II reports only software student metrics, so the core claim that 8-bit fixed-point hardware preserves R2≈0.96 is unverified.","rationale":"The reader's conditional verdict is well aligned with the actual weakness in the paper. The central claim has two parts: compression preserves accuracy, and split-point choice trades resources. The first part is only supported by software metrics (Table II). The hardware deployment via hls4ml introduces 8-bit fixed-point arithmetic that can change numerical behavior, particularly for recurrent LSTM state over multiple time steps. Since the evaluation framework already exists, the absence of hardware accuracy is a clear omission, not a fundamental barrier. I also note a smaller inconsistency: the reported 3.40KB size for 871 parameters is exactly float32 size, so the 45.90x figure is a parameter ratio and does not reflect 8-bit quantization. This does not overturn the paper's engineering contribution but reinforces the need for a revised, accuracy-verified version. Therefore the verdict remains conditional; no change from the reader.","tokens_in":9517,"tokens_out":8341,"duration_ms":81648,"concrete_test":"Use the UART-based framework from Section III-C to run the held-out test set through each of the three synthesized accelerators (LSTM-DO-S, Split-A, Split-B) on the Basys 3 board. Compute MAE, MSE, and R2 from the accelerator outputs and compare them to Table II. The accuracy-preservation claim fails if the hardware R2 is below 0.90 or if MAE degrades by more than 20% relative to the software student; if the metrics match within tolerance, the concern is settled.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central performance claim is that the KD+pruned+quantized student maintains accuracy (R2 0.96) after FPGA deployment. However, Section IV-C (Table II) reports MAE/MSE/R2 only for the Keras software student; no end-to-end accuracy test of the synthesized hls4ml accelerator is presented. The paper's own conclusion (Section V) says the combination offers 'faster forecasting and improved memory efficiency, while maintaining performance,' but the 'maintaining performance' half is unmeasured on hardware. This matters because 8-bit fixed-point LSTM implementations can deviate from float32, especially through recurrent state accumulation over 15 time steps; hls4ml does not guarantee bit-exact equivalence with software. The existing evaluation framework (Section III-C, UART monitoring) would make such a test straightforward, and its absence is the weakest link in the claim. Relatedly, Table II's 3.40KB size for 871 parameters equals 4 bytes/parameter (float32), so the reported '45.90× size reduction' is a parameter-count ratio and does not reflect the stated 8-bit quantization; the actual quantized footprint is not reported. Both issues should be settled before the accuracy-efficiency trade-off is accepted.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"This paper reports a practical deployment study of split-learning LSTM models on a low-end Artix-7 FPGA for river-water dissolved-oxygen forecasting. The authors train an LSTM teacher and a smaller knowledge-distilled student, apply 70% pruning and 8-bit quantization, synthesize the compressed student with hls4ml, and evaluate three hardware configurations (full student, Split-A with two on-FPGA LSTM layers, and Split-B with one on-FPGA LSTM layer) in terms of resource utilization, latency, power, and scalability. The headline results are a 45.90x size reduction (156.06 KB to 3.40 KB) with the software student retaining R2 = 0.96 versus 0.97 for the teacher, and a split-point trade-off in which Split-B uses fewer resources and lower power at somewhat higher latency while enabling two parallel accelerators.","tokens_in":9709,"tokens_out":5604,"duration_ms":56321,"significance":"If the claims are substantiated, this is a useful end-to-end demonstration that knowledge distillation, pruning, and quantization can fit an LSTM edge model onto a small FPGA, with concrete hardware trade-offs that are easy to reproduce. The strengths are the real hardware evaluation on a specific FPGA board, the use of hls4ml, the explicit scalability metric, and the hardware evaluation framework. The distinction among LSTM-DO-S, Split-A, and Split-B is a practical and clearly presented trade-off. However, the paper does not verify that the deployed fixed-point accelerator preserves the reported software accuracy, and the reported model size is inconsistent with the stated 8-bit quantization. These gaps must be closed before the central accuracy-efficiency trade-off can be accepted.","major_comments":[{"comment":"The deployed hardware model's prediction accuracy is never measured. Table II reports MAE, MSE, and R2 for the Keras teacher and student only; the hls4ml-synthesized fixed-point accelerator is not evaluated end-to-end on the test set, even though the evaluation framework in Section III-C supports such a test. Since hls4ml does not guarantee bit-exact equivalence with floating point and recurrent accumulation over 15 time steps can amplify fixed-point errors, the conclusion in Section V that the compression combination 'maintains performance' is unsupported. Please add a hardware-in-the-loop accuracy measurement or clearly state that Table II corresponds only to the software model.","section":"Section IV-C, Table II; Section V"},{"comment":"The reported size of 3.40 KB for 871 parameters equals 4 bytes per parameter, i.e., float32, despite the statement in Section IV-B that post-quantization with 8-bit fixed-point precision is applied. The 45.90x compression ratio is therefore a parameter-count ratio rather than the memory footprint of the model actually deployed. Please report the quantized model's weight and bias footprint in bytes and recompute the compression ratio from that footprint.","section":"Section IV-B and Table II"},{"comment":"The latency and power comparisons are presented as single numbers with no measurement variability or repetition. For example, LSTM-DO-S at 2.82 us and 0.887 W versus Split-B at 3.54 us and 0.829 W are the basis for the claimed trade-off, but without repeated measurements or error bars it is unclear whether these differences are significant given the digital multimeter and timing methodology. Please provide repeated measurements or state the number of trials and the observed spread.","section":"Section IV-C, Table III"},{"comment":"The time-series test split is not described as chronological. For daily water-quality measurements, a random 70/30 split would leak future information into training and could inflate the reported R2 values. Please specify whether the split respects temporal order and, if it does not, re-evaluate the models with a temporal split.","section":"Section IV-A and Section V"},{"comment":"The split-learning communication aspect is not evaluated. The paper assumes ideal channel conditions and reports only on-chip FPGA metrics; no end-to-end split inference latency, bandwidth, or energy for the edge-server link is measured. The conclusion about the potential of split learning on resource-limited hardware therefore rests on FPGA-only results. Either add a communication-cost measurement or temper the conclusion to cover only FPGA acceleration of the edge sub-network.","section":"Section III-A and Section V"}],"minor_comments":[{"comment":"The text refers to 'Bertel et al. [3]' but the reference entry is 'J. Bartels et al.'; please correct the author name.","section":"Section II-B, reference [3]"},{"comment":"In Eq. (1), the notation is inconsistent: MSETL and MSETS are used without separate definitions, and the sentence 'MSE TL defined as...' contains an odd typographical break. Please define both terms cleanly.","section":"Section III-B, Eq. (1)"},{"comment":"The teacher's loss function is listed as 'LMSE' without a definition; please state that it is the standard mean squared error used for regression.","section":"Table I"},{"comment":"The 'Overall max utilization' row is not defined, and it is not derived from the scalability formula given for SC. Please explain how this value is computed.","section":"Section IV-C, Table III"},{"comment":"The paper states that the student architecture is chosen heuristically to reduce communication overhead and that a deeper architecture is preferred, but no procedure or reference is given for this design choice; please add a brief justification.","section":"Section IV-B"}],"recommendation":"major_revision","confidential_remarks":"This is a competent systems paper whose main gap is the missing end-to-end accuracy evaluation of the deployed fixed-point accelerator. That gap is addressable with the existing hardware framework and should be settled before publication. The reported model-size inconsistency also needs a correction. I would not recommend reject, because the efficiency and trade-off results are concrete and likely reproducible."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Colleague — quick take on arXiv:2502.08692. It's a hardware case study, not a research breakthrough, and it's mostly solid. The new bit: applying KD + pruning + quantization to an LSTM and deploying it on a low-end Artix-7 FPGA with three measured split configurations (full student, two LSTM layers, one LSTM layer). That combination, and the direct measurement of split-point trade-offs, is not in the prior art I can see. The hardware tables are the meat: Table III gives resource usage, latency, and power for three configurations, and the numbers support the design-trade-off story. Split-B uses 28% LUTs, 0.829 W, and allows two accelerators on the FPGA; the full student runs slightly faster (2.82 us vs 3.54 us) but uses more resources and power. Those measurements look credible.\n\nThe soft spots. Most important: the accuracy of the deployed hardware model is not measured. Table II reports only the software student's MAE/MSE/R2. The conclusion's 'maintaining performance' claim assumes hls4ml's 8-bit fixed-point implementation matches the float32 model, which is not guaranteed for recurrent layers over 15 time steps. The UART evaluation framework already exists, so this is a simple omission to fix, but it is load-bearing for the accuracy-efficiency claim. Second: the title says split learning, but no distributed training is done — the model is trained offline and then split for inference. That is a framing stretch. Third: the 45.9x compression ratio is computed from float32 sizes (156.06 KB to 3.40 KB), not the quantized 8-bit footprint, so it understates the actual memory savings. Minor, but the paper should be explicit. No error bars or code release also limit the reproducibility, though the methodology is described clearly enough.\n\nOverall: the hardware measurements are likely correct and the paper is honest about what it reports. The missing hardware accuracy test and the split-learning overclaim are the two things I'd want addressed before trusting the full claim. For practitioners working on FPGA edge inference for time series, this is a useful data point. I'd send it to peer review — a serious referee can push on the accuracy gap and the compression accounting.","headline":"Genuine engineering case study with honest hardware numbers, but the deployed model's accuracy is never measured and the split-learning label overshoots the implementation.","tokens_in":10327,"tokens_out":3608,"would_cite":false,"duration_ms":34736,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"By combining knowledge distillation, pruning, and quantization, the authors shrink an LSTM water-quality forecaster 45.90x while keeping its coefficient of determination at 0.96, and show that the FPGA split point determines whether an…","keywords":["split learning","LSTM","FPGA acceleration","knowledge distillation","pruning","quantization","time-series forecasting","water quality monitoring"],"falsifier":"Measure the actual FPGA accelerator's outputs on the held-out 30 percent test set and compare MAE, MSE, and R2 against the software student's values of 0.0574, 0.0087, and 0.96; agreement supports the deployment claim, while any substantial discrepancy shows the hardware implementation does not deliver the reported accuracy.","tokens_in":9272,"feed_emoji":"🌊","tokens_out":8952,"duration_ms":81439,"temperature":0.7,"pith_summary":"Split learning, which cuts a neural network so the edge device computes only the first layers and a server finishes the prediction, is usually discussed as a way to save communication and privacy. This paper shows that on a low-power FPGA, the more pressing question is where to make that cut. The authors train a 39,951-parameter LSTM teacher for dissolved-oxygen forecasting, distill it into an 871-parameter student using knowledge distillation, prune to 70 percent sparsity, quantize to 8-bit fixed point, and shrink the model $45.90\\times$ with only a one-point drop in $R^2$ (0.97 to 0.96). They then synthesize three FPGA variants that differ in the split point between edge and server. The measured result is a design map: full edge inference is fastest at 2.82 microseconds and 0.887 watts, while a single-LSTM split uses 28 percent of LUTs and 0.829 watts and leaves room for two parallel accelerators, at a higher 3.54 microseconds latency.","feed_headline":"45.9x smaller LSTM still predicts oxygen on a low-power FPGA","feed_subtitle":"The compressed student keeps R2 at 0.96 on Danube River data while fitting two parallel accelerators on one Artix-7.","key_machinery":"The load-bearing mechanism is a four-stage compression and deployment chain: knowledge distillation with a teacher LSTM and an MSE-based distillation loss, post-pruning to 70 percent sparsity, 8-bit fixed-point quantization, and a high-level synthesis flow that converts the student into LSTM hardware accelerators on the FPGA. The compression chain is what turns a 39,951-parameter teacher into an 871-parameter student whose accuracy nearly matches, and the split-point choice is what turns the freed resources into either lower power and lower latency or multiple parallel accelerators.","core_discovery":"On the paper's own terms, the central discovery is that combining knowledge distillation, pruning, and quantization compresses an LSTM water-quality forecaster by a factor of $45.90\\times$ in memory footprint, from 156.06 KB and 39,951 parameters to 3.40 KB and 871 parameters, while the coefficient of determination falls only from 0.97 to 0.96. When the student is mapped onto an Artix-7 FPGA, the split point between edge and server becomes the main design lever: full edge inference (LSTM-DO-S) achieves $2.82\\,\\mu s$ latency at 0.887 W, whereas the single-LSTM split (Split-B) drops power to 0.829 W, uses 28 percent of LUTs, and fits two accelerators on the chip (scalability 2) at $3.54\\,\\mu s$. The authors take this as evidence that split-point selection, not only compression, determines whether a split-learning deployment favors speed, balance, or resource efficiency.","pith_inferences":["Beyond the paper, the same recipe should extend to the other six water parameters the dataset records, since the system is multivariate-ready; a testable next step is training per-parameter students and measuring multi-accelerator throughput.","Beyond the paper, split-point selection can be read as a hardware-batch-size knob: moving layers to the server frees on-chip resources that reappear as extra parallel accelerators, a principle likely to carry over to other recurrent architectures.","Beyond the paper, one decisive check is left undone: an end-to-end accuracy measurement of the quantized FPGA implementation against the software student would directly confirm or refute the paper's claim of only slight performance degradation."],"forward_implications":["A $45.90\\times$ model-size cut with $R^2$ moving only from 0.97 to 0.96 implies memory-limited edge nodes can host useful forecasting models.","Split-B's scalability of 2 means one low-end FPGA can run two LSTM accelerators simultaneously, so a single buoy can serve multiple sensor streams in parallel.","The reported table gives deployers a concrete operating-point menu: LSTM-DO-S for lowest latency, Split-A for a balanced profile, and Split-B for lowest power and highest parallelism.","Because the two split points produce intermediate representations of size 5 and 150, the cost of moving data between memory and the inference core depends strongly on where the split is placed."],"supporting_citations":[{"why":"It supplies the LSTMSPLIT algorithm that partitions LSTM networks between edge and server, which underlies the split configurations.","marker":"[12]"},{"why":"It introduces knowledge distillation, the teacher-to-student transfer used to train the compressed LSTM.","marker":"[30]"},{"why":"It justifies replacing the KL divergence with MSE in the distillation loss, the exact loss used to train LSTM-DO-S.","marker":"[33]"},{"why":"It provides the end-to-end compression and FPGA deployment workflow that the paper adapts for RNNs.","marker":"[32]"},{"why":"It supplies the high-level synthesis flow that converts the trained and quantized model into the LSTM hardware accelerator.","marker":"[34]"},{"why":"It defines split learning, the distributed-training paradigm whose feasibility on FPGA is the paper's focus.","marker":"[5]"},{"why":"It is the earlier split-inference FPGA study that this work extends by adding actual hardware implementation and compression choices.","marker":"[20]"},{"why":"It provides the communication block used to connect the soft-core processor to the LSTM accelerator in the evaluation framework.","marker":"[35]"}],"fun_headline_variants":["45.9x smaller LSTM keeps R2 at 0.96 on FPGA edge","Split point beats compression for FPGA LSTM tradeoffs","Edge LSTM compressed 45.9x, R2 dips only to 0.96","How split learning trims an LSTM to 45.9x smaller on FPGA","FPGA split point: the real lever for edge LSTM efficiency"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The deployed FPGA version actually reproduces the software student's accuracy; only the software model is evaluated in the accuracy table, so the hardware's true error is assumed rather than measured.","fun_headline_variants_meta":{"raw":{"variants":["45.9x smaller LSTM keeps R2 at 0.96 on FPGA edge","Split point beats compression for FPGA LSTM tradeoffs","Edge LSTM compressed 45.9x, R2 dips only to 0.96","How split learning trims an LSTM to 45.9x smaller on FPGA","FPGA split point: the real lever for edge LSTM efficiency"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000844,"raw_usage":{"total_tokens":3668,"prompt_tokens":928,"completion_tokens":2740,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":544,"completion_tokens_details":{"reasoning_tokens":2637}},"tokens_in":544,"tokens_out":2740,"duration_ms":16873,"temperature":1.0,"reasoning_tokens":2637,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-08T04:47:32.497225+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Measure the actual FPGA accelerator's outputs on the held-out 30 percent test set and compare MAE, MSE, and R2 against the software student's values of 0.0574, 0.0087, and 0.96; agreement supports the deployment claim, while any substantial discrepancy shows the hardware implementation does not deliver the reported accuracy.","supporting_citations":[{"cited_title":"LSTMSPLIT: Effective SPLIT Learning based LSTM on Sequential Time-Series Data","cited_arxiv_id":"2203.04305","evidence_quote":"It supplies the LSTMSPLIT algorithm that partitions LSTM networks between edge and server, which underlies the split configurations."},{"cited_title":"An end-to-end workflow to efficiently compress and deploy dnn classifiers on soc/fpga,","cited_arxiv_id":null,"evidence_quote":"It provides the end-to-end compression and FPGA deployment workflow that the paper adapts for RNNs."},{"cited_title":"Fast inference of deep neural networks in fpgas for particle physics,","cited_arxiv_id":null,"evidence_quote":"It supplies the high-level synthesis flow that converts the trained and quantized model into the LSTM hardware accelerator."},{"cited_title":"Distributed learning of deep neural network over multiple agents,","cited_arxiv_id":null,"evidence_quote":"It defines split learning, the distributed-training paradigm whose feasibility on FPGA is the paper's focus."},{"cited_title":"Split learning on fpgas,","cited_arxiv_id":null,"evidence_quote":"It is the earlier split-inference FPGA study that this work extends by adding actual hardware implementation and compression choices."},{"cited_title":"Design for portability of reconfigurable virtual instrumentation,","cited_arxiv_id":null,"evidence_quote":"It provides the communication block used to connect the soft-core processor to the LSTM accelerator in the evaluation framework."}],"review_version":1}