{"id":"13b61420-0e49-40ad-a7ff-5acddbf2ff6e","arxiv_id":"2505.05586","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":4.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":2,"one_line_summary":"The JUNO SPMT high-voltage splitter board was designed, built, and tested to meet the detector's 20-year reliability and signal-distortion requirements, with 430 of 435 manufactured boards passing functional tests.","lead":"Engineers designed and qualified a 64-channel high-voltage splitter board that biases and reads out the 25,600 small photomultiplier tubes in the JUNO neutrino detector. The paper documents the design, signal-quality and reliability measurements, and the production and testing of 435 units.","discovery_kind":"extension","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Reliability conclusion conflates per-component FIT with the per-UWB 1900 FIT budget; weighting the reported FITs by component counts already exceeds 1900 per HVS/UWB, so the 20-year claim is unsupported even before the assumed 1 eV activation energy.","rationale":"Good-faith reading: the paper is a thorough, candid engineering report. The measured electrical performance—noise/distortion below 200 uV, crosstalk 1.6%/1.1%, reflection artifacts 0.9%/0.3%, 430/435 production yield—is credible and well documented. The design reasoning (clearances, impedance control, compound encapsulation, redundancy) is sound, and the authors explicitly flag several limitations (unexplained crosstalk reflection mechanism, ESD artifacts, damaged multiplexers, omitted compound in aging). I agree with the reader that the longevity extrapolation is the weak point, but I find an even more immediate, checkable flaw: the FIT argument compares component-level numbers to a system-level requirement. Summing the paper's own reported FITs weighted by the component counts on the HVS/UWB exceeds the 1900 FIT budget, and the capacitor FIT in Table 3 appears arithmetically inconsistent (50.7 rather than 10.4 for the stated 122.8 h test). Combined with the assumed Ea=1 eV and single-board accelerated aging without compound or HVUs, the conclusion that 'the HVS is expected to operate reliably throughout JUNO's 20-year operational lifetime' is not supported by the reliability evidence as presented. This does not call into question the present-day measurements; it means the reliability case needs a proper system-level FIT model and either a measured activation energy or a conservative sensitivity analysis. The conditional verdict is therefore retained.","tokens_in":27863,"tokens_out":17647,"duration_ms":194814,"concrete_test":"Perform the arithmetic check on the paper's own reliability numbers: using Eqs. (1)-(6), recompute the capacitor FIT from Table 3 (D=100, H=122.8 h, Te=373.15 K, Ta=295.15 K, Ea=1 eV, 90% CL), and sum the component FITs per HVS and per UWB with the counts stated in Sections 3.3/3.5/6.5/6.6 (1 PCB, 8 HVUs, 8 R5000F diodes, 64 C0G capacitors per HVS; two HVS per UWB). If either sum exceeds 1900, the paper's claim that the component FITs are below the 1900 requirement does not establish system-level compliance. As a second step, repeat the sum with Ea=0.7 eV for the PCB to quantify the Arrhenius sensitivity.","verdict_should_be":"UNCHANGED","load_bearing_attack":"Section 6.2 derives FIT<1900 from the system-level budget of 10% UWB loss after six years, i.e., failures per 10^9 UWB-hours. Sections 6.3-6.6, however, compute FIT per individual device: Eq. (2) uses D = number of devices tested (100 diodes, 100 capacitors, 186 HVUs, 1 PCB). These are not interchangeable. Weighting the reported values by the component count on one UWB (two HVS boards, 64 channels each) gives: 2 PCBs x 900.1 + 16 HVUs x 53 + 16 R5000F diodes x 10.4 + 128 decoupling capacitors x 10.4 = 4146 FIT, already above 1900, and the HVS alone (900.1 + 8x53 + 8x10.4 + 64x10.4 = 2073 FIT) exceeds the budget before adding resistors, connectors, ESD diodes, ABC, or GCU. Moreover, Table 3 states the capacitor test ran 122.8 h; applying Eqs. (1)-(6) with Ea = 1 eV yields a capacitor FIT of about 50.7, not 10.4, which makes the discrepancy worse. The conclusion 'expected to operate reliably throughout JUNO's 20-year operational lifetime' therefore does not follow from the data as presented. This is independent of the additional Arrhenius extrapolation concern (assumed Ea = 1 eV and aging a single PCB without Pentelast-712 compound and with HVUs outside the oven, Section 6.6), which would raise the PCB FIT above 10^4 if Ea were 0.7 eV.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"This paper documents the design, performance, and production qualification of the High Voltage Splitter (HVS) board for the JUNO SPMT system. The HVS provides high-voltage biasing to 3-inch PMTs and decouples the physics signal for readout. The authors describe the system-level constraints, circuit and physical layout, signal-integrity measurements (SPE waveforms, reflections, crosstalk), ESD protection validation, accelerated-aging reliability estimates, and the production/QC campaign in which 430 of 435 boards passed functional testing. The paper's stated central claim is that the HVS is expected to operate reliably throughout JUNO's 20-year operational lifetime, based on measured compliance with system requirements and on component FIT values that are reported to be below the derived 1900 FIT budget.","tokens_in":28119,"tokens_out":9997,"duration_ms":95630,"significance":"A documented, mass-produced detector front-end board is valuable to the instrumentation community, and the paper has real strengths: the design rationale is detailed, the signal-integrity measurements are presented with enough setup information to be reproducible, the production testing procedure is clearly described, and the limitations of the accelerated-aging test are at least partially acknowledged. If the reliability accounting were correct, the paper would be a useful reference for high-voltage electronics in large neutrino detectors. However, the central reliability conclusion is currently not supported by the FIT analysis as presented: per-component FIT values are compared against a system-level per-UWB budget without summing over the components in a UWB, and the extrapolation to 20 years depends on an assumed activation energy. These issues are load-bearing for the paper's main claim and require substantive revision.","major_comments":[{"comment":"The 1900 FIT requirement is derived in Eq. (7) from a per-UWB failure budget of 10% loss after six years, but the paper compares each component type's FIT individually to 1900 instead of summing the FITs of all components in one UWB. A UWB contains two HVS boards, each servicing 64 channels. Weighting the reported per-component FITs by the component counts on one UWB gives 2×900.1 (PCB) + 16×53 (HVU) + 16×10.4 (R5000F diodes) + 128×10.4 (decoupling capacitors) ≈ 4146 FIT, which already exceeds 1900 before including ESD diodes, series resistors, connectors, the ABC board, or the GCU. Even using the vendor-provided FIT values for the diodes and capacitors (0.1 and 0.4, respectively), the sum is approximately 2700 FIT. The conclusion in Section 8 that 'the HVS is expected to operate reliably throughout JUNO's 20-year operational lifetime' therefore does not follow from the data as presented; the budget must be applied to the summed system FIT.","section":"Section 6.2 and Section 8"},{"comment":"The reported capacitor FIT of 10.4 is inconsistent with the stated test conditions and with Eqs. (1)-(6). Using Ta=295.15 K, Te=373.15 K, Ea=1 eV, D=100 capacitors, H=122.8 h, and r=0 observed failures, the 90%-confidence FIT is χ²(0.9,2)/(2·EDH)·10^9 ≈ 50.6, not 10.4. The value 10.4 corresponds to the diode test duration H=598.5 h. This arithmetic discrepancy should be corrected; with the corrected capacitor FIT, the summed system FIT from the previous comment becomes even larger.","section":"Table 3 and Section 6.4"},{"comment":"The 20-year reliability projection is not robust to the assumed activation energy. For the diodes, capacitors, and PCB, Ea=1 eV is adopted 'in absence of empirical data' (Sections 6.3, 6.4, and 6.6), while Section 6.1.1 quotes 0.7 eV as the generic value for diode-type semiconductors. If Ea=0.7 eV, the single-board PCB test (D=1, H=689.5 h, Te=373.15 K) gives Af≈315 and a 90%-confidence FIT of about 1.1×10^4, already far above 1900; the capacitor FIT similarly rises to about 600. In addition, the PCB aging test omits the Pentelast-712 compound and keeps the HVUs outside the oven, so it does not exercise the insulation system exactly as installed. The paper should either provide measured Ea values, a sensitivity scan over plausible Ea values, or a clearly stated conservatism argument before claiming a 20-year lifetime.","section":"Sections 6.3, 6.4, and 6.6"}],"minor_comments":[{"comment":"The phrase 'usedtousedtocommunicateandcontrol' contains a duplicated word; it should read 'used to communicate and control'.","section":"Section 5.1"},{"comment":"The worst-case crosstalk peaks (1.6% positive and 1.1% negative) are quoted without uncertainties or the number of channel pairs and measurement repetitions used; please provide at least the sample size and a statement of measurement repeatability.","section":"Section 5.4"},{"comment":"The reflection artifacts are quoted as 'roughly 0.9% and 0.3%' without specifying the cable length, trigger settings, and number of channels over which the maximum was observed; the text should state these conditions explicitly.","section":"Section 5.3"},{"comment":"The equivalence of 689.5 h at 100 °C to 291 years is stated without showing the calculation; please state the assumed ambient temperature, activation energy, and acceleration factor at the point of the claim.","section":"Section 6.6"},{"comment":"The requirement is quoted as 'below 1/10 of an SPE' and separately as 'roughly 200 μV', while Section 5.2 gives a typical SPE amplitude of about 2 mV; please clarify whether the 1/10 criterion is applied to peak amplitude, RMS noise, or both.","section":"Section 2.1.6 and Section 5.2"},{"comment":"Refs. [18] and [24] are listed as 'Paper in preparation', and key reliability inputs in Sections 6.3-6.5 rely on private correspondence [35,36]; these limitations should be noted where the values are used, as they currently reduce the reproducibility of the reliability assessment.","section":"References"}],"recommendation":"major_revision","confidential_remarks":"The paper is well within the scope of physics.ins-det and the engineering content is generally solid. The main concern is the FIT accounting: the per-component comparison to a per-UWB budget, together with the assumed activation energy, undermines the paper's central 20-year reliability claim. I see no reason to doubt the measurements themselves, but the reliability argument needs to be reworked before the claim can stand. The editor may also wish to confirm that the unpublished references cited for HVU and HVD reliability will be available to readers."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"First: this is a real, deployed design, not a simulation. The authors built 435 boards, burned them in, functionally tested them, and measured crosstalk and reflections on the final version. Those parts are credible and worth reading. Second: the reliability section has a load-bearing flaw, and the stress-test note is correct.\n\nThe paper derives a system-level FIT budget of 1900 per UWB from the 10% loss in 6 years requirement. Then it reports per-device FITs (diodes 10.4, capacitors 10.4, HVUs 53, PCB 900.1) and appears to compare each to 1900. That is a unit mismatch. Summing the per-device rates over the components in one UWB gives about 4100 FIT using the paper's own numbers, and the HVS boards alone account for roughly 2000 before counting anything else. So the conclusion that the board meets the system reliability requirement does not follow.\n\nThere is also an arithmetic error in the capacitor FIT. Applying the paper's own equations with 100 capacitors, 122.8 hours, zero failures, and Ea = 1 eV gives a FIT of about 51, not 10.4. The 10.4 value matches the diode test only if the diode's 598.5 hours is mistakenly used for the capacitor run. That would be caught in a careful review.\n\nOn top of that, the 1 eV activation energy is assumed for diodes, capacitors, and PCB, and the PCB test is one board aged without the Pentelast-712 compound. With Ea = 0.7 eV the PCB FIT climbs above 10^4, so the 20-year claim is not robust. The authors flag some of these limitations in the text, which is to their credit, but the conclusion still overstates what the data support.\n\nThe rest of the paper is solid. The design rationale is clear, the SPE waveform and crosstalk measurements are detailed and show the board works within the 1/10 SPE distortion budget, and the production yield with burn-in and functional testing is genuinely useful for anyone building similar readout electronics. The paper also identifies its own unexplained artifacts, like the high-frequency ESD waveform and the damaged multiplexers, rather than hiding them.\n\nWho is this for? People building PMT readout chains, especially for underwater or long-lifetime detectors. They will get value from the physical design and production testing sections. The reliability analysis needs a serious rework before the paper's main claim is acceptable. If the paper goes to peer review, the referee should ask the authors to redo Section 6 with proper per-UWB FIT summing, correct the capacitor calculation, and present FIT as a function of activation energy. I would not desk reject it; the engineering content is real. But the 20-year conclusion should not stand without revision.","headline":"Solid engineering documentation; the reliability section's FIT accounting is wrong and the 20-year claim is unsupported.","tokens_in":29171,"tokens_out":6925,"would_cite":false,"duration_ms":65871,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"The High Voltage Splitter board for JUNO's small PMTs is claimed to survive the detector's 20-year lifetime.","keywords":["JUNO","SPMT","High Voltage Splitter","PMT readout electronics","accelerated aging","Arrhenius model","failure rate FIT","printed circuit board design"],"falsifier":"Age replicated HVS boards at three different temperatures below the compound's melting point, for example 60, 70, and 80 degrees Celsius, long enough to observe actual failures, and fit the Arrhenius plot to obtain the true activation energy. If that energy is below about 1 eV, the quoted FIT values and the 20-year expectation are over-optimistic; if it is above, they are conservative. A complementary single run at a higher temperature with the Pentelast-712 compound present would reveal whether compound melting or outgassing introduces failure modes absent from the current test.","tokens_in":27560,"feed_emoji":"⚡","tokens_out":5015,"duration_ms":45663,"temperature":0.7,"pith_summary":"The paper documents the design, qualification, and mass production of the High Voltage Splitter (HVS), the first board in the readout chain of JUNO's small photomultiplier (SPMT) system. Its central claim is that the HVS is fit for deployment: it respects the analog noise and distortion budget (below one tenth of a single photoelectron, roughly 200 microvolts), keeps crosstalk and reflections in the per-cent range, passes all 430 production functional tests, and is expected to operate reliably for JUNO's 20-year lifetime. A sympathetic reader would care because 25,600 PMTs in an inaccessible underwater detector cannot be serviced; the board's longevity is a condition for the experiment's physics program, from neutrino mass ordering to supernova neutrinos.","feed_headline":"JUNO splitter board bets on 20 years of underwater service","feed_subtitle":"Accelerated aging at 100 C claims 291 equivalent years, yet the 1 eV activation energy is assumed, not measured.","key_machinery":"The central object that carries the argument is the HVS board itself (version 3.2), an eight-layer, 365 mm by 190 mm FR-4 PCB with 64 channels, 50 ohm impedance-controlled traces, 4.77 mm high-to-low voltage clearances, and Pentelast-712 compound encasing the decoupling capacitors and MCX connectors. Three design mechanisms do the work: the 20 MOhm series resistors, which limit the current draw of a shorted channel to 75 microamps so a subgroup tolerates two failures; the reverse-biased BAV99S protection diodes, which clamp ESD transients before they reach the CATIROC front-end chip; and the C0G 3.9 nF decoupling capacitor, selected for its voltage-stable capacitance and minimal overshoot. The paper's quantitative claim of 20-year reliability, however, is carried not by the board design alone but by the Arrhenius acceleration factor that converts oven hours into equivalent device hours at ambient temperature.","core_discovery":"The paper's claim is that a carefully constrained board can simultaneously deliver high voltage (up to 1.42 kV) to 64 SPMTs, decouple the roughly 2 mV single-photoelectron pulses, keep all signal artifacts below the 1/10-SPE threshold, and survive continuous underwater operation for the experiment's 20-year design life. The evidence is a chain of measured numbers: worst-case crosstalk of 1.6% positive and 1.1% negative, reflection artifacts at 0.9% and 0.3%, FIT values of 10.4 for the high-voltage diodes, 10.4 and 0.4 for the capacitors, 53 for the HVUs, and 900.1 for the board itself, against a system requirement of 1900; and a production yield of 430/435 boards passing functional and burn-in testing. The reliability figure rests on an accelerated-aging extrapolation using the Arrhenius equation with an activation energy of 1 eV, chosen, in the authors' words, in absence of empirical data.","pith_inferences":["If the assumed 1 eV activation energy is an overestimate, then the same hours at 100 degrees Celsius correspond to far fewer equivalent years at 21 degrees Celsius; a measurement of the true activation energy from multi-temperature aging would settle the 20-year expectation directly.","The observed increase in reflection amplitude after aging hints that dielectric aging affects impedance matching; monitoring the in-situ SPE waveform over the first years of JUNO operation would test whether the same drift appears at ambient temperature.","The same board design and reliability methodology could transfer to other long-lived underwater or inaccessible detectors, but only if the aging extrapolation is anchored to measured activation energies for each material class (diode, capacitor, PCB laminate, encapsulation compound)."],"forward_implications":["The board meets the SPMT system's analog budget: noise and distortion below 200 microvolts, so false triggers from reflections or crosstalk are suppressed at the single-photoelectron threshold.","The redundancy scheme means that up to two shorted PMTs per 16-channel subgroup can be tolerated before the HVU saturates, so single-channel failures degrade the detector gracefully.","With measured FIT values below 1900, the probability of losing more than 10% of the readout channels in the first six years is expected to stay within the system requirement.","The 430/435 production yield and the burn-in plus automated functional testing provide the quality assurance needed to install the boards in an inaccessible underwater detector."],"supporting_citations":[{"why":"Sets the SPMT nominal gain and the 900-1300 V operational voltage range that the HVS must support.","marker":"[21]"},{"why":"Origin of the HVU DC-DC converter design reused for the SPMT system, including its prior reliability qualification.","marker":"[22]"},{"why":"Defines the CATIROC discriminator at 1/3 of a single photoelectron, against which the noise and distortion budget is set.","marker":"[25]"},{"why":"Provides the Pentelast-712 insulation properties and melting constraints that shape the board's compound application and burn-in temperature limits.","marker":"[26]"},{"why":"The IPC-2221B standard supplies the clearance guidelines that determine the high-voltage layout rules of the board.","marker":"[33]"},{"why":"The Arrhenius HTOL accelerated-testing method is the foundation for converting oven hours into equivalent device hours for every FIT value.","marker":"[34]"},{"why":"Manufacturer reliability data for the R5000F high-voltage diodes used to cross-check the experimental FIT value.","marker":"[35]"},{"why":"Manufacturer failure-rate report for the C0G capacitors used to cross-check the experimentally derived FIT value.","marker":"[36]"},{"why":"Documents the overshoot dependence on decoupling capacitance and cable length, guiding the capacitor selection.","marker":"[23]"},{"why":"Provides the earlier JUNO prototype study of PMT overshoot that supports the capacitor choice rationale.","marker":"[28]"}],"fun_headline_variants":["JUNO splitter board bets 20 years on an assumed 1 eV","High-voltage splitter: 1.42 kV, 64 PMTs, extrapolated lifetime","SPMT splitter holds 20-year line, but reliability is assumed","JUNO's HVS board: 430/435 pass, yet aging model unmeasured"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The 20-year reliability expectation assumes that the Arrhenius law with an activation energy of 1 eV, chosen in absence of empirical data, correctly translates a 689.5-hour test at 100 degrees Celsius into 291 years of operation at 21 degrees Celsius, and that the failure modes of a board aged without its insulating compound and with its HVUs outside the oven match those of the installed board.","fun_headline_variants_meta":{"raw":{"variants":["JUNO splitter board bets 20 years on an assumed 1 eV","High-voltage splitter: 1.42 kV, 64 PMTs, extrapolated lifetime","SPMT splitter holds 20-year line, but reliability is assumed","JUNO's HVS board: 430/435 pass, yet aging model unmeasured"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000541,"raw_usage":{"total_tokens":2609,"prompt_tokens":975,"completion_tokens":1634,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":591,"completion_tokens_details":{"reasoning_tokens":1543}},"tokens_in":591,"tokens_out":1634,"duration_ms":12904,"temperature":1.0,"reasoning_tokens":1543,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-15T23:02:16.595628+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Age replicated HVS boards at three different temperatures below the compound's melting point, for example 60, 70, and 80 degrees Celsius, long enough to observe actual failures, and fit the Arrhenius plot to obtain the true activation energy. If that energy is below about 1 eV, the quoted FIT values and the 20-year expectation are over-optimistic; if it is above, they are conservative. A complementary single run at a higher temperature with the Pentelast-712 compound present would reveal whether compound melting or outgassing introduces failure modes absent from the current test.","supporting_citations":[{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Sets the SPMT nominal gain and the 900-1300 V operational voltage range that the HVS must support."},{"cited_title":"Conforti, et al., Catiroc: an integrated chip for neutrino experi- mentsusingphotomultipliertubes,JournalofInstrumentation16(05) (2021) P05010","cited_arxiv_id":null,"evidence_quote":"Defines the CATIROC discriminator at 1/3 of a single photoelectron, against which the noise and distortion budget is set."},{"cited_title":"rep., KS Plast, accessed: 2024-10-23 (n.d.)","cited_arxiv_id":null,"evidence_quote":"Provides the Pentelast-712 insulation properties and melting constraints that shape the board's compound application and burn-in temperature limits."},{"cited_title":"rep., IPC (2012)","cited_arxiv_id":null,"evidence_quote":"The IPC-2221B standard supplies the clearance guidelines that determine the high-voltage layout rules of the board."},{"cited_title":"Nelson, Accelerated Testing: Statistical Models, Test Plans, and DataAnalysis,1st Edition,WileySeriesinProbability andStatistics, Wiley, 2004","cited_arxiv_id":null,"evidence_quote":"The Arrhenius HTOL accelerated-testing method is the foundation for converting oven hours into equivalent device hours for every FIT value."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Manufacturer reliability data for the R5000F high-voltage diodes used to cross-check the experimental FIT value."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Manufacturer failure-rate report for the C0G capacitors used to cross-check the experimentally derived FIT value."},{"cited_title":"Study of the front-end signal for the 3-inch PMTs instrumentation in JUNO","cited_arxiv_id":"2204.02612","evidence_quote":"Documents the overshoot dependence on decoupling capacitance and cable length, guiding the capacitor selection."},{"cited_title":"Luo, Y.-K","cited_arxiv_id":null,"evidence_quote":"Provides the earlier JUNO prototype study of PMT overshoot that supports the capacitor choice rationale."}],"review_version":1}