{"id":"e4b9897f-c836-462e-a6e8-9b4eb1cd3022","arxiv_id":"2505.21714","paper_version":4,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":1,"one_line_summary":"A custom RFSoC time-tagging data acquisition system with a custom analog frontend operated a superconducting nanocryotron shift register at 200 MHz, versus 83 MHz with commercial equipment costing seven times more.","lead":"The authors built a data acquisition system from a reprogrammable chip (RFSoC) and custom amplifiers that tests superconducting circuits faster and cheaper than commercial gear. It ran a superconducting shift register at 200 MHz, about 2.4 times the 83 MHz limit of commercial equipment costing seven times more.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"200 MHz operation claim rests on visual waveform interpretation despite an admitted artifact that blurs switching events; without a quantitative error-rate measurement at 200 MHz, the central speed comparison is not yet established.","rationale":"The reader's conditional verdict identifies the same weakest premise: the 200 MHz result is judged from waveforms despite an acknowledged clock-feedthrough artifact, with no quantitative error rate at that speed. My stress-test pass finds this to be the single most load-bearing concern, because the positive speed comparison collapses if the apparent output pulses at 200 MHz are artifacts rather than genuine data-dependent switching. The rest of the paper is solid: the analog frontend characterization shows a noise floor near the thermal limit and about 20 dB SINAD improvement over a passive breakout; the firmware architecture (sample discriminator, timetagging, trigger sharing) is described carefully; and the open-source release is a real independent artifact. The COTS comparison baseline uses a different amplifier chain and would benefit from explicit restatement, but that is secondary. The required fix is a straightforward measurement enabled by the presented system itself: record a known input pattern, threshold above the artifact, and report an error rate at 200 MHz. Until then, the correct verdict is CONDITIONAL, which is what the reader already recommended, so no verdict adjustment is needed.","tokens_in":16181,"tokens_out":3539,"duration_ms":36192,"concrete_test":"Re-run the shift register with the RFSoC system at 200 MHz for at least 10^5 clock cycles with a known repeating input pattern (e.g., 1010...), using the sample discriminator to record timetags and output pulse heights. Set the discriminator threshold above the amplitude of the clock-only feedthrough artifact, as measured with the input held in a fixed state, and count output events that exceed that threshold. Report bit-error rate versus clock frequency from 83 MHz to 200 MHz. If the measured error rate at 200 MHz is not below a pre-specified target (e.g., <1e-5 per bit), then the claim of operation at 200 MHz should be weakened to 'outputs observed' rather than 'circuit operating correctly.'","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central claim—that the RFSoC DAQ let the same shift register operate at 200 MHz versus 83 MHz—hinges on the Section 4 assertion that 'the same circuit could operate at 200 MHz' (Fig. 5c(iii)). The paper immediately qualifies this: at 200 MHz the fast clock edge 'results in substantial voltage pulses even when the nanocryotron does not switch,' which 'makes it more difficult to determine when the nanocryotron actually switched.' The displayed evidence for 'operate' appears to be visual identification of output pulses in captured traces, not a bit-error-rate measurement or a pre-specified thresholded count of correct state transitions. Because the apparent output pulses can be produced by clock feedthrough alone, a waveform that looks like a correct data pattern could actually be a failing circuit whose outputs are dominated by the differentiation artifact. This is the load-bearing soft spot: the headline improvement is exactly the 200 MHz operating point, and that is the point where the observable is admitted to be ambiguous. The COTS baseline (83 MHz from Ref. [13]) also involved a different amplifier chain, but even granting that comparison, the 200 MHz demonstration needs a quantitative correctness check. The system was explicitly designed for timetagging and error counting, so such a check is feasible and should have been reported. The abstract's 'nearly three-times' wording is also inaccurate (200/83 is 2.4x), but that is a correction, not the core fragility.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper describes a custom, open-source time-domain data acquisition system built around an RFSoC (ZCU111) with a custom analog frontend. The FPGA firmware implements real-time sample discrimination and timetagging for sparse data capture, and the system includes multi-GS/s AWG signal generation. The analog frontend is characterized in loopback, showing improved SINAD and a noise floor consistent with the specified LNA noise figure. As a demonstration, the authors use the system to test a previously characterized superconducting nanocryotron shift register and report operation at 200 MHz, compared with 83 MHz with commercial COTS equipment, claiming a nearly three-fold increase in maximum clock speed.","tokens_in":16312,"tokens_out":3183,"duration_ms":31511,"significance":"If the central speed claim is quantitatively established, this is a valuable contribution: a cost-effective, reproducible DAQ platform (with released firmware, software, and schematics) that combines wideband stimulus and time-tagging acquisition, potentially enabling error-rate studies of novel superconducting circuits at speeds beyond typical sub-GS/s COTS equipment. The thermal-noise-limited analog frontend and the real-time sample-discriminator firmware are useful building blocks for detector readout and nanocryotron logic testing. The open-source release is a concrete strength. However, the headline demonstration—operation of the shift register at 200 MHz—currently rests on visual waveform inspection and is not supported by an error-rate or pattern-verification measurement, so the significance of the speed claim is not yet fully established.","major_comments":[{"comment":"The claim that the shift register 'could operate at 200 MHz' is supported only by visual interpretation of captured waveforms, with no quantitative correctness criterion. The text itself states that at 200 MHz the fast clock edge 'results in substantial voltage pulses even when the nanocryotron does not switch,' making it 'more difficult to determine when the nanocryotron actually switched.' Since apparent output pulses can arise from clock feedthrough and differentiation effects without a true state transition, the displayed traces are insufficient to demonstrate that the circuit produced the correct output sequence. Given that the system is explicitly designed for event counting and time-tagging, a quantitative check—e.g., a known input pattern with a pre-specified acceptance threshold, or a bit-error-rate measurement at 200 MHz—is necessary to support the headline speed claim.","section":"Section 4, Fig. 5c(iii)"},{"comment":"The comparison between the custom system (200 MHz) and the COTS system (83 MHz) is confounded by differences in the amplifier chain: the COTS measurement used two external RF-Bay LNA-2500 amplifiers per output (six total), while the custom measurement used the on-board low-noise amplifier in the custom analog frontend. The paper asserts that the COTS AWG sample rate was the limiting factor, but it does not demonstrate that the different amplification paths could not also contribute to the observed maximum operating frequency. To make the speed comparison a clean demonstration of the DAQ's capability, the authors should either use the same amplifier chain in both configurations or explicitly characterize the effect of amplifier bandwidth/gain on the measured operating margin, for example by measuring the shift register error rate at matched signal levels with both systems.","section":"Section 4, Fig. 5c"}],"minor_comments":[{"comment":"The abstract quotes the COTS maximum clock rate as 80 MHz, while Section 4 and Fig. 5c state 83 MHz; please make these numbers consistent.","section":"Abstract and Section 4"},{"comment":"The phrase 'nearly three-times' (abstract) and 'nearly three-fold' (Section 4) is inaccurate for 200/83 ≈ 2.4; suggest using 'about 2.4-times' or similar.","section":"Abstract and Section 4"},{"comment":"The opening sentence contains a typo: 'data acqusition' should be 'data acquisition', and 'dataacqusitionsystem' is missing a space.","section":"Section 5"},{"comment":"The caption states that the spectra are shifted by 1 MHz in the inset for clarity, but it is not clear what is being clarified; please specify the purpose of the shift (e.g., to avoid overplotting the two traces).","section":"Figure 4b"},{"comment":"The description of the POSTCAPTURE state could be clarified with a timing diagram showing the relationship between the digital trigger, startd, and stopd signals, since the current text is somewhat abstract.","section":"Section 2.4.1"}],"recommendation":"major_revision","confidential_remarks":"The paper is a solid instrumentation contribution and the open-source release is commendable. The main risk is that the central speed claim (200 MHz vs 83 MHz) is not yet quantitatively supported, and a revision should focus on adding a pattern-based or error-rate verification at the claimed maximum frequency and on addressing the amplifier-chain confound. The abstract's 'nearly three-times' wording should also be corrected. I see no evidence of circularity; the benchmark against a passive breakout and independent noise measurements is appropriate."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Short version: the paper delivers a genuinely useful open-source DAQ for superconducting nanocryotron testing, but its headline speed claim is not yet proven.\n\nWhat's new: the firmware architecture (full-rate multi-channel time-tagging with trigger sharing, pre/post event delays, zero suppression) on an RFSoC, plus a custom analog frontend that drives high-impedance cryogenic loads. The frontend characterization is honest and solid: measured noise floor near the thermal limit, SINAD improvement of ~20 dB over a passive balun breakout, and the RFSoC board + AFE comes in at ~$16k versus $110k for the COTS setup. The code, firmware, and schematics are released under MIT license, which makes the engineering reproducible and is a real plus.\n\nWhere the soft spots are: the central claim that the shift register ran at 200 MHz instead of 83 MHz is based on visual interpretation of captured traces, not on a measured error rate. The paper itself states that at 200 MHz the fast clock edge 'results in substantial voltage pulses even when the nanocryotron does not switch,' and this 'makes it more difficult to determine when the nanocryotron actually switched.' That is exactly the kind of ambiguity that an error-counting measurement is designed to resolve, and the authors built the tool to do error counting. They haven't reported that measurement. Also, the 83 MHz comparison is from a prior paper that used a different amplifier chain (external RF-Bay LNAs vs. the custom AFE), so the comparison is not fully controlled; it's plausible the AWG was the limit, but it's asserted rather than demonstrated. And the 'nearly three-times' wording in the abstract and text is an overstatement: 200/83 is 2.4x, not nearly 3x.\n\nNone of these are fatal. The architecture and frontend work are credible, the open-source release is a substantial contribution to a subfield where custom DAQs are often black boxes, and the demonstrated ability to resolve sub-200 ps edges and run a two-loop shift register at 200 MHz is a real, useful result. The fixes are straightforward: add a quantitative error-rate or correct-switching count at 200 MHz (and at a few lower speeds for context), state the COTS comparison conditions clearly, and correct the frequency ratio.\n\nWho it's for: experimentalists testing nanocryotron or other fast superconducting devices, and people designing custom RFSoC-based test systems. It deserves a serious referee, but the referee should require the quantitative speed measurement before acceptance.","headline":"A useful, honestly-engineered open-source DAQ for nanocryotron testing, but the 200 MHz shift-register speed claim rests on visual waveform inspection rather than a quantitative error-rate measurement.","tokens_in":17006,"tokens_out":3174,"would_cite":true,"duration_ms":30404,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":["07.05.Hd"],"model":"deepseek-v4-flash","headline":"A custom RFSoC-based data acquisition system with a thermal-noise-limited analog frontend and time-tagging firmware drove a superconducting nanowire shift register at 200 MHz, nearly three times the 83 MHz reached with commercial…","keywords":["Digital electronic circuits","Digital signal processing (DSP)","Data acquisition circuits","Data acquisition concepts","Data reduction methods","RFSoC","superconducting nanocryotrons","time-tagging"],"falsifier":"Run the same two-loop shift register at 200 MHz with the RFSoC system while counting bit errors from the timetag data over many clock cycles, and repeat the 83 MHz measurement with the identical amplifier chain but swapping only the stimulus source and digitizer. If the error rate at 200 MHz is not low, or if the commercial equipment also reaches 200 MHz with the upgraded frontend, the paper's attribution of the speed limit to test equipment would be overturned.","tokens_in":15852,"feed_emoji":"⚡","tokens_out":8832,"duration_ms":84397,"temperature":0.7,"pith_summary":"The paper argues that for many novel superconducting circuits the test equipment, not the circuit, is the speed bottleneck, and that a single integrated instrument can remove it. The authors build a data acquisition system around an RFSoC with multi-gigasample-per-second converters: a custom analog frontend gives a thermal-noise-limited receive path with roughly 50 dB of dynamic range, and custom FPGA firmware saves only short, timestamped waveform snippets around threshold-crossing events. Used on a previously characterized superconducting-nanocryotron binary shift register, the system clocked the circuit at 200 MHz, compared with an 83 MHz ceiling the authors attribute to the commercial arbitrary-waveform-generator/digitizer setup, at about one-seventh the cost. If the claim holds, the contribution is a reusable, open-source way to probe the intrinsic speed limits and failure modes of nanocryotron circuits and similar stateful electronics.","feed_headline":"Custom test gear runs superconducting shift register at 200 MHz","feed_subtitle":"A time-tagging RFSoC with a 4 GS/s digitizer beats commercial gear that costs seven times more.","key_machinery":"The load-bearing element is the real-time sample discriminator implemented in FPGA firmware. It compares the digitized stream against a high (start) threshold and a low (stop) threshold with hysteresis; any sample above the high threshold begins capture and capture only ends when all samples in a processing batch fall below the low threshold. The discriminator saves a runtime-configurable number of samples before and after each event via delayed data paths and timestamps each capture with a monotonic time counter plus a sample index, so the original waveform can be reconstructed without storing every sample. Start and stop events from one channel can be routed to another through a crossbar, enabling trigger sharing, for example using a filtered version of a signal to capture the raw version. The custom analog frontend, built around a low-noise amplifier with a 3 dB noise figure, supplies the measured signal-to-noise-and-distortion floor of roughly 50 dB and lets the system operate without external amplification.","core_discovery":"The authors set out to show that integrated signal generation and real-time waveform processing can test circuits whose subcomponents have no standardized interfaces, and can do so faster than separate commercial instruments. Their system combines the RFSoC's 6 GS/s digital-to-analog converters and 4 GS/s analog-to-digital converters with custom firmware: a real-time sample discriminator performs hysteretic threshold comparison on batches of eight samples, records a timestamp and the raw voltage samples around each event, and discards the rest, so only data of interest leaves the FPGA. With this system they observed sub-200 ps output rise times and operated a two-loop superconducting nanowire binary shift register at 200 MHz, which they state was the highest frequency at which they observed it operate; the same circuit had previously topped out at 83 MHz with commercial (COTS) equipment. They conclude that the earlier ceiling was largely a sample-rate limitation of the test equipment rather than a property of the circuit, and that the data acquisition system can push circuits beyond their previously measured operating speeds.","pith_inferences":["The 200 MHz figure is based on visual interpretation of voltage traces; a quantitative bit-error-rate measurement at that clock rate would be needed to confirm the circuit truly operates there rather than producing switching-like artifacts.","The 83 MHz baseline came from a setup using a different amplifier chain (external LC amplifiers), so part of the speed gain could come from the improved analog frontend rather than the RFSoC sample rate alone; the paper asserts, rather than isolates, that the COTS AWG was the sole limit.","The time-tagging and trigger-sharing design should transfer directly to other event-sparse, high-rate measurements such as superconducting nanowire single-photon detectors, where it could enable pulse-shape-based particle identification and time-walk correction.","If the claimed speed-up is real, it follows that reported operating frequencies of many novel-device circuits may understate their intrinsic limits, and researchers should treat test-equipment ceilings as a design variable rather than a fixed constraint."],"forward_implications":["The same shift-register circuit operated at 200 MHz with the RFSoC system, showing the prior 83 MHz limit was largely imposed by the commercial test equipment's sample rate.","The time-tagging discriminator stores only events of interest, so locating errors and debugging can be done without moving tens to hundreds of gigabytes of waveforms.","At 4 GS/s the system resolves sub-200 ps rise times and reveals artifacts such as clock-edge differentiation caused by excess inductance, which are invisible to 500 MS/s capture.","The firmware, software, and analog frontend schematics are released under an open-source license, and the hardware costs about $16,000, roughly one-seventh the cost of the compared commercial configuration.","The same architecture can test multiple inputs and outputs simultaneously, which matters for stateful logic circuits whose behavior depends on combined stimuli."],"supporting_citations":[{"why":"supplies the binary shift-register circuit and its prior 83 MHz characterization with COTS equipment, the baseline for the claimed 200 MHz operation","marker":"[13]"},{"why":"introduces the nanocryotron, the three-terminal superconducting nanowire switch from which the shift register is built","marker":"[8]"},{"why":"provides the qualified-buffer concept in RFSoC firmware that the sample discriminator extends to full-rate time-domain capture","marker":"[30]"},{"why":"supplies the hysteretic threshold-comparison and timetagging scheme that the real-time discriminator adapts","marker":"[39]"},{"why":"provides the RF probe/dip-probe apparatus used to connect the dewar and circuit to the data acquisition system","marker":"[25]"},{"why":"demonstrates individual nanocryotrons switching above 600 MHz, the reference point used to argue the shift register's 200 MHz limit is a circuit-level rather than device-level ceiling","marker":"[40]"}],"fun_headline_variants":["Cheap RFSoC test rig hits 200 MHz on superconducting shift register","Inexpensive DAQ reveals true speed of superconducting circuit","Custom test gear more than doubles superconducting shift register speed","Low-cost DAQ beats commercial system that costs seven times more","RFSoC-based data acquisition outruns 7x pricier test equipment"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The central claim rests on treating the 83 MHz ceiling as a test-equipment limit and the 200 MHz operation as genuine switching, even though the switching at 200 MHz was judged from digitized waveforms and the comparison used a different amplifier chain in the commercial setup.","fun_headline_variants_meta":{"raw":{"variants":["Cheap RFSoC test rig hits 200 MHz on superconducting shift register","Inexpensive DAQ reveals true speed of superconducting circuit","Custom test gear more than doubles superconducting shift register speed","Low-cost DAQ beats commercial system that costs seven times more","RFSoC-based data acquisition outruns 7x pricier test equipment"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000603,"raw_usage":{"total_tokens":2811,"prompt_tokens":939,"completion_tokens":1872,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":555,"completion_tokens_details":{"reasoning_tokens":1780}},"tokens_in":555,"tokens_out":1872,"duration_ms":17964,"temperature":1.0,"reasoning_tokens":1780,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-07T13:24:08.781498+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Run the same two-loop shift register at 200 MHz with the RFSoC system while counting bit errors from the timetag data over many clock cycles, and repeat the 83 MHz measurement with the identical amplifier chain but swapping only the stimulus source and digitizer. If the error rate at 200 MHz is not low, or if the commercial equipment also reaches 200 MHz with the upgraded frontend, the paper's attribution of the speed limit to test equipment would be overturned.","supporting_citations":[{"cited_title":"Foster, M","cited_arxiv_id":null,"evidence_quote":"supplies the binary shift-register circuit and its prior 83 MHz characterization with COTS equipment, the baseline for the claimed 200 MHz operation"},{"cited_title":"McCaughan and K.K","cited_arxiv_id":null,"evidence_quote":"introduces the nanocryotron, the three-terminal superconducting nanowire switch from which the shift register is built"},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"provides the qualified-buffer concept in RFSoC firmware that the sample discriminator extends to full-rate time-domain capture"},{"cited_title":"Watkins,SPLENDAQ: A detector-agnostic data acquisition system for small-scale physics experiments,Journal of Low Temperature Physics214(2024) 133","cited_arxiv_id":null,"evidence_quote":"supplies the hysteretic threshold-comparison and timetagging scheme that the real-time discriminator adapts"},{"cited_title":"Butters,Digital and Microwave Superconducting Electronics and Experimental Apparatus, PhD thesis, Massachusetts Institute of Technology, 2022","cited_arxiv_id":null,"evidence_quote":"provides the RF probe/dip-probe apparatus used to connect the dewar and circuit to the data acquisition system"},{"cited_title":"Zheng, Q.-Y","cited_arxiv_id":null,"evidence_quote":"demonstrates individual nanocryotrons switching above 600 MHz, the reference point used to argue the shift register's 200 MHz limit is a circuit-level rather than device-level ceiling"}],"review_version":1}