{"id":"c1e40fce-79b0-41be-8de0-cd63a95fa799","arxiv_id":"2506.14138","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":5.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":0,"one_line_summary":"An FPGA-based spiking neural network emulator with all-to-all connectivity and on-chip STDP learning is presented and tested on digit classification and a citation-graph task.","lead":"NeuroCoreX is an open-source FPGA emulator for spiking neural networks: up to 100 neurons, all-to-all connections, and on-chip spike-timing-dependent plasticity. It reports matching 68% accuracy on handwritten digit classification and targets low-power edge computing and teaching.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Same aggregate 68% accuracy on one inference task cannot certify faithful dynamics; per-sample output comparison is needed, and the MicroSeer STDP divergence already shows the learning path is unvalidated.","rationale":"The reader's weakest assumption is exactly the load-bearing point: aggregate accuracy on one inference task is insufficient to certify functional equivalence between the FPGA and the simulator. This is not an external dispute about consensus; it is an internal evidence gap. Section III.B draws a strong conclusion ('faithfully reproduces the dynamics') from a single coarse number, and Section III.C shows that the same equivalence does not hold in the STDP-enabled regime, which is the platform's headline feature. A per-sample comparison of outputs would settle whether the inference path is truly equivalent. I see no reason to move the reader's CONDITIONAL verdict: the concern is material and fixable, but the paper is not acceptable as-is. The missing code and omitted close-prior-work comparison noted by the reader are secondary but reinforce the conditionality. My recommendation is UNCHANGED because the conditional verdict already captures this concern, and the proposed test would determine whether the condition can be lifted.","tokens_in":11359,"tokens_out":4121,"duration_ms":44526,"concrete_test":"Re-run the DIGITS test set on both SuperNeuroMAT and NeuroCoreX with identical trained weights and identical input spike streams, and compare per-sample output labels plus spike rasters for all output neurons, not just aggregate accuracy. If per-sample outputs and spike times match exactly, the faithfulness claim in III.B is supported; if they differ, the 68% equality is a coarse coincidence and the central claim must be weakened or re-evidenced. A secondary fixed-point reference run with STDP enabled would settle whether the learning path is correct, but the per-sample inference comparison is the minimal decisive check.","verdict_should_be":"UNCHANGED","load_bearing_attack":"Section III.B's equivalence claim rests on one statistic: 68% test accuracy on DIGITS observed both in SuperNeuroMAT and on NeuroCoreX. That is too coarse to establish that the FPGA 'faithfully reproduces the dynamics' of the simulated SNN. Identical aggregate accuracy can occur with different per-sample predictions, shifted spike times, or systematically different membrane-potential trajectories, especially because 68% is far from ceiling and may be dominated by input statistics rather than by exact fixed-point arithmetic. The paper does not report per-sample agreement, spike-timing differences, or membrane-potential comparisons for the DIGITS test set. The scope problem is compounded by Section III.C: with STDP enabled, weight evolution on the FPGA diverges from the simulator, attributed to the rectangular versus exponential learning rule and 8-bit fixed-point weights. Thus the only quantitative validation covers inference with learning disabled, while the title/abstract's central feature, on-chip learning, is explicitly not shown to match simulation or to be correct in any validated sense. The claimed functional equivalence is therefore underdetermined by the evidence presented.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The manuscript presents NeuroCoreX, an FPGA-based spiking neural network emulator implemented in VHDL, featuring LIF neurons, current-based exponential synapses, all-to-all connectivity for up to 100 neurons, and a pair-based STDP learning rule with a rectangular window. The system is programmed through a UART interface controlled by a Python module. Validation experiments are reported on the DIGITS dataset, where a 68% test accuracy is claimed both in the SuperNeuroMAT simulator and on the NeuroCoreX hardware with STDP disabled, and on the MicroSeer citation-graph dataset, where inference with STDP disabled is said to match the simulator but STDP-enabled weight evolution diverges from it. The paper argues that the DIGITS result establishes that the FPGA faithfully reproduces the simulated SNN dynamics and that the platform enables on-chip, online learning.","tokens_in":11537,"tokens_out":3748,"duration_ms":42001,"significance":"If the central claims were fully substantiated, NeuroCoreX would be a useful open-source contribution: it targets a low-cost FPGA, offers flexible all-to-all connectivity, provides real-time observability through spike-raster and membrane-potential read-back, and incorporates on-chip STDP. The authors deserve credit for openly reporting the MicroSeer STDP divergence and for providing a concrete power estimate. However, the current evidence underdetermines the main validation claim: the only quantitative inference comparison is a single aggregate accuracy number with learning disabled, and the on-chip learning feature is not validated against any reference. The contribution is promising, but the verification needs to be substantially strengthened before the paper's conclusions are supported.","major_comments":[{"comment":"The statement that the authors achieved a 68% test accuracy on the SuperNeuroMAT simulator and observed the same accuracy on NeuroCoreX hardware is the only quantitative evidence for the central claim that the FPGA 'faithfully reproduces the dynamics of the simulated SNN.' A single aggregate accuracy cannot certify functional equivalence: identical accuracy can be accompanied by different per-sample predictions, shifted spike times, or systematically different membrane-potential trajectories, especially at 68% accuracy where the metric is far from ceiling and may be dominated by input statistics rather than exact fixed-point arithmetic. The paper should report per-sample label agreement (or a confusion matrix), spike-timing comparison for the test set, and representative membrane-potential traces from both the simulator and the hardware, along with repeated runs to quantify variability.","section":"III.B"},{"comment":"On-chip STDP learning is a headline feature of the abstract and title, yet the only experiment involving learning explicitly reports divergence between hardware and simulation. The MicroSeer evaluation gives no classification accuracy, no quantitative weight-evolution comparison, and no description of what parameter tuning was attempted. As written, the paper demonstrates that weights change on the FPGA, but not that learning is correct or that the learned network solves the graph task. This is a load-bearing gap for the 'on-chip learning' claim and must be addressed with quantitative results, for example a weight-trajectory comparison and task accuracy for both simulator and hardware after tuning.","section":"III.C and abstract"},{"comment":"The model equations, as written, are incomplete and ambiguous. The membrane-potential update V(t+1)=V(t)-lambda+Isyn(t) does not show how incoming spikes contribute to Isyn, and the synaptic-current update Isyn(t+1)=Isyn(t)-lambda_syn shows only decay. The reset, refractory period, and threshold behavior are described only in prose. Because the paper's validation rests on the equivalence between the hardware and the simulator, the exact discrete-time update rules used by both sides must be stated unambiguously, including fixed-point scaling and overflow handling.","section":"II.C"}],"minor_comments":[{"comment":"There is an unresolved placeholder reference to 'EONs []'; either complete the citation or remove the pointer.","section":"II.A"},{"comment":"The matrix notation is inconsistent: the paper mostly uses WAA and Win, but Section II.E introduces WF F; please use a single set of names throughout.","section":"II.E"},{"comment":"The paper repeatedly states that NeuroCoreX is released as open-source, but no repository URL, license, or version identifier is provided; please add the public repository link.","section":"I and IV"},{"comment":"The sentence after the 68% accuracy result claims that the result 'confirms that the FPGA implementation faithfully reproduces the dynamics of the simulated SNN'; this claim exceeds what a single aggregate accuracy can support and should be tempered until per-sample evidence is provided.","section":"III.B"},{"comment":"Please correct minor typographical issues, including 'upto N = 100' and the missing spaces in 'pre-and postsynaptic'; a full proofread would be useful.","section":"II.C and II.E"},{"comment":"The 305 mW power estimate is reported without methodological detail; if it is based on a vendor power-analysis tool, please state that and give the operating conditions used.","section":"III.C"}],"recommendation":"major_revision","confidential_remarks":"The manuscript is within scope for a neuromorphic computing or FPGA-systems venue, and the open-source release is a genuine plus. I am not recommending rejection because the platform appears to be functional and the authors candidly report the STDP divergence. However, the central validation claim is currently supported by too little evidence: one aggregate accuracy number for inference and no quantitative validation of learning. If the authors add per-sample agreement, spike-level comparisons, repeated runs, and a proper learning experiment, the paper could become acceptable."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Colleague — quick take. NeuroCoreX is a real, clearly described open FPGA SNN emulator: VHDL, time-multiplexed LIF, all-to-all 100-neuron connectivity, rectangular STDP, Python/UART control. The DIGITS result shows the inference pipeline works — same 68% test accuracy on hardware as in their SuperNeuroMAT simulator, with read-back membrane traces and raster plots that make the basic operation credible. The scalability discussion is honest about the 500-neuron memory-bandwidth bound. That core engineering is the value here.\n\nThe soft spots are in proportion. First, 'faithfully reproduces the dynamics' is overclaimed from one aggregate accuracy number. Identical 68% can hide different per-sample predictions, shifted spike times, or different subthreshold trajectories. They don't report per-sample agreement, spike-timing error, or membrane-potential comparison for the DIGITS test set. That is a fixable but real gap. Second, on-chip STDP — the headline feature — is not validated. The MicroSeer experiment explicitly diverges from simulation, blamed on rectangular vs exponential STDP and 8-bit fixed point. Tuning parameters might align them, but currently there is no demonstration that the learning rule does anything correct. Third, the paper says 'open-source' but no repository link appears; for an open-source claim that needs to be in the manuscript. Finally, their own prior all-to-all FPGA processor (ref [23], Maheshwari et al.) is omitted from related-work comparison. That is a citation gap they should fix.\n\nNone of this sinks the platform; the central inference claim holds up in a modest sense. The paper is for neuromorphic-hardware people who want a low-cost, hackable testbed for SNN inference and maybe learning experiments. It deserves a serious referee and likely major revision, not desk rejection. If they add per-sample validation, an STDP learning result that does something demonstrably sensible, a code link, and the missing comparison, I'd be happy to see it in print.","headline":"Useful open FPGA SNN testbed with honest write-up, but the 'faithful dynamics' claim rests on a single aggregate accuracy number and the on-chip learning path is unvalidated.","tokens_in":12074,"tokens_out":1510,"would_cite":true,"duration_ms":14864,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"NeuroCoreX claims its FPGA emulator faithfully reproduces a trained spiking neural network's dynamics, matching the simulator's 68% test accuracy on the DIGITS handwritten-digit task.","keywords":["spiking neural networks","FPGA","neuromorphic hardware","STDP","on-chip learning","LIF neuron","DIGITS dataset","time multiplexing"],"falsifier":"Run a broader battery of comparisons between SuperNeuroMAT and NeuroCoreX on the same trained network, comparing per-neuron spike rasters, membrane potential traces, and final weight matrices across many trials; if spike trains or per-neuron dynamics differ substantially even when accuracies coincide, the claim of faithful reproduction is falsified, while exact raster-level agreement would confirm it.","tokens_in":11168,"feed_emoji":"⚡","tokens_out":4010,"duration_ms":38713,"temperature":0.7,"pith_summary":"The paper introduces NeuroCoreX, an open-source FPGA-based spiking neural network emulator that can run trained networks in real time and adapt them on-chip using spike-timing-dependent plasticity. Its central validation claim is that the hardware reproduces the behavior of a software simulation: a two-layer spiking network trained on the DIGITS dataset reaches 68% test accuracy both in the SuperNeuroMAT simulator and on the FPGA, with on-chip learning switched off. The authors present this match as evidence that the FPGA's fixed-point neuron and synapse computations faithfully implement the simulator's floating-point dynamics. A second experiment on a citation-graph dataset shows that when STDP learning is enabled, weight evolution on the FPGA diverges from the simulator, which the paper attributes to differences in learning rule and numerical precision and presents as motivation for algorithm–hardware co-design. The wider aim is to give researchers and students an affordable, reconfigurable platform for testing spiking networks and learning rules under real hardware constraints.","feed_headline":"FPGA chip matches simulator's 68% accuracy on spiking digits","feed_subtitle":"Open-source NeuroCoreX runs trained spiking networks on cheap hardware and adds on-chip learning via STDP.","key_machinery":"The load-bearing mechanism is a time-multiplexed digital neuron core paired with block-RAM-stored weight and trace matrices. One physical Leaky Integrate-and-Fire neuron circuit emulates up to 100 virtual neurons by updating each in turn under a 100 kHz clock, while a 100 MHz clock services the memory reads and writes needed for the all-to-all weight matrix, the feedforward input weight matrix, and the STDP trace registers. The STDP variant uses a rectangular learning window with signed 8-bit weights and tracks pre- and post-synaptic spike times in dedicated trace matrices, with a binary enable-STDP mask restricting which synapses are plastic. This combination is what allows the platform to claim both faithful reproduction of simulator dynamics and on-chip learning on a low-cost Artix-7 FPGA.","core_discovery":"On its own terms, the paper's central discovery is that a single time-multiplexed digital neuron circuit, using fixed-point arithmetic with 1 sign bit, 7 integer bits, and 10 fractional bits, can emulate a 100-neuron all-to-all spiking network closely enough that a benchmark accuracy is preserved exactly: 68% on the DIGITS test set, identical to the simulator. The authors use this equality to assert that the FPGA implementation faithfully reproduces the dynamics of the simulated SNN, validating spike integration, thresholding, and synaptic current accumulation in hardware.","pith_inferences":["A single aggregate accuracy match (68%) is a weak certificate of dynamical equivalence; the paper's own STDP experiment shows that learning trajectories can diverge, so per-neuron, per-timestep comparisons would be a stronger test of the fidelity claim. ","The observed divergence between the simulator's exponential 64-bit STDP and the hardware's rectangular 8-bit STDP suggests that simulated learning rules should be adapted to hardware precision before deployment, rather than ported unchanged. ","Because NeuroCoreX can read back membrane potentials and synaptic weights, a natural extension is to replay identical spike trains on simulator and FPGA and compare full spike rasters; exact raster-level agreement would certify equivalence far more convincingly than a single accuracy number. ","The all-to-all weight matrix, though memory-intensive, makes the platform a convenient testbed for graph-structured spiking networks, and the paper's hybrid scaling idea implies that larger networks could be tiled across multiple FPGA instances. "],"forward_implications":["A network trained in software simulation can be ported to NeuroCoreX without retraining and can reproduce the same test accuracy on a standard benchmark. ","Because connectivity is all-to-all and reconfigurable, the platform can implement non-layered topologies such as small-world and graph-structured networks, not just feedforward layers. ","On-chip STDP enables synaptic weights to evolve in real time during inference, supporting online adaptation for edge, robotics, and embedded applications. ","The time-multiplexed architecture sets a concrete scalability bound: about 100 neurons on the current Artix-7 board, with a theoretical ceiling near 500 neurons given the clock and memory-bandwidth constraints described in the paper. ","When STDP is enabled, hardware learning diverges from the simulator, so the paper argues that learning parameters must be tuned separately in each environment for comparable accuracy. "],"supporting_citations":[{"why":"Supplies the DIGITS handwritten-digit dataset used as the benchmark for the hardware–simulator accuracy comparison.","marker":"[2]"},{"why":"SuperNeuroMAT simulator provides the trained network, the floating-point reference dynamics, and the 68% baseline accuracy that NeuroCoreX is claimed to match.","marker":"[8]"},{"why":"Defines the Leaky Integrate-and-Fire neuron and current-based synapse model that NeuroCoreX implements in digital logic.","marker":"[19]"},{"why":"Original biological STDP rule that the simplified rectangular-window on-chip learning rule is designed to approximate.","marker":"[24]"},{"why":"Supports the paper's assertion that a rectangular STDP window can preserve functional behavior when synaptic weights have more than 6-bit resolution.","marker":"[5]"},{"why":"CiteseerX is the source graph from which the MicroSeer dataset is derived, used in the STDP-enabled graph-learning experiment.","marker":"[4]"}],"fun_headline_variants":["Open-source FPGA SNN hits simulator accuracy with on-chip STDP","FPGA emulator trains spiking nets on-chip, matches simulator","Open-source NeuroCoreX: FPGA spiking nets with STDP learning","Chip learns spiking patterns, equals sim at 68% on digits","FPGA spiking emulator: on-chip learning, same accuracy as sim"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The conclusion that the hardware faithfully reproduces the simulated spiking network rests on a single match: the same 68% test accuracy on DIGITS with learning disabled; if aggregate accuracy can match while internal dynamics diverge, the correctness claim loses its evidence.","fun_headline_variants_meta":{"raw":{"variants":["Open-source FPGA SNN hits simulator accuracy with on-chip STDP","FPGA emulator trains spiking nets on-chip, matches simulator","Open-source NeuroCoreX: FPGA spiking nets with STDP learning","Chip learns spiking patterns, equals sim at 68% on digits","FPGA spiking emulator: on-chip learning, same accuracy as sim"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.00027,"raw_usage":{"total_tokens":1608,"prompt_tokens":912,"completion_tokens":696,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":528,"completion_tokens_details":{"reasoning_tokens":600}},"tokens_in":528,"tokens_out":696,"duration_ms":5983,"temperature":1.0,"reasoning_tokens":600,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-15T19:53:57.698207+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Run a broader battery of comparisons between SuperNeuroMAT and NeuroCoreX on the same trained network, comparing per-neuron spike rasters, membrane potential traces, and final weight matrices across many trials; if spike trains or per-neuron dynamics differ substantially even when accuracies coincide, the claim of faithful reproduction is falsified, while exact raster-level agreement would confirm it.","supporting_citations":[{"cited_title":"Kulkarni, Robert Patton, Mark Coletti, and Thomas Potok","cited_arxiv_id":null,"evidence_quote":"SuperNeuroMAT simulator provides the trained network, the floating-point reference dynamics, and the 68% baseline accuracy that NeuroCoreX is claimed to match."},{"cited_title":"Time structure of the activity in neural network models","cited_arxiv_id":null,"evidence_quote":"Defines the Leaky Integrate-and-Fire neuron and current-based synapse model that NeuroCoreX implements in digital logic."},{"cited_title":"Regulation of synaptic efficacy by coincidence of postsynaptic aps and epsps","cited_arxiv_id":null,"evidence_quote":"Original biological STDP rule that the simplified rectangular-window on-chip learning rule is designed to approximate."},{"cited_title":"A combi- national digital logic approach to stdp","cited_arxiv_id":null,"evidence_quote":"Supports the paper's assertion that a rectangular STDP window can preserve functional behavior when synaptic weights have more than 6-bit resolution."},{"cited_title":"Citeseer x: A scholarly big dataset","cited_arxiv_id":null,"evidence_quote":"CiteseerX is the source graph from which the MicroSeer dataset is derived, used in the STDP-enabled graph-learning experiment."}],"review_version":1}