{"id":"44553e27-724b-4167-8f15-a835604c4bc0","arxiv_id":"2507.22907","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":0,"one_line_summary":"A clock-pulling phase-locked-loop feedback scheme stabilizes the previously unstable maximum-efficiency state of a nonlinear PT-symmetric wireless power transfer system.","lead":"This paper shows that adding a phase-locked-loop clock to a nonlinear wireless power transfer circuit lets it lock onto a steady state that was previously considered unstable but gives the highest transfer efficiency. The scheme is demonstrated in a prototype, potentially improving efficiency in real wireless charging systems.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Eq. (4)'s sign for Im(gss,c) contradicts Eq. (2); the printed polarity would destabilize the very state the clock-pulling design claims to stabilize.","rationale":"The reader's weakest assumption is exactly the most load-bearing concern. The central claim is that clock pulling stabilizes the otherwise unstable maximum-efficiency state eω0, and the mechanism's feasibility rests entirely on the frequency-phase polarity of the complex gain. Eq. (4) is the only derivation of that polarity, and it is algebraically inconsistent with Eq. (2): the sign of Im(gss,c) is reversed. A reversed sign turns the proposed negative feedback into positive feedback, so the printed theory predicts the opposite of the observed stabilization. This is an internal inconsistency, not merely a disagreement with consensus. The paper does report a direct experimental stabilization of eω0, with measured frequency and efficiency matching the coupled-mode model over the reported coupling range, which is independent evidence that the mechanism can work in practice. However, that empirical success does not fix the written derivation. The appropriate verdict is therefore CONDITIONAL, not REJECT: the authors should correct Eq. (4) (likely changing '+' to '−' inside the bracket) and confirm that Fig. 2(d) uses the corrected polarity. If the corrected sign also yields the argued stability, the claim may be accepted; if the printed sign is intended, the theoretical explanation fails and the claim needs substantial revision.","tokens_in":8059,"tokens_out":14210,"duration_ms":147552,"concrete_test":"Independently solve Eq. (2) symbolically for gss,c as a function of real ω (e.g., using SymPy) for χc=χl=1, and compare Im(gss,c) with Eq. (4) at δ=±0.01 with k=0.3, γ=0.0565. If the derived expression contains 1−k²/(γ²+4δ²), Eq. (4) has a sign typo; then recompute the curves in Fig. 2(b,d) with the corrected sign and check that the red arrows indeed point toward ω0. If the derived expression reproduces the printed plus sign, the polarity design is unsupported and the paper's central claim lacks a theoretical basis.","verdict_should_be":"UNCHANGED","load_bearing_attack":"Solving Eq. (2) for complex gss,c with χc=χl=1 and real ω gives Im(gss,c)=2(ω−1)[1−k²/(γ²+4(ω−1)²)]. The printed Eq. (4) has 1+k²/(γ²+4(ω−1)²) in the same bracket. These differ in sign for k>γ, i.e. exactly in the PT-symmetric phase where the stabilization claim is made. For the experimental parameters (k=0.3, γ=0.0565) and small δ=ω−1, the correct sign gives Im(gss,c)≈−0.48δ, whereas Eq. (4) gives ≈+0.52δ. The whole clock-pulling polarity argument in Fig. 2(d) requires the negative sign: a positive frequency error must produce a phase error that makes the PLL reduce the frequency. With the printed plus sign, the feedback is positive and would destabilize ω0 rather than stabilize it. Hence the written theory contradicts its own stabilization mechanism. This is an internal inconsistency in the central derivation, not a matter of disagreement with the community. The empirical demonstration in Fig. 3 is credible and supports the phenomenon, but it cannot repair the incorrect equation as published.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The manuscript proposes a 'clock-pulling' feedback mechanism, realized by a phase-locked loop, to stabilize the conventionally unstable symmetric mode ω̃₀ = 1 of a nonlinear parity-time-symmetric two-coil wireless power transfer system. The authors derive a coupled-mode-theory dispersion relation for the complex steady-state gain, argue that the frequency-dependent phase response of this gain permits a feedback polarity that makes the maximum-efficiency mode robustly stable, and support the idea with an FPGA-based PLL prototype operating at 85 kHz. Measured frequency and efficiency data are compared with the CMT predictions over a range of coupling coefficients. The central claim is that this clock-pulling scheme forcibly breaks the PT symmetry and enables operation at the theoretical maximum transfer efficiency without active tuning.","tokens_in":8332,"tokens_out":12702,"duration_ms":136672,"significance":"If correct, the paper would offer a control-theoretic route to operate a two-coil WPT system at the maximum-efficiency mode while retaining frequency robustness, and it would generalize the clock-pulling concept to other nonlinear non-Hermitian platforms. The experimental comparison is a genuine strength: Fig. 3 reports measured frequency and efficiency versus coupling coefficient for both the clock-pulling scheme and a conventional PT-symmetric system, with the model curves evidently not fitted to the data. The proposed mechanism is falsifiable and the central claim is clearly stated. However, the written algebraic derivation of the key dispersion relation contains a sign error that, as printed, reverses the feedback polarity and would destabilize the very state the design aims to stabilize. That issue must be resolved before the theoretical mechanism can be considered established.","major_comments":[{"comment":"Equation (4) is algebraically inconsistent with Eq. (2) in the sign of the k² term in the imaginary part. Setting χ_c = χ_l = 1 and solving Eq. (2) for complex g_ss,c as a function of real ω̃ gives Im(g_ss,c) = 2(ω̃−1)[1 − k²/(γ² + 4(ω̃−1)²)], whereas Eq. (4) as printed has the same bracket with a plus sign. In the PT-symmetric phase k > γ, the correct sign is negative near ω̃ = 1, and the printed plus sign gives the opposite dispersion. Since the clock-pulling polarity argument in Fig. 2(d) relies on the sign of Im(g_ss,c) to determine whether a frequency error produces a stabilizing or destabilizing PLL response, the derivation as written does not support the claimed stabilization of ω̃₀. The authors should correct Eq. (4), re-plot the phase-dispersion curves in Fig. 2(b), and confirm that the polarity analysis still predicts stabilization of ω̃₀.","section":"Eq. (4) and Fig. 2(b)-(d)"},{"comment":"The narrative around Fig. 2(b) states that the left neighborhood of ω̃₀ exhibits negative phase angles and the right neighborhood positive angles. With the corrected sign derived from Eq. (2), the opposite holds for k > γ: left of ω̃₀ (δ < 0) gives positive Im(g_ss,c) and right (δ > 0) gives negative Im(g_ss,c). The text therefore describes the polarity that follows from the erroneous plus sign in Eq. (4), not from the stated model. The stabilization arrows in Fig. 2(d) must be re-derived from the corrected phase-frequency relation; as printed, they implement positive feedback and would destabilize the maximum-efficiency state.","section":"Fig. 2(b)-(d) and Sec. II"},{"comment":"The stability analysis is presented only as a heuristic red-arrow argument in Fig. 2(d) with no linearized small-signal stability calculation for the combined PLL/resonator dynamics. The claim that the clock-pulling scheme makes ω̃₀ 'uniquely robust stable' is load-bearing but is not supported by a Lyapunov or perturbation analysis. Given the sign error in Eq. (4), a proper linearized treatment is necessary to establish the claimed polarity and to define the conditions under which the continuous-time PLL loop actually converges to ω̃₀ rather than to ω̃₁ or ω̃₂.","section":"Sec. II, Fig. 2(d)"}],"minor_comments":[{"comment":"The grammar 'nonlinear parity-time (PT) symmetry ... have posed' should be 'has posed', and the term 'parity-time symmetric WPT system' is used before the abbreviation PT is fully established in the same sentence; please polish the opening paragraph.","section":"Abstract and Introduction"},{"comment":"The caption contains a typo ('steady-state requried gain') and the axis label 'Log(gss)' should be 'Log(|g_ss,c|)' for clarity.","section":"Fig. 1(d) caption"},{"comment":"The bracket structure of Eq. (4) is ambiguous in the typeset equation; the imaginary part should be written with explicit parentheses so that the reader can immediately see the term 2χ_c²ω̃ − 2χ_c⁴χ_l² and the k² term are both inside the imaginary bracket.","section":"Eq. (4)"},{"comment":"Reference [19] is given as 'See Supplement Material at url' with a placeholder 'url'; the actual supplementary link and document identifier should be provided before publication.","section":"Reference [19]"},{"comment":"The measured data in Fig. 3(c) and (d) are presented without error bars or a statement of measurement uncertainty or number of repeated trials; adding this information would strengthen the claimed agreement with the CMT calculation.","section":"Fig. 3(c)-(d)"},{"comment":"The description of the two PLL fixed-point types is confusing: for ϕ = (2n+1)π the text says the output is 'in phase' with the reference, which is unconventional for a sinusoidal phase detector; please clarify the sign convention and the relation to z_f.","section":"Fig. 2(a) description"}],"recommendation":"major_revision","confidential_remarks":"The sign inconsistency in Eq. (4) sits at the heart of the feedback-polarity argument, so the paper cannot be accepted in its present form. The error appears fixable: the correct expression follows directly from Eq. (2), and the experimental demonstration may still be valid. I would encourage the authors to recompute the dispersion, revise Fig. 2(b) and (d) accordingly, and add a small-signal stability analysis of the combined PLL-resonator loop. The manuscript's scope and the experimental comparison are otherwise suitable for this journal."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Jackie,\n\nQuick take: this is a paper worth reading and worth refereeing, but as written it has a load-bearing typo. The experimental part is genuinely new: the authors show that a PLL-based clock-pulling loop can stabilize the 'unstable' e0 mode—the one with maximum transfer efficiency—in a two-coil PT-symmetric WPT system. Measured frequencies and efficiencies track the coupled-mode model nicely over the coupling range, and the idea of using a classical clock to enforce continuous frequency variation so feedback can pull the system to a normally unstable steady state is clever, with clear reach beyond WPT.\n\nThe soft spot is real. Equation (4), which is the theoretical basis for the entire polarity design, does not follow from Eq. (2). For the PT case (χc=χl=1), solving Eq. (2) for the required complex gain gives Im(gss,c) = 2δ[1 − k²/(γ²+4δ²)]. The printed Eq. (4) has a plus sign in the bracket. That is not cosmetic: the whole stability argument in Fig. 2(d) relies on the Im(gss,c) slope being negative near e0 for k>γ, so that a positive frequency error produces a phase error that makes the PLL pull the frequency down. With the printed plus sign, the feedback would be positive and would destabilize e0 instead of stabilizing it. This looks like a missing minus sign in the second term of the imaginary part, but it is a central equation and the paper cannot stand as is.\n\nTwo smaller points. There is no closed-loop stability analysis; the stability is inferred from the dispersion sign plus an intuitive PLL picture. That is acceptable for a first demonstration, but a small-signal loop model would make the claim solid. And the measured waveforms show noticeable harmonic distortion; the authors acknowledge it and argue it doesn't affect the fundamental, which is fine.\n\nIf the authors fix the sign in Eq. (4) and confirm the plotted dispersion uses the corrected formula, this is a solid paper. The experimental result is the strongest evidence and would likely survive correction. I'd send it to peer review with a request for that fix, and ideally a short closed-loop stability argument.\n\nBest,","headline":"Clever experiment stabilizes the max-efficiency mode in PT-symmetric WPT, but a sign error in Eq. (4) contradicts the paper's own stability argument and must be fixed before publication.","tokens_in":8830,"tokens_out":12638,"would_cite":true,"duration_ms":126116,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"The paper claims a clock-pulling feedback loop can stabilize the maximum-efficiency state of nonlinear parity-time-symmetric wireless power transfer, and demonstrates it experimentally.","keywords":["wireless power transfer","parity-time symmetry","non-Hermitian systems","clock pulling","phase-locked loop","nonlinear gain","transfer efficiency","multistability"],"falsifier":"Measure the phase-frequency response of the clock-pulling gain module around $\\tilde{\\omega}_0 = 1$ and check whether its slope matches the polarity assumed in Fig. 2(d); then flip the phase-detector operating point from $\\pi$ to $0$ and see whether the stable mode switches from $\\tilde{\\omega}_0$ to $\\tilde{\\omega}_{1,2}$. If reversing the pulling polarity has no effect on which steady state is reached, the clock-pulling mechanism is not what stabilizes the maximum-efficiency mode.","tokens_in":7886,"feed_emoji":"⚡","tokens_out":7454,"duration_ms":76097,"temperature":0.7,"pith_summary":"The paper aims to show that a nonlinear feedback mechanism it calls clock pulling can force a parity-time (PT) symmetric two-coil wireless power transfer system to settle on its conventionally unstable steady state, the one with maximum transfer efficiency. PT symmetry here means the transmitter gain and receiver loss are balanced, so the system has two symmetric modes $\\tilde{\\omega}_{1,2}$ and a high-gain mode $\\tilde{\\omega}_0 = 1$. The paper argues that stability in these nonlinear non-Hermitian systems is not permanently fixed by the principle of minimal gain, but can be reconfigured through the frequency-dependent phase of the required complex gain. If the claim is right, a wireless power link can run at its theoretical efficiency limit over a range of coil couplings without active retuning, and the same feedback principle could apply to other nonlinear non-Hermitian platforms.","feed_headline":"Clock pulling pins wireless power at maximum efficiency","feed_subtitle":"A phase-locked feedback loop locks the system onto the one state that maximizes efficiency, beating parity-time-symmetric designs.","key_machinery":"The mechanism is clock pulling: a phase-locked loop whose voltage-controlled oscillator provides a classical clock and forces continuous frequency variation, so feedback can act on the frequency-dependent phase of the steady-state required gain instead of being defeated by rapid transient frequency jumps. The load-bearing identity is the complex steady-state gain formula $g_{ss,c}$ (Eq. (4)); for the PT case its imaginary part changes sign across the mode $\\tilde{\\omega}_0 = 1$, giving the PLL a pulling polarity that increases frequency on one side and decreases it on the other. That polarity is what stabilizes the previously unstable maximum-efficiency state and destabilizes the symmetric modes.","core_discovery":"The central discovery is that the steady-state selection of a nonlinear PT-symmetric WPT dimer can be switched by a clock-pulling feedback loop. Examining the dispersion of the required gain, the authors find that the mode $\\tilde{\\omega}_0 = 1$, which conventionally is dismissed as unstable because it requires the highest gain, sits at an extremum of the complex required gain $g_{ss,c}$; its imaginary part has opposite polarity in the adjacent frequency bands. A phase-locked loop whose voltage-controlled oscillator provides a classical clock enforces continuous frequency variation, and near its $\\phi_{\\mathrm{PLL}} = \\pi$ equilibrium the loop adjusts frequency with the correct polarity to pull the system to $\\tilde{\\omega}_0$ and hold it there, while making the symmetric modes $\\tilde{\\omega}_{1,2}$ unstable. The paper reports an 85 kHz two-coil prototype in which the system operates stably at $\\tilde{\\omega}_0$ with the theoretically maximum transfer efficiency in the strong-coupling region, consistent with coupled-mode calculations.","pith_inferences":["Beyond the paper, the same design logic should generalize to any nonlinear non-Hermitian oscillator whose required gain has an extremum at a target mode: clock pulling turns a frequency-domain extremum into a stable attractor, so other 'maximum-gain' modes could be stabilized without changing the physical nonlinearity.","A testable extension is to sweep load resistance and coupling while recording efficiency: the clock-pulled state should track the theoretical maximum-efficiency curve up to the PT-broken boundary and then lose stability, giving a sharp quantitative prediction of the operating envelope.","The engineering limit implied by the mechanism is feedback speed: if the loop bandwidth is too low to follow the rapid transient frequency shifts reported in earlier PT-circuit experiments, the stabilizing action will fail, so measuring loop bandwidth against frequency-switch transients would set the practical range."],"forward_implications":["If the paper is right, two-coil wireless power transfer can operate at the theoretical maximum transfer efficiency over a range of coupling coefficients without active tuning, outperforming conventional PT-symmetric designs in the strong-coupling region.","The same clock-pulling principle should stabilize the corresponding zero-point mode in asymmetric non-Hermitian systems where $\\chi_l \\chi_c \\neq 1$, since the phase-frequency response of the required gain remains similar.","The stability assignment reverses in the PT-broken region: the clock-pulling configuration that stabilizes $\\tilde{\\omega}_0$ is unstable there, so the method is confined to the strong-coupling regime.","Because the feedback reconfigures stability dynamically rather than changing the dispersion landscape, the mechanism should transfer to other nonlinear non-Hermitian platforms such as waveguide resonators, acoustic cavities, and optoelectronic oscillators."],"supporting_citations":[{"why":"Provides the nonlinear PT-symmetric WPT baseline in which the high-gain mode is conventionally unstable; the paper's claim is precisely that clock pulling makes this mode stable.","marker":"[3]"},{"why":"Supplies the switch-mode implementation of the nonlinear PT-symmetric circuit that the clock-pulling design builds on.","marker":"[16]"},{"why":"Gives the nonlinear PT-symmetric model for constant-efficiency WPT, another baseline whose behavior the paper extends.","marker":"[17]"},{"why":"Establishes dispersive gain as a steady-state selection tool for asymmetric non-Hermitian WPT, the conceptual predecessor of the frequency-dependent gain analysis here.","marker":"[18]"},{"why":"Is the coupled-mode theory used to write the dimer Hamiltonian and derive the characteristic equation for steady states.","marker":"[20]"},{"why":"Documents the rapid and discontinuous transient frequency shifts in PT-symmetric active circuits that motivate the need for a classical clock in the feedback loop.","marker":"[21]"},{"why":"Is the phaselock-techniques reference that the clock-pulling PLL implementation is based on.","marker":"[24]"},{"why":"Carries the modeling details, stability analysis, and experimental setup parameters that support the reported measurements.","marker":"[19]"}],"fun_headline_variants":["Clock-pulling locks wireless power at peak efficiency","Feedback clock steers wireless power to max efficiency","Clock trick forces wireless power into top gear","Pulling the clock brings wireless power to max","Clock-pull feedback hits wireless power's sweet spot"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The design rests on the sign of the frequency-dependent complex gain in Eq. (4), which sets the pulling polarity: if the imaginary part of the required gain does not change sign across $\\tilde{\\omega}_0 = 1$ in the way the paper's arrows show, the feedback would push the system away from the maximum-efficiency state instead of toward it.","fun_headline_variants_meta":{"raw":{"variants":["Clock-pulling locks wireless power at peak efficiency","Feedback clock steers wireless power to max efficiency","Clock trick forces wireless power into top gear","Pulling the clock brings wireless power to max","Clock-pull feedback hits wireless power's sweet spot"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000184,"raw_usage":{"total_tokens":1280,"prompt_tokens":871,"completion_tokens":409,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":487,"completion_tokens_details":{"reasoning_tokens":338}},"tokens_in":487,"tokens_out":409,"duration_ms":5238,"temperature":1.0,"reasoning_tokens":338,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-06T17:14:39.137670+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Measure the phase-frequency response of the clock-pulling gain module around $\\tilde{\\omega}_0 = 1$ and check whether its slope matches the polarity assumed in Fig. 2(d); then flip the phase-detector operating point from $\\pi$ to $0$ and see whether the stable mode switches from $\\tilde{\\omega}_0$ to $\\tilde{\\omega}_{1,2}$. If reversing the pulling polarity has no effect on which steady state is reached, the clock-pulling mechanism is not what stabilizes the maximum-efficiency mode.","supporting_citations":[{"cited_title":"Assawaworrarit, X","cited_arxiv_id":null,"evidence_quote":"Provides the nonlinear PT-symmetric WPT baseline in which the high-gain mode is conventionally unstable; the paper's claim is precisely that clock pulling makes this mode stable."},{"cited_title":"Assawaworrarit and S","cited_arxiv_id":null,"evidence_quote":"Supplies the switch-mode implementation of the nonlinear PT-symmetric circuit that the clock-pulling design builds on."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Gives the nonlinear PT-symmetric model for constant-efficiency WPT, another baseline whose behavior the paper extends."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Establishes dispersive gain as a steady-state selection tool for asymmetric non-Hermitian WPT, the conceptual predecessor of the frequency-dependent gain analysis here."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Is the coupled-mode theory used to write the dimer Hamiltonian and derive the characteristic equation for steady states."},{"cited_title":"Schindler, A","cited_arxiv_id":null,"evidence_quote":"Documents the rapid and discontinuous transient frequency shifts in PT-symmetric active circuits that motivate the need for a classical clock in the feedback loop."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Is the phaselock-techniques reference that the clock-pulling PLL implementation is based on."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Carries the modeling details, stability analysis, and experimental setup parameters that support the reported measurements."}],"review_version":1}