{"id":"436e8010-e772-49f6-9564-bbc6599b683b","arxiv_id":"2508.13159","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":4.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":4,"one_line_summary":"An RC long-chain reduction method accelerates Ngspice transient simulation by an average of 8.8% on ISCAS-85 benchmarks with under 0.7% output error.","lead":"This paper proposes ways to speed up transistor-level circuit simulation by replacing long chains of resistors and capacitors with simpler equivalent forms. On standard benchmark circuits this gives about an 8.8% average speedup (up to 22%) while keeping output errors below 0.7%.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Benchmark reduction is valid only if every deleted chain node is a pure two-terminal link; the chain detector is unspecified and output remapping can hide errors, so the 8.8%/0.7% claim is not yet fully supported.","rationale":"The paper's mathematical derivation in Section 4 is standard and the function-driven simulations provide some empirical support for the two implemented regimes. However, the benchmark speedup is the main claimed contribution, and it depends on an automated netlist transformation whose correctness conditions are not verified. The reader's weakest assumption identifies exactly this gap: the purity of the identified chains and the validity of the output remapping. I agree that this is the most load-bearing concern. If the chains are pure and the remapping is honest, the concern does not land; if not, the benchmark results overstate both speedup and accuracy. Because the issue is concrete and addressable by inspecting the released code and re-running with full node monitoring, the appropriate verdict remains CONDITIONAL rather than ACCEPT or REJECT. My read does not change the reader's verdict, so the verdict should be unchanged.","tokens_in":17639,"tokens_out":12923,"duration_ms":146180,"concrete_test":"Run the open-source chain detector on each *_ann.net and, for every node deleted in *_simp.net, compute its incident-edge count in the original netlist (excluding the node's own capacitor to ground). Verify each such node has exactly two resistor edges to its chain neighbors and zero connections to MOSFET terminals or other branches, and report violations per circuit. Additionally, instrument one high-split circuit (e.g., c5315 or c1355) by adding output commands for every original chain node and compare full Ngspice transient against *_simp.net with the same remapping rule; if the maximum relative error over all chain nodes exceeds the reported 0.7%, the headline error metric is misleading.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central speedup claim (Section 5.2, Table 8, Figure 5) rests on replacing each identified RC long chain by a single grounded capacitor (n+1)C at the chain head. This is exact only if the chain is a pure ladder: every interior node has exactly two resistive neighbors and one capacitor to ground, with no gate, drain, or other branch touching it. Section 3.3 asserts this structure for a Tarjan-based analysis, but Section 5.2 does not specify the chain-detection algorithm used to build *_simp.net, nor does it report any check that every deleted node has no side connections. If an interior node drives or is driven by a transistor, deleting that node removes a real circuit branch and the simplified netlist solves a different circuit. The error metric weakens the test further: when an output node lies inside a removed chain, the output expression is replaced with V(chain_start) (Section 5.2), so the comparison measures the chain-head voltage, not the actual deleted node's voltage. The reported 0.7% relative error therefore does not establish that internal chain-node voltages are preserved, and the 8.8% speedup could be accompanied by unmonitored local errors. This is a reproducibility and verification gap in the empirical core of the paper, not a flaw in the mathematical derivation per se.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper studies uniform RC ladder networks ('long chains') attached to a core circuit at one port. It derives an exact frequency-domain admittance Y_n(ω) by solving the KCL recurrence, then proposes three approximations according to the time-constant regime: small (Eq. 17), same order (Eq. 18), and large (Eq. 19). The paper validates the small- and large-regime approximations on synthetic RC chains in Ngspice and applies a chain reduction to ISCAS-85 benchmarks, reporting an average 8.8% speedup and 0.7% relative error. The same-order method is explicitly left as future work.","tokens_in":17923,"tokens_out":5322,"duration_ms":59905,"significance":"The exact closed-form admittance for the uniform RC ladder is a useful theoretical result and is derived without fitting parameters. The asymptotic formulas for small and large time constants are physically plausible and receive synthetic validation. The benchmark study addresses a real performance bottleneck, and the code is open-sourced. However, the central empirical claims are currently weakened by an unverified chain-reduction procedure and by the gap between the abstract's 'three methods' and the two implemented regimes; the significance is contingent on addressing these issues.","major_comments":[{"comment":"The reported 8.8%/0.7% result rests on replacing each chain by a single grounded capacitor (n+1)C at the chain head. This replacement is exact only when every deleted interior node is a pure two-terminal ladder node with exactly two resistive connections and one capacitor to ground, and with no gate, drain, source, or other branch touching it. The paper does not specify the chain-detection algorithm used to build *_simp.net, does not state that it verifies the absence of side connections at every deleted node, and remaps output nodes inside chains to V(chain_start). Consequently, the comparison does not measure voltages at deleted output nodes, and the claimed 0.7% relative error could mask large local errors. Please specify the detector, verify the purity of all deleted nodes (or handle impure chains), and report errors at the original output nodes.","section":"Section 5.2, Table 8"},{"comment":"The abstract and the contribution list claim three reduction methods, but Section 4.4 explicitly states that the same-order method (Eq. 18) is only a conceptual direction with no implementation or accuracy analysis, and Section 5 confirms that experiments cover only Eq. (17) and Eq. (19). The claim of 'three methods' is therefore not supported by the reported work. Either implement and evaluate Eq. (18) or revise the abstract and contributions to report two demonstrated methods plus a proposed extension.","section":"Abstract and Section 4.4"},{"comment":"For the small-time-constant case with EXP input, the reported relative errors are on the order of 10^-1 for n≤64. The paper attributes this to 'differing discretization strategies' without providing evidence. Since the abstract's accuracy claim is unqualified, this large error should be explained quantitatively, or the scope of Eq. (17) should be restricted, for example to smooth inputs with bounded derivatives.","section":"Section 5.1"},{"comment":"The decision rule uses hand-picked parameters α=10 and m=⌊n/2⌋ for n>64, and the Gaussian width M in Eq. (7) is given only as a range. No sensitivity analysis is provided showing how accuracy and speedup vary with these choices, and no selection criterion is given for M within its stated range. Please add a sensitivity study or justify these choices from the error analysis.","section":"Section 4.5"}],"minor_comments":[{"comment":"The phrase 'our methods yields' should be corrected to 'our methods yield'.","section":"Abstract"},{"comment":"The sentence 'all resistors in these chains have the same resistance value of 0.953316Ω' appears to refer specifically to c1355, while the following sentence says values vary from circuit to circuit; clarify that the numerical values are for c1355 or state the per-circuit uniformity differently.","section":"Section 3.3"},{"comment":"The definitions of F_n(s) and G_n(s) involve integrals over all ω, while the numerical evaluation truncates to |λ|≤25; state the truncation error bound or justify the cutoff.","section":"Section 4.1"},{"comment":"The expansion leading to the recurrence with γ_k and β_k omits the definition of I^(k) and the transition to the final recurrence is not derived; since this is explicitly future work, mark the equations as tentative or provide the omitted derivation.","section":"Section 4.4"},{"comment":"The condition 's/α ≤ τ_c ≤ α·d' mixes the simulation step s and the elapsed time d; clarify whether the upper bound should involve d or s and why the regime boundary depends on total simulated time.","section":"Section 4.5"},{"comment":"c3540 and c7552 have exactly zero error despite c3540 having a nonzero split ratio; explain why (for example, no observed output lies inside a reduced chain), otherwise the zero entries appear to be placeholders.","section":"Section 5.2, Table 8"}],"recommendation":"major_revision","confidential_remarks":"The paper is within scope for a circuit-simulation venue. The main concern is not the mathematics but the verification of the benchmark reduction and the calibration of the claims; the authors can likely fix these with additional experiments and revised claims. I would encourage the editor to also verify that the open-source repository contains the actual chain-detection code used to generate *_simp.net, since the paper does not describe it."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Quick take: this is a real but modest result with an overstuffed abstract. The paper derives explicit current formulas for uniform RC chains in the small- and large-time-constant regimes and validates a lumped-capacitor replacement on ISCAS-85 netlists. The math is standard but competently done, and the large-time-constant approximation (Eq. 19) is a genuinely useful piece that TICER-style methods don't cover. That part deserves credit.\n\nThe soft spots are mostly on the experimental side. The abstract claims 'three methods' with experimental demonstration, but the same-order method (Eq. 18) is explicitly future work; only the small- and large-time-constant cases are tested. That overclaim should be fixed. More importantly, the benchmark validation has a verification gap: Section 5.2 doesn't specify the chain-detection algorithm used to build *_simp.net, and it never reports a check that every deleted interior node has no side connections (gate, drain, or other branch). If an interior node drives or is driven by a transistor, deleting it changes the circuit beyond a load approximation. The stress-test concern on output remapping is also valid: when an output node lies inside a removed chain, the comparison substitutes the chain-head voltage, so the 0.7% relative error doesn't actually bound errors at the deleted node. That doesn't sink the method—the port current is the intended abstraction—but it does mean the empirical claim 'preserves internal node voltages' is unverified.\n\nThe error analysis and causality discussion are honest, and the code is open-sourced, which is good. The speedup of 8.8% average (up to 22%) is modest but believable for long industrial runs.\n\nOverall: this paper deserves a serious referee. It has a concrete, correct derivation and a plausible reduction that could save days on multi-week simulations. The referee should ask for (a) a precise description of chain detection, including a check for side connections, (b) an error metric that reports errors at deleted output nodes, and (c) an abstract that matches what was actually implemented. The same-order method can stay as future work, but it shouldn't be billed as a demonstrated method.\n\nI'd send it to review. I wouldn't put it in my own citation list until the experimental verification gap is closed.","headline":"Real but modest RC-chain reduction with a verification gap in the benchmark claims; deserves review, not a pass.","tokens_in":18448,"tokens_out":3064,"would_cite":false,"duration_ms":34674,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"This paper proves that the current entering a uniform RC long chain is exactly fixed by the port voltage and the chain length through a closed-form admittance $Y_n(\\omega)$, and uses that equivalence to delete chain interior nodes…","keywords":["transistor-level simulation","RC long chain","frequency-domain equivalence","time constant reduction","transient analysis","circuit simulation acceleration","node elimination","RC reduction"],"falsifier":"Take any benchmark circuit's original netlist and the simplified netlist produced by the paper's chain deletion, and list every edge incident to a deleted interior node; if any such edge connects to a MOSFET terminal or to a node outside the chain, the deletion changes the circuit beyond the claimed load equivalence. A direct test is to modify one circuit so that an interior chain node drives a transistor gate, rerun the transient simulation, and check whether the output waveform moves by more than the claimed 0.7% relative error.","tokens_in":17411,"feed_emoji":"⚡","tokens_out":11792,"duration_ms":123442,"temperature":0.7,"pith_summary":"Transistor-level simulation of integrated circuits is slow because every time step requires factoring a large sparse matrix. The paper identifies a recurring substructure in real circuits: long chains built from identical resistors and grounded capacitors, which occupy on average 6.34% of the nodes. It derives an exact frequency-domain equivalence for such chains: the current entering the chain is determined solely by the port voltage and the chain length through an admittance $Y_n(\\omega)$. From that equivalence it obtains three reduction rules for small, intermediate, and large time constants. If the equivalence holds, the interior nodes of these chains can be collapsed, shrinking the simulation matrix and speeding up transient analysis by 8.8% on average (up to 22%) with 0.7% relative error on standard benchmark circuits.","feed_headline":"Exact RC-chain identity speeds transistor simulation by up to 22%","feed_subtitle":"One admittance formula deletes chain interior nodes, cutting simulation time 8.8% at 0.7% relative error.","key_machinery":"The central object is the RC long chain: a path of $n$ equal resistors, with every node grounded through an equal capacitor, terminating in a closed end. Its behaviour is carried by the port admittance $Y_n(\\omega)$, the ratio of input current to port voltage in the frequency domain, obtained by solving the KCL recurrence with characteristic roots $a$ and $b$. The paper evaluates the inverse Fourier transform with a Gaussian envelope $e^{-M^2t^2}$ to guarantee convergence, and enforces causality either by forcing $V_0$ to vanish after the time step or by replacing $Y_n$ with its causal version via a Hilbert transform. A numerically stable form $H_n(\\omega)$ is introduced to compute $Y_n$ without cancellation. These pieces turn the chain into a one-port element whose current can be written directly from $V_0$, which is what allows the interior nodes to be eliminated.","core_discovery":"The central claim is that a uniform RC long chain—$n$ identical resistors $R$ in series with $n+1$ identical grounded capacitors $C$—has a port behaviour completely captured by the admittance $Y_n(\\omega)$ in equation (6), so the current $I(t)$ into the chain is a function only of the port voltage $V_0$ and the length $n$. Solving the KCL equations by Fourier transform gives a second-order recurrence whose characteristic roots yield this closed form. Depending on how the time constant $\\tau=RC$ compares with the simulation time step, the paper derives three regimes: for small $\\tau$, all nodes charge together and $I(t)\\approx (n+1)C\\,dV_0/dt - \\frac{n(n+1)}{2}RC^2\\,d^2V_0/dt^2$ (equation 17); for large $\\tau$, only the first two nodes respond and the rest of the chain contributes negligibly (equation 19); for $\\tau$ of the same order as the time step, the paper proposes an $m$-order recurrence in past currents and voltages as a conceptual direction, without a full implementation. The benchmark simplification deletes all interior chain nodes and replaces the port capacitor by $(n+1)C$. On the benchmark circuits, this yields an average 8.8% speedup (up to 22%) with 0.7% relative error, with the largest gains on circuits whose chains hold the largest share of nodes.","pith_inferences":["A natural extension: because $Y_n(\\omega)$ depends only on $n$, $R$, and $C$, a simulator could precompute it for every chain length in a netlist and turn the reduction into a lookup rather than a per-chain derivation.","The same-order recurrence is a short-memory approximation of the convolution with $Y_n$; if implemented, it could be combined with node-elimination methods to reduce chains that currently fall outside both approaches' regimes.","Because the reported speedup tracks the split ratio, the method should give larger gains on power grids, clock trees, or interconnect-dominated netlists where RC chains are denser than in these benchmarks.","The weighted relative-error metric used in the paper downweights near-zero current samples; circuits dominated by long quiet periods may show larger per-point deviations than the 0.7% average, so the error number should be read as a weighted aggregate, not a worst case."],"forward_implications":["For small time constants, each chain can be replaced by a single port node with capacitance $(n+1)C$, removing $n$ nodes and their resistors from the simulation matrix.","For large time constants, only the first two nodes of the chain matter; the remaining nodes can be discarded without appreciable error.","For time constants comparable to the simulation step, a recurrence over past currents and voltages would extend the reduction into the regime where node-elimination methods are not reliable.","The speedup on a given circuit grows with the share of nodes held in chains; circuits without such chains show no improvement.","The reduction is a preprocessing step, so it composes with any downstream sparse solver and does not change the numerical integration scheme."],"supporting_citations":[{"why":"Supplies the baseline time-constant-balancing reduction that this paper extends to chains with relatively large time constants.","marker":"[29]"},{"why":"Provides the sparse LU solver that the benchmark experiments use and whose factorisation cost the reduction is meant to lower.","marker":"[11]"},{"why":"Supplies the reference simulator and the example netlists used for error and runtime comparison.","marker":"[24]"},{"why":"Origin of the combinational circuits whose enlarged versions form the benchmark suite.","marker":"[5]"},{"why":"The graph-decomposition algorithm used to separate the core circuit from the long-chain structures.","marker":"[35]"},{"why":"The sparse solver used in the function-driven simulations that validate the reduction formulas.","marker":"[20]"}],"fun_headline_variants":["RC chain identity speeds IC simulation up to 22%","Exact RC-chain reduction boosts simulation 8.8%","Deleting RC chain nodes accelerates circuit sim 22%","RC long-chain equivalence cuts simulation time 22%","Fast RC-chain simulation with 0.7% error"],"cache_read_input_tokens":3200,"weakest_assumption_plain":"The method assumes every interior node of a detected chain is a pure two-terminal link—connected only to its two chain neighbours through equal resistors and to ground through a capacitor—with no gate, drain, or other branch attached, and the benchmark experiments do not explicitly verify this property for the chains they simplified.","fun_headline_variants_meta":{"raw":{"variants":["RC chain identity speeds IC simulation up to 22%","Exact RC-chain reduction boosts simulation 8.8%","Deleting RC chain nodes accelerates circuit sim 22%","RC long-chain equivalence cuts simulation time 22%","Fast RC-chain simulation with 0.7% error"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000245,"raw_usage":{"total_tokens":1549,"prompt_tokens":974,"completion_tokens":575,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":590,"completion_tokens_details":{"reasoning_tokens":493}},"tokens_in":590,"tokens_out":575,"duration_ms":6898,"temperature":1.0,"reasoning_tokens":493,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-06T16:47:47.410384+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Take any benchmark circuit's original netlist and the simplified netlist produced by the paper's chain deletion, and list every edge incident to a deleted interior node; if any such edge connects to a MOSFET terminal or to a node outside the chain, the deletion changes the circuit beyond the claimed load equivalence. A direct test is to modify one circuit so that an interior chain node drives a transistor gate, rerun the transient simulation, and check whether the output waveform moves by more than the claimed 0.7% relative error.","supporting_citations":[{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Supplies the baseline time-constant-balancing reduction that this paper extends to chains with relatively large time constants."},{"cited_title":"Davis and Natarajan","cited_arxiv_id":null,"evidence_quote":"Provides the sparse LU solver that the benchmark experiments use and whose factorisation cost the reduction is meant to lower."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Supplies the reference simulator and the example netlists used for error and runtime comparison."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Origin of the combinational circuits whose enlarged versions form the benchmark suite."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"The sparse solver used in the function-driven simulations that validate the reduction formulas."}],"review_version":1}