{"id":"900ca4cd-bbc4-4ede-9135-1ebf6efbcee8","arxiv_id":"2602.04847","paper_version":2,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":5.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":3,"one_line_summary":"A-Graph/Archx represents a complete computer system as one weighted directed acyclic graph, letting users estimate performance and cost at any chosen granularity for CMOS or superconducting technologies.","lead":"This paper presents A-Graph, a graph representation that models application, software, architecture, and circuit levels in one structure, with a Python framework Archx that builds and sweeps these graphs. The pitch: engineers could simulate performance and cost across CMOS and superconducting designs at any granularity, before committing to RTL.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Temporal dependencies and dynamic behavior are not represented in the A-Graph WDAG; they live in user-written performance models, undercutting the claim that stack changes can be captured by updating nodes and edges (Sec. III vs VII.B).","rationale":"The reader's weakest assumption already identified user-supplied performance models and granularity as the key risk. This stress-test sharpens that into a precise representational concern: the WDAG is acyclic and its edges carry static scalar weights, while temporal dependencies are explicitly excluded from the graph and placed inside arbitrary performance-model code. That means the strongest claim—'unified graph representation' enabling 'at-will simulation'—is not self-validating and is internally conceded in Section VII.B. The CMOS case studies against Cadence EDA flows provide real evidence that the framework works for static analytical mappings, so this is not a reason to reject the paper. But the manuscript should either narrow the claim to statically analyzable workloads or extend the graph with first-class temporal dependencies. The proposed MAC pipeline test would settle empirically whether the current graph formalism is sufficient or whether the burden falls entirely on user code. Since the reader's CONDITIONAL verdict already reflects this class of concern, no verdict change is needed.","tokens_in":22080,"tokens_out":5308,"duration_ms":63795,"concrete_test":"Use the Listing 2 MAC example: instantiate the same A-Graph with identical nodes, subevent counts, and aggregation types for (a) a 1-cycle fused MAC and (b) a 2-cycle pipelined MAC. If the only way to make (b) produce a different cycle_count/runtime is to edit the Python performance model—i.e., no node/edge/aggregation change suffices—then temporal dependency is not encoded in the graph. This directly tests the §III claim that stack changes can be reflected by updating nodes and edges.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central claim is that A-Graph is a unified graph representation in which 'any changes in technologies, architecture, and applications can be reflected in this graph structure by updating nodes and edges properly' (§III). The load-bearing condition is that the WDAG itself carries the dependency information needed for cross-stack simulation. That condition is not met. §III.A.2 states that 'weighted edges do not reveal temporal dependencies between events'; instead, 'temporal dependencies of events are captured inside the performance models of the parent event.' §IV.B.1 then shows performance models are arbitrary user-written Python functions that compute edge weights once before traversal; §III.C offers only three static aggregation patterns (module sum, summation, and max/sum for parallel/sequential). Consequently, dynamic or data-dependent behavior—pipeline stalls, backpressure, cache/memory contention, control-flow-dependent reuse—cannot be represented in the graph; it must be pre-collapsed into scalar counts by the user's model. The paper's own §VII.B concedes: 'This leaves Archx to rely on user expertise to maintain proper spatial and temporal relationships.' If temporal relationships are outside the graph, the strong form of the central claim—a unified graph whose updates reflect stack changes—does not hold; A-Graph is an aggregation harness over user-supplied performance models, not a representation that makes cross-stack simulation 'at will.' The case studies do not test the missing capability: all use static, closed-form mappings (e.g., GEMM tile counts, FFT butterflies), and Fig. 10 shows up to 30.8% error when leaf granularity is chosen differently. This is not a fatal flaw in the tool, but it is a real gap between the title's 'at-will simulation across system stacks' and what the graph can express.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper proposes A-Graph, a weighted directed acyclic graph intended to unify application, software, architecture, and circuit abstractions into a single representation, together with Archx, a Python framework that implements A-Graph for design space exploration. A-Graph uses event nodes, weighted dependency edges, and a small set of aggregation patterns (module, summation, specified sequential/parallel) to compute metrics such as area, power, energy, cycle count, and runtime. Archx adds a front-end programming interface, automatic sweeping under user constraints, and scope-based metric retrieval. The authors validate the approach through five case studies: CMOS FFT and systolic arrays and a TNN column against a full EDA flow, and superconducting FIR and CNN arrays against published results. The central claim is that A-Graph enables 'at-will simulation' with high accuracy across arbitrary technologies, architectures, applications, and granularities.","tokens_in":22390,"tokens_out":6493,"duration_ms":67435,"significance":"If the claims were fully supported, this would be a useful contribution: a single pre-RTL representation spanning multiple system stacks, with pattern-based metric aggregation and flexible user-defined metrics, is more general than domain-specific simulators such as Aladdin, Accelergy, or DSAGEN. The CMOS validation against a genuine EDA flow (synthesis and place-and-route) is a strength, and the two superconducting case studies demonstrate the intended technology flexibility. The paper also has a concrete artifact, Archx, and the scope-based retrieval idea is genuinely convenient for hierarchical analysis. However, the conceptual and empirical support for the strongest claims is incomplete: the graph itself does not encode temporal dependencies, the accuracy of the examples depends on post-hoc granularity choices, and the superconducting FIR validation is not independent. These issues are addressable in revision but currently prevent me from recommending acceptance.","major_comments":[{"comment":"The central claim that cross-stack changes can be captured 'by updating nodes and edges properly' is not supported by the design as described. Section III.A.2 states that 'weighted edges do not reveal temporal dependencies between events' and that temporal dependencies are 'captured inside the performance models of the parent event.' Section IV.B.1 confirms that these performance models are arbitrary user-written Python functions that compute edge weights once before graph traversal, and Section III.C provides only three static aggregation patterns (module, summation, specified). Thus dynamic behavior such as pipeline stalls, backpressure, data-dependent timing, and contention is pre-collapsed into scalar values by the user's model rather than represented in the WDAG. The paper's own limitation section (VII.B) concedes that Archx must 'rely on user expertise to maintain proper spatial an","section":"Sections III.A.2, III.C, IV.B.1, VII.B"},{"comment":"The claimed 'high accuracy' is strongly dependent on the user's choice of leaf-module granularity, and there is no principled way to choose it a priori. In the FFT study (Figure 8), the PE granularity caps errors at 15%, while PE-Sub granularity gives errors that grow with array size. In the systolic array study (Figure 10), the PE implementation is better at small array sizes but PE-Sub is better at larger, with dynamic energy errors reaching -30.8%. The paper suggests using 'an ensemble of module databases' but does not provide a method for selecting or combining granularities without access to ground-truth EDA results. Since 'simulate at any granularity, thus accurately, at their own will' is a core claim, this user-dependence must be addressed directly, for example by automatic granularity selection, error bounds as a function of granularity, or a concrete criterion based on wiring c","section":"Section VI.B, Figures 8 and 10"},{"comment":"The FIR superconducting case study is not an independent validation. The text explicitly says 'Without access to the original throughput and area values, we reproduce their reported trends' (Section VI.C.1), so Figure 12 demonstrates only that the Archx model can be tuned to reproduce trends, not that it predicts unknown values. More concerning, Table IV reports leakage power of 8.4 mW with a relative error of 1.81e-14, exactly matching the [27] baseline; this is effectively fitting to the target. Please either obtain the original data and report true prediction errors, or relabel the FIR study as a qualitative/functional reproduction and base the cross-technology 'high accuracy' claim on the CNN case study, where actual baseline numbers are available. As written, the superconducting validation overstates the evidence.","section":"Section VI.C.1 and Table IV"}],"minor_comments":[{"comment":"The code sample has unbalanced brackets/parentheses: `param_value=[[2, 2], [4, 4], sweep=True)` is not valid Python. This appears to be a typo and should be fixed.","section":"Listing 1, line 17"},{"comment":"The performance model snippet shows a malformed dictionary entry (`'runtime': 2}}` and an apparent brace mismatch). Please ensure the listings compile or use ellipses consistently.","section":"Listing 2, lines 14-15"},{"comment":"The text says 'Like Alladin [65]' but the correct name is 'Aladdin.' Also, the author affiliation city is spelled 'Pittsburg' in the byline; it should be 'Pittsburgh.'","section":"Section VII.B"},{"comment":"References [77] and [78] appear to be duplicate versions of the same TNNGen paper. Please check the bibliography and cite each source once.","section":"References"},{"comment":"The x-axis is hard to read: groups of array sizes are listed without separators, and the legend entries (A-Sub, A-PE, EDA-F, EDA-Sub, EDA-PE) are not clearly tied to the bar groups. A table or clearer axis labels would help.","section":"Figure 7"},{"comment":"There is a typo: 'V on Neumann' should be 'von Neumann.' Please proofread the manuscript for similar minor errors.","section":"Section II.C"}],"recommendation":"major_revision","confidential_remarks":"The paper has a plausible core idea and a reasonable CMOS validation, but the central 'unified graph' claim overreaches the implemented system, and the superconducting validation includes at least one case where the reported agreement is effectively exact fit to the baseline. I do not see this as a reject: the issues can be addressed by moderating the claims, adding a proper independent superconducting comparison, and discussing granularity selection. The manuscript would also benefit from editorial cleanup (code listings, typos, duplicate references). On balance, I recommend major revision."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"First thing: the core idea is sound but narrower than advertised. A-Graph is a WDAG that lets you decompose application, software, architecture, and circuit stacks, attach user-defined metrics, aggregate with three traversal patterns, and query at any scope. That is genuinely useful, and it is more general than Charm, Aladdin, Accelergy, or DSAGEN, each of which only covers part of the stack. The CMOS validation against Cadence synthesis and place-and-route is the strongest part of the paper: errors are mostly under 15%, and Figure 10 honestly shows granularity choice can push dynamic energy error to about 30%. That is a real external check, and the paper gives it proper weight.\n\nWhere I part with the framing is the 'at-will' language. The stress-test note is correct: temporal dependencies are not in the WDAG. Section III.A.2 says edges do not reveal temporal relationships; those are captured inside user-written performance models, which are arbitrary Python functions executed before traversal. So stack changes are not fully reflected by updating nodes and edges; they are reflected by editing the models that generate edge weights. A-Graph is an aggregation harness over user-supplied models, not a representation that itself carries the dependency information for cross-stack simulation at will. That is not fatal, but it should be said plainly.\n\nThe superconducting case studies are the weakest evidence. The FIR study says it reproduces reported trends because the original throughput and area values are unavailable, and Table IV's leakage power matches the baseline to 1.8e-14, which is machine precision. That is fitting, not independent estimation. The CNN study against [28] is better but still relies on the same group's numbers. I would want independent ground truth or at least the artifact released. Which brings me to the missing artifact: no code, no data. For a framework whose main selling point is programmability, that is a real obstacle.\n\nMinor issues: no error bars, a small case-study set, and the granularity question is answered with advice ('create an ensemble of module databases') rather than a criterion. Table I and some comparisons are a bit generous to the contribution, but the related-work coverage is fair.\n\nBottom line: the paper is worth a serious referee. The graph-plus-DSL package is a plausible foundation for pre-RTL DSE, especially for emerging technologies where no full design flow exists. A good reviewer would ask for artifact release, an a priori granularity rule or error bound, and an honest rewording of the at-will claim. I would not desk-reject.","headline":"A credible unified-graph framing for pre-RTL DSE with real EDA validation, but the 'at-will' claim overreaches: temporal behavior lives in user code, granularity is chosen post hoc, and superconducting validation partly reproduces prior trends.","tokens_in":23021,"tokens_out":2658,"would_cite":false,"duration_ms":30950,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"A-Graph claims that representing a system as a weighted directed acyclic graph of events lets designers simulate performance and cost at any granularity across application, software, architecture, and circuit stacks.","keywords":["graph-based simulation","design space exploration","weighted directed acyclic graph","performance and cost modeling","cross-stack system simulation","metric aggregation","at-will simulation","emerging technology evaluation"],"falsifier":"Run Archx on a fixed CMOS GEMM systolic array with leaf nodes set at processing-element level and at submodule level, then compare reported area and dynamic energy against a full place-and-route EDA flow for the same design. If the submodule version underestimates dynamic energy by more than about 30% for a 32x32 array while the processing-element version matches, the claim that users can simulate accurately at any chosen granularity is not self-fulfilling without explicit guidance on choosing leaf granularity.","tokens_in":21922,"feed_emoji":"🕸️","tokens_out":5460,"duration_ms":51955,"temperature":0.7,"pith_summary":"Simulating a whole computer system—application, software, architecture, and circuit—usually means picking one abstraction level and a simulator tied to that level. This paper claims that a single weighted directed acyclic graph (WDAG), whose nodes are events and whose weighted edges are dependencies, can represent all four levels at once, so a designer can ask for performance or cost at any granularity, for any technology (CMOS, superconducting, and others), and for any application, by updating nodes and edges rather than rewriting a simulator. To make that idea usable, the paper presents Archx, a framework that turns a few lines of user code into swept design points, builds the WDAG, computes edge weights via performance models, and retrieves metrics by graph traversal. If the claim holds, design-space exploration before RTL would no longer be tied to a single stack, and the same description could compare a CMOS accelerator, a superconducting accelerator, a neuromorphic core, and a classical GEMM engine on equal footing. The paper backs the claim with case studies across CMOS and superconducting technologies, with errors mostly in the low single digits to about 15%, though some configurations reach roughly 30%.","feed_headline":"One graph spans app-to-circuit simulation at any granularity","feed_subtitle":"A weighted DAG lets designers sweep performance and cost across CMOS, superconducting, and neuromorphic stacks from one description.","key_machinery":"The load-bearing object is the weighted directed acyclic graph (WDAG): nodes are events (workload events, module events, and subevents), edges carry weights that count parent-to-child invocations, and acyclicity guarantees a deterministic topological order for metric aggregation. Three aggregation patterns—module, summation, and specified (sequential versus parallel)—define how metrics propagate upward, and scope-based metric retrieval lets the same graph answer questions about a single module, a tagged group such as a processing element, an event, or the whole workload. The paper also introduces a constraint-graph-based front end that generates and sweeps design points from user code, and a","core_discovery":"The paper's central claim is that at-will simulation is achievable: a user-defined weighted DAG of events, spanning application, software, architecture, and circuit, lets a designer simulate performance and cost at any granularity with any metric, and is agnostic to technology, architecture, and application. Events can be as coarse as a full workload or as fine as an individual register; edge weights count how many times a subevent is invoked by its parent, and metrics are computed by topologically traversing the graph and aggregating leaf-node values according to three patterns: module (direct leaf metric), summation (additive across edges), and specified (sequential sum or parallel max). B","pith_inferences":["If A-Graph were widely adopted, a natural next step would be shared, validated libraries of event decompositions and module databases, letting cross-stack co-design become a matter of composing vetted nodes rather than hand-tuning simulators.","The metric-aggregation mechanism is general enough that it could host non-hardware metrics—energy-delay product, thermal budget, cost per wafer, carbon footprint—as long as they are additive or max-composed along the same dependency graph; the paper gestures at this but does not develop it.","A testable extension is automatic granularity selection: because the paper shows that leaf-node granularity changes accuracy by up to about 30%, a wrapper could search over granularity by predicting wiring and fanout effects, turning at-will granularity into well-chosen granularity."],"forward_implications":["The same A-Graph specification can describe and simulate CMOS and superconducting designs, so early design-space exploration can compare fundamentally different technologies before committing to a design flow.","Users can define new metrics, such as area in Josephson Junctions instead of square millimeters, by registering a metric name, unit, and aggregation pattern; no simulator rewrite is needed.","Because metric retrieval is scope-based, the same design point can be analyzed at the module, processing-element, event, or workload level, giving designers hierarchical visibility into where cost comes from.","The reported simulation speedup over full EDA flows is large (up to roughly 10^5 times faster for pure simulation), which makes broad sweeps of the design space practical before RTL.","Accuracy of the composed graph depends on leaf-module granularity: the systolic-array study shows that choosing submodules instead of whole processing elements can underestimate dynamic energy by roughly 20–30% at larger array sizes, so practical use requires careful granularity choice or an ensemble of module databases."],"fun_headline_variants":["Unified graph enables at-will simulation across system stacks","One graph, any granularity: simulate app to circuit","A graph that unifies simulation across tech, arch, app","At-will design simulation with a unified graph","Graph-based simulation for any system stack"],"cache_read_input_tokens":2304,"weakest_assumption_plain":"The central claim collapses if a user's performance model for an event does not correctly encode the spatial and temporal dependencies inside that event, or if the chosen leaf-module granularity's precomputed circuit data stops being valid when composed; the paper concedes in Section VII.B that Archx relies on user expertise to maintain proper spatial and temporal relationships, and its systolic-array study shows errors up to about 30% when the granularity is too fine.","fun_headline_variants_meta":{"raw":{"variants":["Unified graph enables at-will simulation across system stacks","One graph, any granularity: simulate app to circuit","A graph that unifies simulation across tech, arch, app","At-will design simulation with a unified graph","Graph-based simulation for any system stack"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000424,"raw_usage":{"total_tokens":2061,"prompt_tokens":843,"completion_tokens":1218,"prompt_tokens_details":{"cached_tokens":256},"prompt_cache_hit_tokens":256,"prompt_cache_miss_tokens":587,"completion_tokens_details":{"reasoning_tokens":1142}},"tokens_in":587,"tokens_out":1218,"duration_ms":7953,"temperature":1.0,"reasoning_tokens":1142,"cache_read_input_tokens":256,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-04T00:33:19.912031+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Run Archx on a fixed CMOS GEMM systolic array with leaf nodes set at processing-element level and at submodule level, then compare reported area and dynamic energy against a full place-and-route EDA flow for the same design. If the submodule version underestimates dynamic energy by more than about 30% for a 32x32 array while the processing-element version matches, the claim that users can simulate accurately at any chosen granularity is not self-fulfilling without explicit guidance on choosing leaf granularity.","supporting_citations":[],"review_version":1}