{"id":"1dd52487-b1dc-407a-a192-6e8f5d5fc90c","arxiv_id":"2607.01514","paper_version":1,"verdict":"UNVERDICTED","confidence":"LOW","novelty_score":7.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":0,"one_line_summary":"Monolithic integration of piezo-optomechanical photonic circuits with CMOS electronics on 200 mm wafers, demonstrated via PDACs for digital control of phase shifters, MZIs, and ring resonators.","lead":"Engineers built photonic circuits with piezoelectric actuators directly onto finished commercial CMOS wafers using standard back-end processing. This creates a dense electronic backplane for controlling thousands of optical devices on one chip.","discovery_kind":"new_application","skeptic_critique":{"model":"grok-4.3","headline":"BEOL photonic layer on completed CMOS may degrade electronics or piezo components despite uniformity claims","rationale":"The reader's weakest_assumption directly identifies the load-bearing condition. The abstract's characterization claim does not yet supply the quantitative before/after data needed to close the gap, so the concern stands without internal contradiction in the stated argument.","tokens_in":1806,"tokens_out":280,"duration_ms":13708,"concrete_test":"On the same wafer, measure CMOS driver metrics (e.g., per-channel voltage swing and static power) and piezo actuator displacement at identical test sites before versus after full BEOL photonic stack; if any metric shifts >5% or functional yield falls below 90% across reticles, the no-degradation premise fails.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central claim of monolithic all-CMOS co-fabrication with >2M connections per die and functional POMPICs requires that back-end-of-line processing (SiN waveguides + piezo actuators on finished CMOS) leaves both electronic drivers and optomechanical performance intact. The abstract states wafer-scale electronic/photonic characterization was performed to establish uniformity and yield, yet provides no explicit pre/post-BEOL comparison of CMOS metrics (threshold voltage, leakage, driver output swing) or piezo actuator yield. This is the least secure precondition for the scalability assertion.","agreement_with_reader":"agree"},"referee_report":{"model":"grok-4.3","summary":"The manuscript claims a fully monolithic all-CMOS platform for piezo-optomechanical photonic integrated circuits (POMPICs) fabricated directly on completed 200 mm CMOS driver wafers via back-end-of-line processing. It reports integration of piezoelectric actuators under broadband SiN waveguides with a high-density digital backplane (>2 million electrical connections per die at 6.4×6.4 μm pitch), introduces segmented Photonic Digital-to-Analog Converters (PDACs) for multi-bit analog optical modulation from low-voltage digital signals, demonstrates parallel HDMI-programmed control of phase shifters, Mach-Zehnder interferometers, routing trees, and tunable rings, and states that wafer-scale electronic/photonic characterization across multiple reticles establishes uniformity and yield.","tokens_in":1901,"tokens_out":448,"duration_ms":28292,"significance":"If the central claims are substantiated, the work would provide a concrete route to dense, scalable electronic control of low-power, broadband, cryogenic-compatible POMPICs, addressing a key barrier in EPIC architectures for AI, sensing, and quantum applications by eliminating hybrid bonding and enabling >2 M connections per die.","major_comments":[{"comment":"Abstract: the claim that 'wafer-scale electronic and photonic characterization was performed to establish uniformity and yield' is presented without any quantitative metrics, error bars, yield percentages, uniformity statistics (e.g., standard deviation of actuator response or driver swing), or pre-/post-BEOL comparisons of CMOS parameters (threshold voltage, leakage, output swing) or piezo actuator yield. This data is load-bearing for the assertion that BEOL processing leaves both electronics and optomechanical performance intact.","section":"Abstract"},{"comment":"Main text (fabrication and characterization sections): no explicit pre-/post-BEOL device metrics or failure-mode analysis are supplied to substantiate that the high-density electrode pitch and >2 M connections per die remain functional after photonic/piezo layer deposition, which is the least secure precondition for the monolithic scalability claim.","section":"Main text (fabrication and characterization sections)"}],"minor_comments":[],"recommendation":"major_revision","confidential_remarks":null},"author_rebuttal":{"model":"grok-4.3","summary":"We thank the referee for their careful reading and for highlighting the need for quantitative substantiation of our wafer-scale uniformity and yield claims. We address each major comment below.","responses":[{"response":"We agree that the abstract would be strengthened by explicit quantitative metrics. In the revised manuscript we will expand the abstract to report key statistics from our wafer-scale data, including yield percentages, uniformity (standard deviations of actuator response and driver swing), and available pre-/post-BEOL CMOS parameter comparisons.","revision_made":"yes","referee_comment":"[Abstract] Abstract: the claim that 'wafer-scale electronic and photonic characterization was performed to establish uniformity and yield' is presented without any quantitative metrics, error bars, yield percentages, uniformity statistics (e.g., standard deviation of actuator response or driver swing), or pre-/post-BEOL comparisons of CMOS parameters (threshold voltage, leakage, output swing) or piezo actuator yield. This data is load-bearing for the assertion that BEOL processing leaves both electronics and optomechanical performance intact."},{"response":"We acknowledge that explicit pre-/post-BEOL metrics and failure-mode discussion are needed to fully substantiate functionality of the high-density interconnects. The revised manuscript will add dedicated subsections in the fabrication and characterization sections that present pre- and post-BEOL CMOS and piezo device metrics together with any observed failure modes.","revision_made":"yes","referee_comment":"[Main text (fabrication and characterization sections)] Main text (fabrication and characterization sections): no explicit pre-/post-BEOL device metrics or failure-mode analysis are supplied to substantiate that the high-density electrode pitch and >2 M connections per die remain functional after photonic/piezo layer deposition, which is the least secure precondition for the monolithic scalability claim."}],"tokens_in":1510,"tokens_out":393,"duration_ms":21202,"standing_objections":[]},"desk_editor":{"model":"grok-4.3","letter":"The main point is that they put piezo-optomechanical circuits on top of finished CMOS wafers using back-end processing, wiring piezoelectric actuators under SiN waveguides to a dense digital backplane with 6.4 micron pitch and more than 2 million connections per die. They also show segmented PDACs that turn low-voltage digital signals into multi-bit optical phase and amplitude control, plus HDMI programming of phase shifters, Mach-Zehnders, routing trees, and rings.\n\nThis approach is new in combining POMPICs with monolithically integrated CMOS drivers at wafer scale. It directly targets the electrical interconnect limit that has kept photonic arrays small. The choice of commercial CMOS and standard interfaces makes the control side realistic for larger systems.\n\nThe soft spot is the lack of numbers. The abstract states they ran wafer-scale electronic and photonic tests to confirm uniformity and yield, yet gives no values, no error bars, no pre- versus post-BEOL CMOS metrics like threshold voltage or leakage, and no piezo actuator performance data. Without those, the assumption that the back-end steps leave both the electronics and the optomechanics intact stays untested.\n\nThis paper is for groups building dense photonic processors for AI, sensing, or quantum work who need practical electrical interfacing. A reader focused on fabrication flows would find the process description useful if the full text includes the missing characterization.\n\nIt should go to peer review. The integration claim is substantial enough to warrant referee time, even though the current evidence is thin and the central assumption needs concrete verification.","headline":"The paper claims the first monolithic BEOL integration of POMPICs with commercial CMOS on 200 mm wafers and over 2 million connections, but offers no quantitative data to support the yield or non-degradation claims.","tokens_in":2424,"tokens_out":400,"would_cite":false,"duration_ms":18813,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"grok-4.3","headline":"Piezo-optomechanical photonic devices can be monolithically fabricated on finished CMOS wafers using back-end processing.","keywords":["monolithic integration","piezo-optomechanical photonics","CMOS electronics","photonic integrated circuits","back-end-of-line processing","photonic digital-to-analog converters","silicon nitride waveguides"],"falsifier":"A direct comparison of CMOS driver functionality and photonic modulation efficiency before and after the back-end-of-line photonic layer deposition that shows significant degradation.","tokens_in":2715,"feed_emoji":"🔌","tokens_out":696,"duration_ms":22238,"temperature":0.7,"pith_summary":"The paper establishes that photonic integrated circuits using piezoelectric actuators can be added directly onto completed commercial CMOS chips. This integration links over two million electrical connections per die to control optical components like phase shifters and ring resonators. A sympathetic reader would care because it removes the need for separate electronic and photonic chips, potentially allowing much larger and more complex photonic systems for applications in computing and sensing. The approach uses standard wafer-scale manufacturing steps to achieve this co-fabrication across 200 millimeter wafers.","feed_headline":"Photonic devices integrated monolithically with CMOS on 200mm wafers","feed_subtitle":"Over two million electrical connections per die link piezoelectric actuators to digital control for optical modulation.","key_machinery":"Back-end-of-line processing that builds the photonic layer on completed CMOS wafers, linking piezoelectric actuators under silicon nitride waveguides to a high-density digital backplane with over two million connections per die.","core_discovery":"A fully monolithic platform for piezo-optomechanical photonic integrated circuits is co-fabricated with commercial control electronics on 200 millimeter wafers. Photonic layers are constructed on completed CMOS driver wafers by back-end-of-line processing. This connects integrated piezoelectric actuators under broadband silicon nitride waveguides to a high-density digital backplane with more than two million electrical connections per die at a 6.4 by 6.4 micron electrode pitch. Segmented components function as photonic digital-to-analog converters that turn low-voltage digital signals into multi-bit analog optical phase and amplitude modulation, with parallel control demonstrated via a stand","pith_inferences":["The platform could support control of thousands to millions of reprogrammable photonic devices on a single chip without separate packaging.","The same integration approach might be tested on other photonic material stacks or different CMOS process nodes.","Cryogenic compatibility of the combined system could be checked to assess suitability for quantum computing applications."],"forward_implications":["Segmented POMPIC components convert digital electronic signals to analog optical modulation as photonic digital-to-analog converters.","Parallel control of optical phase shifters, Mach-Zehnder interferometers, optical routing trees, and tunable ring resonators is achieved using a standard HDMI interface to program the CMOS electronics.","Wafer-scale integration is demonstrated through electronic and photonic characterization across multiple reticles and the entire wafer to establish uniformity and yield.","Dense scalable electronic control of piezo-optomechanical circuits becomes possible through the high-density backplane."],"fun_headline_variants":["Monolithic piezo-optomechanical photonics with CMOS on 200mm wafers","POMPICs co-fabricated with CMOS backplane on 200mm wafers","Piezo-optomechanical photonics monolithically integrated with CMOS","200mm wafers enable co-fabricated POMPIC and CMOS electronics"],"cache_read_input_tokens":2112,"weakest_assumption_plain":"Back-end-of-line processing to build the photonic layer on completed CMOS wafers does not degrade the performance or yield of either the electronic drivers or the piezo-optomechanical components.","fun_headline_variants_meta":{"raw":{"variants":["Monolithic piezo-optomechanical photonics with CMOS on 200mm wafers","POMPICs co-fabricated with CMOS backplane on 200mm wafers","Piezo-optomechanical photonics monolithically integrated with CMOS","200mm wafers enable co-fabricated POMPIC and CMOS electronics"]},"model":"grok-4.3","cost_usd":0.004904,"raw_usage":{"total_tokens":2457,"prompt_tokens":776,"num_sources_used":0,"completion_tokens":75,"cost_in_usd_ticks":49037000,"prompt_tokens_details":{"text_tokens":776,"audio_tokens":0,"image_tokens":0,"cached_tokens":256},"completion_tokens_details":{"audio_tokens":0,"reasoning_tokens":1606,"accepted_prediction_tokens":0,"rejected_prediction_tokens":0}},"tokens_in":776,"tokens_out":75,"duration_ms":13267,"temperature":1.0,"reasoning_tokens":1606,"cache_read_input_tokens":256,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-07-03T18:17:32.798769+00:00","model_set":{"reader":"grok-4.3"},"falsifier":"A direct comparison of CMOS driver functionality and photonic modulation efficiency before and after the back-end-of-line photonic layer deposition that shows significant degradation.","supporting_citations":[],"review_version":1}