{"id":"2824ec83-427b-475c-8195-e176167ae1e0","arxiv_id":"2607.13121","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":1,"one_line_summary":"First high-fidelity SiMOS spin qubits fabricated with EUV lithography show 99.9% single-qubit and ~99% two-qubit gate fidelities across four double-dot systems.","lead":"Scientists made silicon quantum-dot spin qubits using extreme-ultraviolet (EUV) lithography on a 300 mm semiconductor line, reaching single-qubit gate fidelities above 99.9% and two-qubit gate fidelities near 99%. The work suggests EUV, already standard in chip factories, could mass-produce silicon quantum processors.","discovery_kind":"new_application","skeptic_critique":{"model":"deepseek-v4-flash","headline":"Wafer-scale uniformity data are for 80 nm-pitch devices, while qubit fidelities come from two 60 nm-pitch devices; no yield/uniformity data or selection criteria are given for the 60 nm geometry, so the manufacturing claim is under-supported.","rationale":"The reader’s weakest assumption—that devices A and B are representative of the 89-die wafer population—is on the right track, but the paper reveals a sharper gap: the 89-die population characterized in Fig. 2 is the 80 nm-pitch design, whereas the qubit devices are 60 nm-pitch. Thus, the two devices are not even drawn from the population whose yield and uniformity are reported. This makes the representativeness concern more concrete and more damaging than a generic selection-bias worry, because it points to a direct mismatch between the uniformity evidence and the qubit geometry. The core experimental demonstration—high-fidelity SiMOS qubits in EUV-fabricated devices—remains credible: GST fidelities are reported with uncertainties, and the devices operate with reproducible exchange. But the broader manufacturing conclusion depends on the 60 nm-pitch process having comparable yield and uniformity, which is not shown. This does not invalidate the paper; it means the manufacturing claim is conditional on additional data. The reader’s CONDITIONAL verdict is therefore appropriate, and no further adjustment is needed.","tokens_in":13855,"tokens_out":6467,"duration_ms":118698,"concrete_test":"Provide the room-temperature leakage yield and CD/overlay statistics for the 60 nm-pitch device variant across the wafer, and state the criterion by which devices A and B were selected for cryogenic measurement (e.g., all available 60 nm devices, first-tested, or best-performing). If the 60 nm-pitch yield is below 100% or its uniformity metrics deviate substantially from the 80 nm-pitch numbers, or if A and B were selected based on favorable screening, the manufacturing-readiness claim for the qubit geometry should be downgraded.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central claim that EUV lithography is a viable manufacturing route for SiMOS spin qubits rests on two pillars: wafer-scale uniformity metrics and qubit fidelities. The paper’s uniformity evidence is explicitly for the 80 nm-pitch design: 'Figure 2a shows the room-temperature gate-to-gate leakage yield for the targeted 80 nm dot-to-dot-pitch design' and the reported dpp and overlay statistics (σ = 0.8 nm and σ = 1.5 nm) are measured on that geometry. However, the qubit devices are 'two more aggressively scaled 60 nm-pitch triple-quantum-dot devices fabricated on the same wafer' (QUBIT BENCHMARKING). The 60 nm pitch is a different, more challenging variant, and the paper provides no room-temperature leakage yield, CD/overlay statistics, or any screening data for it. Moreover, the selection criteria for devices A and B are not stated: they are simply 'performed in-depth characterization on two triple-dot devices' with no information about how they were chosen from the 60 nm-pitch population. Consequently, the inference from 100% yield and sub-nm uniformity on 80 nm devices to manufacturability of the actual 60 nm qubit geometry is unsupported. Even if the qubit fidelities are genuine, they may not be representative of the 60 nm-pitch process, and the wafer-scale reproducibility claim for the demonstrated qubit architecture is not established.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"The manuscript reports a 300 mm pilot-line fabrication of SiMOS quantum-dot spin qubits using extreme-ultraviolet (EUV) lithography. The authors present wafer-scale room-temperature gate-to-gate leakage yield (100% for the targeted 80 nm-pitch triple-dot design), capacitance-equivalent oxide thickness uniformity across three gate layers, sub-nanometer critical-dimension control (σ = 0.8 nm for plunger-to-plunger spacing), and overlay control (σ = 1.5 nm for GL2–GL3). They then characterize two 60 nm-pitch triple-dot devices at 10 mK, operating each as two double-dot systems, and perform gate-set tomography (GST) to report single-qubit X-gate fidelities up to 99.9%, CZ fidelities up to 99.1%, and SPAM fidelities up to 99.8%, with exchange turn-on slopes of 10–13 dec/V. On this basis they claim EUV lithography is a viable manufacturing technology for SiMOS spin qubits.","tokens_in":14227,"tokens_out":4435,"duration_ms":44399,"significance":"The result is significant because it is, to my knowledge, the first demonstration of high-fidelity SiMOS spin qubits patterned by EUV lithography, a technology with throughput and overlay advantages over e-beam. The use of GST with reported 95% confidence intervals is a strength, as is the wafer-scale metrology. The main limitation is that the process-level claims rest on two cryogenically characterized devices, and the wafer-scale uniformity data are for a different (80 nm) pitch than the qubit geometry (60 nm).","major_comments":[{"comment":"The manufacturing-readiness claim is load-bearing, but the wafer-scale yield and uniformity data (Fig. 2a–d) are explicitly for the targeted 80 nm dot-to-dot-pitch design. The qubit devices are 'two more aggressively scaled 60 nm-pitch triple-quantum-dot devices fabricated on the same wafer' (QUBIT BENCHMARKING). No room-temperature leakage yield, CD/overlay statistics, or other screening data are reported for the 60 nm geometry. Since 60 nm pitch is a different and more challenging variant, the 80 nm metrics do not establish wafer-scale manufacturability of the actual qubit architecture. Please either provide equivalent data for the 60 nm design or revise the manufacturing claim to reflect the scope of the evidence.","section":"FABRICATION UNIFORMITY / Fig. 2"},{"comment":"The paper does not state how devices A and B were selected for cryogenic measurement. Only two devices (four double-dot systems) are characterized. Without a defined selection rule, it is not possible to assess whether the reported fidelities are representative of the 60 nm-pitch population or are the result of favorable selection. This is critical because the conclusion generalizes from 'two triple-dot devices' to a process-level statement. Please state the selection criteria (e.g., sequential from a fixed location, random, best-of) and, if possible, provide room-temperature screening or yield data for the 60 nm devices on the same wafer.","section":"QUBIT BENCHMARKING"}],"minor_comments":[{"comment":"The first author's name appears as 'Thomas V an Caekenberghe' with a spurious space; please fix the formatting.","section":"Author list"},{"comment":"The phrase 'Theinsetshows' should read 'The inset shows'.","section":"Fig. 2b caption"},{"comment":"The unit for exchange controllability is written inconsistently as 'dec/V' in the abstract and 'dec V^{-1}' in the main text; harmonize.","section":"Abstract / Fig. 4e"},{"comment":"The phrase 'fault-tolerance threshold commonly associated with the surface error correction code' is vague; specify a concrete threshold value or cite the specific estimate used.","section":"DISCUSSION"}],"recommendation":"major_revision","confidential_remarks":"The paper is a solid experimental demonstration. My main concern is the gap between the 'manufacturing technology' claim and the data: the wafer-scale data are for 80 nm pitch, while the qubits are 60 nm pitch and only two devices. If the authors can supply any 60 nm yield/screening data or explicitly limit the claim to a demonstration, I would be satisfied. The GST methodology is rigorous; I do not doubt the reported fidelities for the measured devices."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"This paper does something genuinely new: it shows that EUV lithography can pattern SiMOS quantum-dot devices with sub-20 nm exchange gates and that those devices support high-fidelity spin qubits. The GST numbers (99.8–99.9% for SPAM/single-qubit, 99.1% for two-qubit) are credible and clearly described. The combination of an industrial 300 mm pilot line with a rigorous QCVV benchmark is the strongest part. GST on four double-dot systems is a step beyond simple Rabi or randomized benchmarking, and the error-generator breakdown is useful. The measured exchange controllability (11.3 ± 2.6 dec/V) is consistent across devices, which is a good sign of process reproducibility.\n\nThe soft spot is a geometry mismatch, and it's exactly what the stress-test note flags. All the wafer-scale uniformity metrics — 100% leakage yield, CD variation σ = 0.8 nm, overlay σ = 1.5 nm — are taken on the 80 nm-pitch design. The qubit devices are a more aggressively scaled 60 nm-pitch variant. The paper never gives leakage yield, CD/overlay statistics, or screening data for the 60 nm geometry, and it doesn't state how devices A and B were selected. So the inference from “uniform 80 nm process” to “manufacturable 60 nm qubit process” is not directly supported. This isn't fatal, but it is a real gap that needs to be closed, either with 60 nm-pitch yield data or with a statement that the 60 nm devices are representative.\n\nSecond, the raw data are promised only upon publication. GST fidelities come with 95% CIs, which is good, but independent scrutiny would benefit from the actual datasets. That's a minor issue given that the main claims are experimental, not derived from simulations.\n\nI'd push back against a stricter skeptic here: the absence of selection criteria doesn't mean the devices were cherry-picked. The qubit-level measurements are already a significant amount of work, and the authors are transparent about the small sample. The paper is a milestone, not a full manufacturing demonstration. The conclusion goes a little beyond the evidence, but the underlying data look solid.\n\nThis paper deserves peer review. It's the kind of result that people in the field need to see and interrogate. I'd recommend sending it to a venue with strong experimental quantum-dot and QCVV expertise, and asking for the 60 nm-pitch uniformity data and device-selection rationale as part of the revision.\n\nFor a reader: anyone working on silicon spin qubits, industrial fabrication, or QCVV should read it. It's a useful comparison point for e-beam and 300 mm foundry work.","headline":"EUV-patterned SiMOS spin qubits with GST fidelities approaching 99.9% are a real milestone, but the wafer-scale uniformity evidence and the qubit benchmarks come from different geometries, so the manufacturing-readiness claim is under-supported.","tokens_in":14872,"tokens_out":2324,"would_cite":true,"duration_ms":24115,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":["85.35.Gv","03.67.Lx"],"model":"deepseek-v4-flash","headline":"Extreme-ultraviolet lithography can pattern silicon spin qubits whose operation fidelities reach 99.9% for single-qubit gates and 99.1% for two-qubit gates.","keywords":["silicon spin qubits","EUV lithography","SiMOS quantum dots","gate set tomography","quantum-dot uniformity","exchange coupling","300 mm wafer fabrication","semiconductor quantum computing"],"falsifier":"Cryogenically benchmark a random sample of dies from the same wafer with the same gate-set-tomography protocol. If a substantial fraction of the 60-80 nm-pitch devices fail to form stable double dots or yield single-qubit fidelities far below 99%, the manufacturing-readiness claim collapses. A simpler first check is to report how devices A and B were selected from the 89-die population.","tokens_in":13754,"feed_emoji":"⚛️","tokens_out":6894,"duration_ms":68997,"temperature":0.7,"pith_summary":"The paper sets out to show that extreme-ultraviolet (EUV) lithography, the parallel exposure method used in advanced chip manufacturing, can replace electron-beam writing for making silicon metal-oxide-semiconductor (SiMOS) spin qubits. It reports that a full 300 mm wafer of triple-quantum-dot devices passed room-temperature leakage screening, with sub-nanometer gate-dimension control, and that two devices cooled to millikelvin temperatures operated as four double-dot qubit systems. Gate-set tomography on all four systems gave fidelities up to 99.8% for state preparation and measurement, 99.9% for single-qubit gates, and 99.1% for two-qubit gates, with reproducible exchange turn-on slopes of 10-13 dec V-1. If true, this removes a major obstacle to scaling silicon spin qubits beyond laboratory prototypes, because EUV exposure is high-throughput, wafer-scale, and already aligned with industrial CMOS manufacturing.","feed_headline":"EUV lithography produces silicon spin qubits at 99.9% fidelity","feed_subtitle":"Wafer-scale 300 mm EUV patterning yields qubits on par with e-beam, a practical route to large silicon processors","key_machinery":"The load-bearing object is a three-layer overlapping polysilicon gate stack patterned by single-exposure 0.33 NA EUV lithography with a metal-oxide resist. The critical dimension is the exchange gate: at 60 nm dot-to-dot pitch, the J gates are narrower than 20 nm at the Si/SiO2 interface, and their voltage response follows a reproducible exponential turn-on of 10-13 dec V-1. This uniformity, combined with ~12 nm gate-oxide thickness and 1.5 nm overlay precision, is what lets four double-dot systems reach near-threshold fidelities with similar operating points. Gate-set tomography is the benchmarking mechanism that translates this fabrication reproducibility into per-gate operation fidelities","core_discovery":"The central claim is that EUV lithography can define SiMOS quantum-dot spin qubits with the dimensional control required for high-fidelity operation, and that this was achieved on a 300 mm pilot line. The evidence is a wafer in which all 89 dies passed room-temperature gate-to-gate leakage tests, critical dimensions varied by less than 1 nm, and gate-oxide thickness varied by fractions of a nanometer. Two triple-dot devices with 60 nm dot-to-dot pitch, comprising four double-dot systems, were then characterized at 10 mK. Gate-set tomography yielded SPAM fidelities up to 99.8%, single-qubit X-gate fidelities up to 99.9%, and CZ two-qubit fidelities up to 99.1%, comparable to e-beam-defined de","pith_inferences":["A natural extension the authors do not state: if the two devices were drawn at random from the wafer, the same uniformity arguments would support qubit-level yield across the 89-die population; cryogenic testing of additional random dies would confirm this.","The consistent exchange turn-on suggests shared operating-voltage patterns could work across a die, which would ease automated tune-up and move the field closer to shared-control crossbar architectures.","As fabrication uniformity improves, the effective bottleneck shifts from making qubits to measuring them; multiplexed or wafer-level cryogenic probing would be the next capability to develop."],"forward_implications":["EUV becomes a viable front-end for silicon spin-qubit production, replacing serial e-beam writing with a single-exposure, high-throughput process.","Qubit operation fidelities approaching the surface-code threshold can be achieved without custom laboratory fabrication.","Uniform gate dimensions and exchange turn-on reduce calibration overhead, making automated electrostatic tune-up feasible across many devices.","The same process can be extended to denser architectures, with future high-NA EUV possibly enabling single-layer gate layouts.","Manufacturing and qubit performance become jointly optimizable: process metrics such as leakage yield and critical-dimension spread can be tracked at wafer scale."],"fun_headline_variants":["EUV lithography hits 99.9% qubit fidelity on 300mm wafers","Wafer-scale EUV spin qubits match e-beam performance","EUV-defined qubits deliver 99.9% gate fidelity at scale","300mm EUV pilot line yields high-fidelity silicon qubits","EUV lithography enables reproducible, high-fidelity spin qubits"],"cache_read_input_tokens":2304,"weakest_assumption_plain":"The load-bearing premise is that the two triple-dot devices measured at millikelvin temperatures are representative of the whole 89-die wafer; the paper does not state how they were chosen, so wafer-scale qubit yield is inferred rather than directly measured.","fun_headline_variants_meta":{"raw":{"variants":["EUV lithography hits 99.9% qubit fidelity on 300mm wafers","Wafer-scale EUV spin qubits match e-beam performance","EUV-defined qubits deliver 99.9% gate fidelity at scale","300mm EUV pilot line yields high-fidelity silicon qubits","EUV lithography enables reproducible, high-fidelity spin qubits"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000252,"raw_usage":{"total_tokens":1427,"prompt_tokens":805,"completion_tokens":622,"prompt_tokens_details":{"cached_tokens":256},"prompt_cache_hit_tokens":256,"prompt_cache_miss_tokens":549,"completion_tokens_details":{"reasoning_tokens":523}},"tokens_in":549,"tokens_out":622,"duration_ms":5795,"temperature":1.0,"reasoning_tokens":523,"cache_read_input_tokens":256,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-02T06:08:47.981626+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Cryogenically benchmark a random sample of dies from the same wafer with the same gate-set-tomography protocol. If a substantial fraction of the 60-80 nm-pitch devices fail to form stable double dots or yield single-qubit fidelities far below 99%, the manufacturing-readiness claim collapses. A simpler first check is to report how devices A and B were selected from the 89-die population.","supporting_citations":[],"review_version":1}