{"id":"c5a7a3a7-f152-461b-882a-59c6ddc2937e","arxiv_id":"2607.21693","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":5,"one_line_summary":"Micro-electromechanical cantilevers on a CMOS silicon-nitride photonic chip store multi-level optical phase and amplitude states (up to 5 bits) with >1-hour retention, 50-kbit/s programming, and >1-billion-cycle endurance.","lead":"A new kind of optical memory stores up to 5-bit values by flexing tiny silicon-nitride cantilevers on a photonic chip and letting them stick in place, holding the state for hours without power. The device survived over a billion write cycles, making it a candidate for durable, energy-lean optical computing hardware.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"5-bit capacity and >1-hour non-volatility are never demonstrated simultaneously; multi-level states require refresh at 1–100 s, undercutting the central memristor claim.","rationale":"The reader's weakest assumption concerns the uncontrolled stiction mechanism and the 27x lifetime spread. While valid, both observed devices exceed the 1-hour threshold, so the '>1 hour' claim is not directly contradicted. A more immediate logical problem is that the multi-bit and non-volatility metrics are never achieved together. 5-bit and 4-bit tests run at T = 1 s, and 3-bit degrades at T = 100 s; hence the abstract's '5-bit' and '>1 hour' cannot both be read as properties of a single operating mode. This matters because the central claim is a practical multi-level non-volatile memristor. The stiction uncertainty may explain this tradeoff, but the tradeoff itself is the load-bearing gap; the paper must either demonstrate multi-bit retention at ~1 hour or qualify the claim. This does not change the CONDITIONAL verdict, but adds a specific required condition.","tokens_in":16198,"tokens_out":6269,"duration_ms":62565,"concrete_test":"Run the 5-bit pseudorandom sequence (Fig. 5d protocol) with read-write period T = 3600 s instead of T = 1 s, keeping all other conditions identical, and measure BER. If BER exceeds a practical threshold (e.g., >1e-2) well before 1 hour, the abstract's juxtaposition of 5-bit storage and >1-hour lifetime is misleading; if BER remains low, the concern is resolved. A complementary analysis: plot BER vs. refresh period from existing Supp. Fig. S8 and extrapolate to 3600 s.","verdict_should_be":"CONDITIONAL","load_bearing_attack":"The central claim implies a practical non-volatile multi-level optical memory. However, the reported metrics are not jointly achieved. 5-bit operation (Fig. 5d) used a read-write period T = 1 s; 4-bit also used T = 1 s. 3-bit at T = 100 s already has BER ~7.8% (Supp. Fig. S8). The long non-volatile lifetime τ = 4000 s (main text) and τ = 110000 s (Supp. Fig. S7) are measured as phase/transmission decay in the high-Z state, but the paper does not report multi-bit BER at times approaching 1 hour. Thus 'up to 5-bit phase storage' and 'non-volatility lifetimes >1 hour' are separate demonstrations; a 5-bit state held for 1 hour would almost certainly have unusable BER. Without simultaneous multi-bit retention, the device behaves as a volatile multi-level phase shifter with a binary non-volatile mode, not as the multi-level non-volatile memristor promised in the abstract. This is the load-bearing gap: the central claim of a practical optical memristor requires both properties at once.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper reports a micro-electromechanical (MEMS) cantilever-based photonic phase shifter that is presented as an optical memristor. The device is fabricated in a CMOS-compatible silicon nitride process, uses electrostatic and piezoelectric actuation, and stores phase by mechanical deformation / stiction, with no additional back-end materials. The authors demonstrate binary endurance of >1 billion cycles at 50 kHz, multi-level phase storage from 2 to 5 bits with Gray-coded BER values (0% for 2/3 bits, 3.1% for 4 bits, 5.9% for 5 bits), single-state non-volatile decay time constants of 4000 s (main device) and 110000 s (supplementary device), and a battery-powered refresh module that maintains binary states for 48 hours. The central claim is that this constitutes a practical multi-level, non-volatile photonic memristor. However, the paper reports multi-bit operation and long retention in separate measurements, and the multi-bit BER at extended retention times is not characterized.","tokens_in":16524,"tokens_out":5132,"duration_ms":48962,"significance":"If the headline metrics were simultaneously achieved, this would be a notable advance: a CMOS-foundry-compatible, low-loss, multi-level optical phase memory with high endurance and no power-consuming hold state is attractive for programmable photonics and optical in-memory computing. The paper is transparent in reporting BER, calibration tables, and an energy model, and it ships a tangible packaged prototype. The main significance is qualified by the fact that the multi-bit and long-retention demonstrations are not joint, and by the large device-to-device spread in the non-volatile lifetime. The work is nonetheless a useful experimental contribution to MEMS-based photonic memories, and the identified gaps are addressable in a revision.","major_comments":[{"comment":"The central claim of a multi-level non-volatile optical memristor requires simultaneous multi-bit fidelity and long retention. The 5-bit (Fig. 5d) and 4-bit (Fig. 5c) tests use a 1 s read-write period; 3-bit at T=10 s is error-free (Fig. 5b) but degrades to 7.8% BER at T=100 s (Supp Fig. S8). The long-lifetime measurements (Fig. 3d, Supp Fig. S7) are single-state phase decays in high-Z, not multi-bit BER at times approaching 1 hour. Thus \"up to 5-bit\" and \"non-volatility lifetimes >1 hour\" are separate demonstrations; a 5-bit state held for 1 hour would have unusable BER given the observed state spacing and τ=4000 s. To support the abstract, the authors must either report multi-bit BER at an extended retention time (e.g., >1 hour, or at least >1000 s for 5-bit) or explicitly scope the non-volatility claim to binary operation.","section":"§4, Fig. 5d, Supp Fig. S8"},{"comment":"The >1 billion cycle endurance claim is not quantified as a BER after the test. Fig. 4j shows a time trace \"after a >1 billion binary cycle endurance test\" with the text \"still operates at 0 bit errors,\" but no bit count or BER measurement is reported for that post-test trace. A \"0 error\" result without a defined number of transmitted bits is not a meaningful error rate. Additionally, all BER experiments appear to be single-device, single-shot measurements without repeated trials or error bars; the 3.1% and 5.9% BER values would need confidence intervals to be statistically robust. This is not a demand for exhaustive statistics but is necessary for the headline endurance and BER claims.","section":"§3, Fig. 4j"},{"comment":"The reproducibility of the non-volatile lifetime is not established. The main-text device has τ=4000 s, while a same-design device in Supp Fig. S7d has τ=110000 s, a 27x spread. The Discussion (Sec. 5) explicitly states \"Additional studies also are required to fully understand the nature of the stiction responsible for the long-lived memory lifetime,\" and Supp S2 says \"We will investigate the storage physics in more detail in a future study.\" Since the \"strain-assisted non-volatility\" is the core memristive mechanism, this admitted lack of physical understanding and the large device-to-device variation make the >1-hour non-volatility claim difficult to evaluate as a reproducible device property. The authors should provide statistics over multiple devices or temper the claim accordingly.","section":"§2, Supp Fig. S7, Sec. 5"},{"comment":"The energy-efficiency comparison uses a 1000 s refresh period for \"MEMS with non-volatility,\" but the multi-bit experiments require refresh periods of 1-10 s for acceptable BER (Fig. 5c-d, Supp Fig. S8); at 1000 s refresh, only binary operation is demonstrated (Fig. 4a-c). Consequently, the 12 pW average power quoted for the non-volatile MEMS in Table S3 does not represent multi-bit operation; at 1-10 s refresh the average power would be ~1.2-12 nW, reducing the claimed energy advantage. The analysis should state the bit depth associated with each refresh rate or use a refresh rate compatible with the claimed multi-bit operation.","section":"Supp S3, Table S3"}],"minor_comments":[{"comment":"In the text describing the T=40 µs experiment, \"The sampled states in Fig. 4e show good accuracy\" appears to be a typo; the relevant sampled-power panel for that experiment is Fig. 4h, not Fig. 4e.","section":"§3, Fig. 4e/4h"},{"comment":"The phrase \"non-volatility lifetimes >1 hour\" is ambiguous: τ=4000 s in the main text is a decay time constant, not a retention time at a specified fidelity. Please define \"lifetime\" explicitly (e.g., time to reach a given phase error or BER threshold).","section":"Abstract and Sec. 2"},{"comment":"\"van der Waal's forces\" should be \"van der Waals forces\" for correctness; the same appears in Supp S2.","section":"Sec. 5"},{"comment":"Fig. 4j appears to be a short trace without axis labels or a stated acquisition duration; adding scale bars and the number of post-endurance bits would help readers interpret the claim.","section":"Fig. 4"}],"recommendation":"major_revision","confidential_remarks":"The core experimental work is credible and well reported, but the manuscript's central claim—a practical multi-level, non-volatile optical memristor—is not fully supported because multi-bit operation and extended retention are demonstrated separately. The authors should either provide joint multi-bit BER at long retention times or reframe the contribution as a binary non-volatile MEMS phase switch with a multi-level volatile mode. The large τ spread also raises questions about process control; a multi-device study would strengthen the case. These are addressable with additional measurements or revised claims, so I recommend major revision rather than rejection."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Colleague,\n\nRead this before it hits press: the device is genuinely new, but the central 'non-volatile multi-level optical memristor' framing needs a hard look. What's actually demonstrated is a durable, multi-level programmable phase shifter with refresh times of seconds, plus a separate binary state that holds for an hour or more. Those are not the same thing.\n\nCredit where due: prior MEMS non-volatile photonic devices are binary latches; this group extends their piezo-optomechanical platform with electrostatic actuation and stiction-based retention to a multi-level MEMS memory. The endurance numbers are impressive — over 100 million bits at 25 kHz, then a >1 billion cycle run with no visible degradation. Error-free 2- and 3-bit operation with transparent error tables for 4/5-bit (3.1% and 5.9% BER) is solid, honest reporting. The battery-powered refresh module is a good system-level step.\n\nThe soft spots are real. The stress-test note is correct: 5-bit and 4-bit used a read-write period of T=1 s, and 3-bit already degrades to 7.8% BER at T=100 s (Supp Fig. S8). The '>1 hour lifetime' comes from exponential fits on two devices whose lifetimes differ 27-fold (tau = 4000 s main text vs 110000 s Supp Fig. S7). No multi-bit BER at times approaching an hour is reported anywhere. So the abstract's list of metrics is a menu, not a specification. Second, the stiction mechanism that gives non-volatility is admittedly poorly understood and may be process-dependent; the authors say so in the Discussion, which I respect, but it undercuts reproducibility. Third, single devices per test, no error bars, and the post-billion-cycle '0 error' claim lacks a bit count. The data are not public.\n\nThese are fixable with a revised narrative and a few targeted experiments, not with new physics. The core demonstration is credible, the engineering is thorough, and the authors themselves hint at the right framing when they say the ideal reconfiguration time is 10–100 s. I would send it to a serious referee, but the referee should demand: report multi-bit BER as a function of hold time, quantify the billion-cycle bit count, and separate the multi-level volatile mode from the binary non-volatile mode in the abstract and conclusion. If they do that, it's a useful contribution to reconfigurable photonics — not the optical storage breakthrough the current abstract implies.\n\nRecommendation: engage with it, but make the joint-metric question central to the revision.","headline":"A solid new MEMS photonic multi-level memory with real endurance, but the headline metrics (5-bit, >1 hour, >1B cycles) are not shown in one experiment; the abstract oversells the combination.","tokens_in":17049,"tokens_out":3056,"would_cite":true,"duration_ms":34893,"reading_group":"maybe","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"A foundry-fabricated MEMS cantilever acts as a multi-level optical memristor, storing up to 5 bits of optical phase that persists for over an hour without power and survives more than a billion write cycles.","keywords":["MEMS photonic memristor","silicon nitride waveguides","CMOS-compatible photonics","multi-level optical memory","non-volatile phase storage","stiction-based retention","electrostatic-piezoelectric actuation","in-memory optical computing"],"falsifier":"On a fresh batch of at least ten nominally identical cantilevers from multiple wafers, measure the high-impedance phase-retention lifetime under controlled temperature; if lifetimes still scatter between roughly 4,000 s and 110,000 s and the decay shows the non-exponential jumps seen in the supplementary data, then the '>1 hour' retention is a sample-dependent effect rather than a reliable device property.","tokens_in":16076,"feed_emoji":"💾","tokens_out":7048,"duration_ms":65235,"temperature":0.7,"pith_summary":"This paper aims to show that a mechanical cantilever in a standard CMOS photonics process can serve as a practical optical memristor — a device whose optical phase can be written electrically, held without power, and read out at the speed of light. The authors' central claim is that a voltage-pulled cantilever, held against the substrate by stiction, stores analog phase levels with up to 5-bit resolution, error-free binary operation through hundreds of millions of bits, and an endurance beyond one billion cycles. They further show that a simple battery-powered refresh circuit extends the memory to days. If correct, this replaces lossy, low-endurance material-based optical memories with a low-loss, foundry-compatible mechanism, moving programmable photonics closer to real optical storage and in-memory computing.","feed_headline":"MEMS cantilever stores 5-bit optical data, survives 1B cycles","feed_subtitle":"Foundry-made low-loss optical memristor holds phase without power for an hour; battery refresh stretches it to days.","key_machinery":"The central object is a singly clamped cantilever with meandering silicon-nitride waveguides, actuated by two independent voltage controls: electrostatic plates and a piezoelectric aluminum-nitride layer. Its job is to convert electrical programming pulses into a persistent mechanical deformation that shifts the optical phase. The state is held by a mixture of electrostatic charge retention and nonlinear mechanics — buckling and partial stiction to the substrate — often attributed to van der Waals adhesion. An integrated Mach-Zehnder interferometer turns the stored phase into an amplitude readout that can be decoded to bits, and a return-to-zero programming protocol improves multi-level fide","core_discovery":"On its own terms, the paper demonstrates that a MEMS phase shifter can be programmed like a memristor: applying an electrostatic voltage bends a singly clamped cantilever carrying meandering silicon-nitride waveguides until it contacts the substrate; switching the drive to high impedance removes power yet the flattened cantilever remains, locking the optical phase. The phase decays exponentially with a natural lifetime of about 4000 seconds in the main device, and a supplementary device shows a lifetime of about 110,000 seconds (roughly 30 hours). Using a return-to-zero protocol to suppress mechanical hysteresis, the authors report zero bit errors for binary pseudorandom sequences at 25 kHz","pith_inferences":["The 27x spread in retention lifetime between the main device (about 4000 s) and a nominally similar supplemental device (about 110,000 s) suggests the paper's '>1 hour' headline figure is not yet a controlled design parameter; a multi-wafer statistical study of stiction would be the direct test.","Because the 5-bit errors concentrate in states 25-28 near the high-voltage end of the calibration curve, redefining states to avoid the nonlinear actuation region — or using non-uniform state spacing — could plausibly yield error-free 5-bit storage without changing the device.","The battery-refresh module points toward an optical memory hierarchy: a fast, refresh-free tier for seconds-to-minutes storage alongside a refreshed tier for hours-to-days, which could be co-integrated with CMOS control electronics on the same chip.","If the stiction lifetime can be made reproducible and longer, the same cantilever becomes a true 'set-and-forget' non-volatile phase shifter, removing the need for refresh circuits in most photonic computing applications."],"forward_implications":["Binary optical memory runs with zero bit errors at up to 50 kbit/s, with no measurable degradation after more than one billion write-read cycles.","Multi-bit phase storage is error-free for 2-3 bits; 4-5 bit operation is possible with low (3-6%) bit error rates, and because errors are mostly single-state hops, standard error-correcting codes could push usable capacity higher.","The device can operate without power for minutes to hours, and a simple battery-driven refresh circuit extends this to days, enabling an optical random-access-memory style operation.","In the 10-100 second reconfiguration regime the memristor is competitive with or better than thermo-optic and phase-change approaches on average power, consuming roughly the energy of a once-per-day-reprogrammed phase-change device when refreshed every 1000 seconds.","With existing fabrication yield, scaling toward roughly one kilobit of optical storage is plausible, with the main limits being electronic I/O and packaging rather than the photonic mechanism itself."],"fun_headline_variants":["MEMS photonic memristor stores 5-bit phase, runs 1B cycles","Optical memristor on a chip: 5 bits, 50 kbit/s, no power for hours","Cantilever-based optical memristor holds phase >1 hour, 1B endurance","Photonic memristor: 5-bit phase, 1B cycles, battery-refresh to days","Foundry-made optical memristor stores phase for days with refresh"],"cache_read_input_tokens":2304,"weakest_assumption_plain":"The load-bearing premise is that the cantilever's strained contact with the substrate — held by stiction and said by the authors to be not yet fully understood — is stable enough to lock optical phase for the claimed minutes-to-hours with device-to-device reproducibility; the measured lifetime spreads from about 4000 s to about 110,000 s between devices, so if that adhesion is uncontrolled the non-volatility and multi-bit fidelity claims are not assured.","fun_headline_variants_meta":{"raw":{"variants":["MEMS photonic memristor stores 5-bit phase, runs 1B cycles","Optical memristor on a chip: 5 bits, 50 kbit/s, no power for hours","Cantilever-based optical memristor holds phase >1 hour, 1B endurance","Photonic memristor: 5-bit phase, 1B cycles, battery-refresh to days","Foundry-made optical memristor stores phase for days with refresh"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.001319,"raw_usage":{"total_tokens":5228,"prompt_tokens":782,"completion_tokens":4446,"prompt_tokens_details":{"cached_tokens":256},"prompt_cache_hit_tokens":256,"prompt_cache_miss_tokens":526,"completion_tokens_details":{"reasoning_tokens":4327}},"tokens_in":526,"tokens_out":4446,"duration_ms":28549,"temperature":1.0,"reasoning_tokens":4327,"cache_read_input_tokens":256,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-01T07:02:47.903478+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"On a fresh batch of at least ten nominally identical cantilevers from multiple wafers, measure the high-impedance phase-retention lifetime under controlled temperature; if lifetimes still scatter between roughly 4,000 s and 110,000 s and the decay shows the non-exponential jumps seen in the supplementary data, then the '>1 hour' retention is a sample-dependent effect rather than a reliable device property.","supporting_citations":[],"review_version":1}