{"id":"35bc932c-eaa0-4621-bd71-427d5b18d1bc","arxiv_id":"2607.29154","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":6.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":9,"one_line_summary":"At millikelvin temperatures, trap-rich SOI substrates give the highest superconducting-resonator quality factors; high-resistivity SOI suffers from parasitic sheet conduction at the buried-oxide interface.","lead":"Using superconducting microwave resonators at millikelvin temperatures, this paper compares how much microwave energy is lost on four silicon-on-insulator (SOI) substrate types. It finds that standard-resistivity SOI outperforms high-resistivity SOI, and that adding a trap-rich layer yields the best resonators, limited mainly by the buried oxide.","discovery_kind":"new_application","skeptic_critique":{"model":"deepseek-v4-flash","headline":"HR-SOI PSC attribution rests on unmeasured oxide charge density; if Qox is below ~1e10 cm^-2 on these wafers, the proposed PSC mechanism cannot explain the observed losses.","rationale":"The reader's weakest assumption identifies exactly the same load-bearing concern: the PSC attribution relies on simulated Qox values (1e10–1e12 cm^-2) rather than direct measurements of the wafers under test. I agree that this is the most important gap. The empirical ranking (trap-rich > standard > high-resistivity SOI at millikelvin temperatures) is directly supported by the resonance data and is robust, so the paper should not be rejected. However, the mechanism-level conclusion—that HR SOI losses are caused by PSC and that trap-rich SOI losses are limited only by SiO2 TLS—goes beyond the data in a falsifiable way. The paper honestly acknowledges unresolved mechanisms (e.g., the high-temperature downturn in trap-rich SOI, the empirical exp(-T/TX) law in Std SOI), but the central PSC attribution is not independently verified. A direct Qox measurement is the clearest way to settle it. The TiN uniformity concern is real but secondary: the 4% sheet-resistance uniformity and the distinct power/temperature signatures of HR SOI (frequency shift, bell shapes) make a pure TiN artifact less likely. Weighing all factors, the reader's CONDITIONAL verdict remains appropriate; no change is needed.","tokens_in":15448,"tokens_out":6268,"duration_ms":70697,"concrete_test":"Measure Qox at the BOX/Si interface on the same or sister SOI wafers used for the resonators using high-frequency capacitance-voltage (C-V) measurements on MOS capacitors after selectively removing the top Si layer, or use a contactless corona-Kelvin method. Alternatively, fabricate a four-point test structure contacting the Si handle and measure the PSC sheet resistance at 20 K and at 25 mK. If the extracted Qox is below ~1e10 cm^-2 for HR SOI (or the sheet resistance is >10^5 Ω/sq), the PSC model cannot explain the observed Qi ~10^3, and the mechanism assignment should be revised. If Qox is instead in the 1e10–1e11 cm^-2 range with a correspondingly low sheet resistance, the PSC attribution is supported and the central claim holds.","verdict_should_be":"UNCHANGED","load_bearing_attack":"The central mechanism claim—that losses in high-resistivity SOI are dominated by parasitic surface conduction (PSC) at the BOX/Si interface—depends on an unmeasured quantity, the oxide charge density Qox. In Sec. V.B the simulations (Fig. 4d) show a PSC threshold of ~1e10 cm^-2 for the HR SOI doping level. In Sec. V.C the authors match measured Qi values via electromagnetic simulations with a 1-µm conducting layer, inferring rho_eff ~10 kΩ·cm for HR SOI and mapping that back to Qox ~1e10 cm^-2. This is a fit using a 'typical' Qox range, not a measurement on the actual wafers. If the real Qox is below ~1e10 cm^-2, no inversion layer forms, the modeled PSC is absent, and the observed factor-of-20 degradation of HR SOI relative to trap-rich SOI would require a different explanation. The paper introduces DC test structures in Sec. II but reports no C-V, conductance, or Hall data that would constrain Qox or PSC sheet resistance. Because the novelty of the work lies in mechanism attribution ('Origins of microwave losses'), not just the empirical substrate ranking, this unmeasured parameter is load-bearing. The same issue affects the standard-SOI analysis: the threshold there is ~1e11 cm^-2, so a common Qox ~1e10 would give no PSC in Std SOI, consistent with their bulk-doping attribution, but a Qox ~1e11 would reintroduce PSC and weaken that attribution. A direct measurement of Qox on the actual wafers is needed to decide whether the PSC explanation is correct or whether another loss channel (e.g., interface traps, BOX loss, or TiN variation) is responsible.","agreement_with_reader":"agree"},"referee_report":{"model":"deepseek-v4-flash","summary":"The paper presents a comparative study of superconducting TiN microwave resonators fabricated on four substrates: high-resistivity bulk silicon, high-resistivity SOI, standard-resistivity SOI, and trap-rich SOI. At 25 mK the authors find that high-resistivity SOI performs worst (Qi ~10^3), standard SOI is intermediate, trap-rich SOI reaches Qi ~2–3×10^4 at the single-photon level, and HR bulk reaches ~2.5×10^5. They attribute the HR SOI degradation to a parasitic surface conduction (PSC) layer at the BOX/Si interface, the standard SOI limitation to residual bulk silicon dissipation, and the trap-rich SOI limitation to dielectric losses in the buried SiO2 layer. The support combines power and temperature dependence of Qi with 1D Poisson–Schrödinger simulations of PSC and electromagnetic simulations that map measured Qi to an effective PSC resistivity and then to an oxide charge density Qox.","tokens_in":15833,"tokens_out":3516,"duration_ms":45276,"significance":"If the mechanism attributions are correct, the work is significant for the integration of superconducting quantum circuits with SOI platforms: it overturns the default assumption that high-resistivity silicon is the best SOI choice, demonstrates a practical trap-rich alternative with Qi above 2×10^4, and identifies the BOX dielectric as the remaining loss channel. The empirical substrate ranking is well supported by the resonator measurements, and the paper includes several strengths: the same TiN process is used across all substrates, standard TLS and thermal-quasiparticle models are applied, the data are openly available, and the authors openly report where the TLS+QP model fails (trap-rich SOI above 250 mK). The main weakness is that the central mechanism attribution—particularly the PSC claim for HR SOI—rests on an inferred, not measured, oxide charge density Qox.","major_comments":[{"comment":"The attribution of HR SOI losses to parasitic surface conduction depends on an unmeasured Qox. The simulations show a PSC threshold near 10^10 cm^-2 for HR SOI, and the measured Qi is matched by EM simulations using a 1-µm conducting layer, giving rho_eff ≈ 10 kΩ·cm and then mapping to Qox ≈ 10^10 cm^-2. For standard SOI the inferred Qox would be ≈10^11 cm^-2. However, no C-V, conductance, or Hall measurement on the actual wafers is reported (Section II only describes TiN van der Pauw characterization). If the real Qox on the HR SOI wafer were below ~10^10 cm^-2, the modeled PSC would be absent and the factor-of-20 degradation relative to trap-rich SOI would require another explanation. A direct measurement of Qox (or at least an upper bound) on the four wafers is needed to make the PSC attribution load-bearing rather than a consistency argument.","section":"§V.B, §V.C, Fig. 4d"},{"comment":"The claim that trap-rich SOI is 'only limited by losses in the SiO2 layer' is not uniquely established. The Qi ≈ 23,000 value is estimated by electromagnetic simulation assuming tan δ_SiO2 ≈ 3×10^-4; no independent measurement of the BOX loss tangent or participation ratio is presented, and the same SiO2 BOX is not compared with a different thickness or geometry. Moreover, the temperature dependence in Fig. 3 shows an additional loss mechanism above 250 mK that the TLS+QP model fails to reproduce; the authors correctly flag this as unexplained and mention the poly-Si layer or top-Si resistivity as candidates. That unexplained channel could also contribute at base temperature. The text should either soften the exclusivity of the BOX-limited statement or provide additional experimental evidence (e.g., variable BOX thickness, or a direct loss-tangent measurement).","section":"§V.A, §V.C, Fig. 3"},{"comment":"The thermal-QP model fit for the HR bulk substrate yields Δ0/h = 95 GHz, whereas the BCS estimate from Tc is Δ0/h = 132 GHz—about 28% lower. The text calls this 'comparable', but the discrepancy is large enough to indicate either a systematic issue in the QP model (e.g., the assumed kinetic inductance fraction or thin-film gap reduction) or a temperature calibration offset. Since this fitted Δ0 is then used as a fixed input for the trap-rich SOI analysis, the uncertainty in Δ0 propagates into the conclusion that thermal QPs are negligible in trap-rich SOI. A sensitivity check varying Δ0 within the uncertainty of the Tc measurement would strengthen that argument.","section":"§IV, Eq. (4)"}],"minor_comments":[{"comment":"Typo: 'chararectization' should be 'characterization'. Also 'buried oxied' in the second paragraph should be 'buried oxide'.","section":"§II"},{"comment":"The top-silicon layer resistivity is listed as ≈10 Ω·cm for all SOI substrates, but the paper does not state the top-silicon thickness for the standard SOI sample in the text (only in Table I). A brief sentence in Section II would help.","section":"§I / Table I"},{"comment":"The fitting parameters for trap-rich SOI from the two datasets (Qc and Qc+) differ noticeably: Qi,sat = 19,000 vs 28,000 and β = 0.17 vs 0.27. The text notes the lower error bar for Qc+ but does not comment on whether the differences are statistically compatible. A short comment on the robustness of the TLS parameters would be useful.","section":"Fig. 2 and Table II"},{"comment":"The notation '⟨n⟩' in Eq. (3) is not defined; it should be identified as ⟨n_photon⟩ from Eq. (2). Also, the normalization of the TLS saturation term with tanh(ℏω/2kBT) is standard but its derivation is not given; citing a recent review would help readers.","section":"§III, Eq. (3)"},{"comment":"The gray dashed exponential fits for standard SOI and HR SOI at high power are not described with fit parameters in the text or caption. State TX values (the text gives TX ≈ 300 mK for standard SOI only) and the fitting range.","section":"§IV, Fig. 3"},{"comment":"The sentence 'We do not expect such large variation of the defect density between the two substrates' is an assumption that should be explicitly flagged. Without Qox measurements this is a conjecture, not a conclusion.","section":"§V.C"}],"recommendation":"major_revision","confidential_remarks":"The empirical comparison is valuable and likely correct in its ranking, but the paper's title and abstract promise mechanism attribution ('Origins of microwave losses'). That mechanism attribution currently rests on an unmeasured Qox and on simulations that are adjusted to match the data. I do not see this as a fatal flaw—the measurements are consistent with the proposed picture—but it is a load-bearing gap. The authors should either provide direct measurements of Qox (or equivalent interface characterization) on the actual wafers, or substantially soften the PSC claim for HR SOI and the BOX-limited claim for trap-rich SOI. The unexplained temperature-dependent loss in trap-rich SOI also needs more attention before the 'only limited by SiO2' statement can stand. I would encourage the editor to request a revision rather than reject, since the central empirical result is well supported."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Colleague, here's my read.\n\nThe empirical core is solid and worth knowing: trap-rich SOI gives Qi ~2.5e4 at single photon, about 20x better than high-resistivity SOI and 5x better than standard SOI. That ranking comes directly off the resonance fits and is robust. The paper is also honest—it says outright when its models fail, e.g. the TLS model can't capture the HR SOI power dependence, and the trap-rich temperature downturn above 250 mK is left unexplained.\n\nWhat's new: this is the first dedicated mK superconducting-resonator study of SOI loss mechanisms with single-photon Qi, and the differential experiment between HR SOI and trap-rich SOI is the strongest piece of evidence. Since those two substrates differ only by the trap-rich layer under the BOX, the 20x improvement points hard at interface free-carrier conduction in HR SOI. That is a good experiment.\n\nThe soft spots are mostly in the quantitative attribution. The PSC mechanism is inferred from 1D Poisson-Schrödinger simulations using Qox in a 'typical' range, 1e10–1e12 cm^-2, not measured on these wafers. Mapping Qi to rho_eff ~10 kOhm-cm and back to Qox ~1e10 is a fit, not a measurement. If the real Qox were below threshold, the model wouldn't explain the losses. But the differential data would still demand some interface-related mechanism, so the qualitative conclusion holds; only the specific Qox value is uncertain. Direct C-V or Hall measurements would settle it.\n\nMinor: no error bars for the Std and HR SOI Qi data, which are the very comparison the ranking rests on. Tc is reported for a full-sheet witness rather than per-device, so film uniformity across wafers is only checked via 4% sheet resistance. Neither is fatal.\n\nThe unexplained exp(-T/TX) behavior in standard SOI and the trap-rich downturn are honestly flagged as open questions; I don't hold that against them.\n\nWho should read this: anyone integrating superconducting circuits with SOI for NEMS or optomechanics. It gives a clear materials selection and a warning about HR SOI. It deserves a serious referee. I'd send it to review, asking for whatever constrains Qox—even one C-V measurement—and for error bars or device counts.\n\nRecommendation: send to peer review.","headline":"Solid empirical ranking of SOI substrates at mK; the PSC mechanism is plausible but rests on unmeasured oxide charge, so it deserves review but with a request for direct Qox constraints.","tokens_in":16489,"tokens_out":2852,"would_cite":true,"duration_ms":33098,"reading_group":"yes","serious_thinker":"yes","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"High-resistivity SOI substrates are the worst of three SOI variants for cryogenic superconducting resonators, because a parasitic conductive sheet forms at the buried-oxide interface and dominates microwave loss.","keywords":["silicon-on-insulator","superconducting resonators","microwave loss","two-level systems","parasitic surface conduction","trap-rich SOI","TiN","cryogenic temperatures"],"falsifier":"Measure the oxide charge density Qox on the same HR SOI and Std SOI wafers (e.g., by capacitance-voltage or Hall profiling) and compare with the simulation threshold; if Qox is below 10^10 cm^-2 on HR SOI, the PSC explanation fails. Also compare TiN critical temperature wafer-by-wafer to rule out film variation.","tokens_in":15280,"feed_emoji":"❄️","tokens_out":5151,"duration_ms":46773,"temperature":0.7,"pith_summary":"The paper claims that the standard assumption—use high-resistivity silicon to minimise microwave loss—fails for silicon-on-insulator (SOI) substrates at millikelvin temperatures. At cryogenic temperatures, a parasitic sheet conduction layer at the buried-oxide/silicon-handle interface makes high-resistivity SOI the worst performer (internal quality factors below 10^3), while standard-resistivity SOI is limited by residual doping. Adding a polycrystalline trap-rich layer under the buried oxide suppresses the parasitic sheet, yielding internal quality factors above 2×10^4 at the single-photon limit, limited only by dielectric losses in the silicon oxide. If correct, trap-rich SOI becomes a promising platform for superconducting electromechanical and microwave-to-optics devices, allowing the oxide to be kept under static parts.","feed_headline":"High-resistivity SOI is worst for cryogenic circuits; traps fix it","feed_subtitle":"A parasitic sheet at the buried-oxide interface dominates loss, but trap-rich substrates reach quality factors above 20,000.","key_machinery":"The central object is the parasitic surface conduction (PSC) layer: a thin, highly conductive sheet formed at the buried-oxide/silicon-handle interface by positive charge in the BOX that attracts mobile carriers. Its presence and magnitude are modeled with a 1D Poisson-Schrödinger solver, which yields a threshold oxide charge density (~10^10 cm^-2 for HR SOI and ~10^11 cm^-2 for Std SOI) below which the PSC disappears at 20 K. The paper uses this threshold to explain why HR SOI, despite its high bulk resistivity, suffers large low-temperature losses, and why intentionally introduced traps in trap-rich SOI suppress the PSC.","core_discovery":"The paper's central discovery is a counterintuitive substrate ranking and its mechanistic explanation. High-resistivity SOI substrates present the largest microwave losses of the three SOI variants studied, due to a parasitic surface conduction layer at the BOX/silicon interface that persists down to millikelvin temperatures. Standard-resistivity SOI performs better because dopant freeze-out suppresses bulk carrier loss, but it remains limited by residual substrate dissipation. Trap-rich SOI, with an engineered polycrystalline layer under the BOX, suppresses the parasitic sheet and reaches internal quality factors above 2×10^4 in the single-photon regime, with losses dominated by two-level s","pith_inferences":["The same PSC mechanism likely degrades other cryogenic devices on insulator-on-semiconductor stacks (e.g., lithium niobate on insulator); a trap-rich layer could be a generic mitigation.","If the oxide charge density in standard SOI could be reduced below its ~10^11 cm^-2 threshold, standard-resistivity SOI might approach trap-rich performance without an extra processing layer.","The unexplained temperature-activated loss in trap-rich SOI above 250 mK, with no corresponding frequency shift, may originate in the polycrystalline trap layer itself; probing its 1/f permittivity noise could identify it and enable further improvement.","Measuring oxide charge density on the actual wafers would convert the simulation threshold from an assumption into a measured parameter, directly testing the PSC explanation."],"forward_implications":["Trap-rich SOI can serve as a low-loss substrate for superconducting circuits at millikelvin temperatures, with Qi above 2×10^4 at the single-photon level, already compatible with electromechanical and microwave-to-optical transducers.","For high-resistivity SOI, the buried-oxide interface acts as a loss channel: PSC losses limit Qi to about 10^3, so designers should avoid or neutralize this interface.","Because losses in trap-rich SOI are dominated by the SiO2 layer, changing the resonator geometry to reduce the oxide participation ratio offers a direct path to higher quality factors.","The temperature and power signatures of PSC losses—bell-shaped Qi and anomalous frequency shifts—differ from TLS losses, giving experimental fingerprints to identify PSC in other devices.","Keeping the buried oxide under static regions, rather than releasing it everywhere, preserves mechanical integrity and improves heat evacuation for nanomechanical devices."],"fun_headline_variants":["Trap-rich SOI beats high-resistivity for superconducting qubits","Parasitic interface layer ruins high-resistivity SOI cryo circuits","Standard SOI outperforms high-resistivity at millikelvin","Engineered traps suppress microwave loss in SOI resonators","High-resistivity SOI loss traced to buried-oxide interface"],"cache_read_input_tokens":2304,"weakest_assumption_plain":"The assignment of HR SOI losses to parasitic sheet conduction rests on simulations that assume oxide charge densities of 10^10–10^12 cm^-2 at the BOX/silicon interface; the wafers' actual charge density is not measured, and if it fell below the ~10^10 cm^-2 threshold the proposed mechanism could not account for the factor-of-20 degradation relative to trap-rich SOI.","fun_headline_variants_meta":{"raw":{"variants":["Trap-rich SOI beats high-resistivity for superconducting qubits","Parasitic interface layer ruins high-resistivity SOI cryo circuits","Standard SOI outperforms high-resistivity at millikelvin","Engineered traps suppress microwave loss in SOI resonators","High-resistivity SOI loss traced to buried-oxide interface"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000615,"raw_usage":{"total_tokens":2709,"prompt_tokens":773,"completion_tokens":1936,"prompt_tokens_details":{"cached_tokens":256},"prompt_cache_hit_tokens":256,"prompt_cache_miss_tokens":517,"completion_tokens_details":{"reasoning_tokens":1844}},"tokens_in":517,"tokens_out":1936,"duration_ms":11887,"temperature":1.0,"reasoning_tokens":1844,"cache_read_input_tokens":256,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-03T12:35:10.685660+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Measure the oxide charge density Qox on the same HR SOI and Std SOI wafers (e.g., by capacitance-voltage or Hall profiling) and compare with the simulation threshold; if Qox is below 10^10 cm^-2 on HR SOI, the PSC explanation fails. Also compare TiN critical temperature wafer-by-wafer to rule out film variation.","supporting_citations":[],"review_version":1}