{"id":"8740bdd8-3c24-4694-883c-e952ce3eff69","arxiv_id":"2608.07963","paper_version":1,"verdict":"CONDITIONAL","confidence":"MODERATE","novelty_score":5.0,"correctness_risk":"medium","formal_verification":"none","parameter_count":0,"one_line_summary":"A discrete SiGe BJT transimpedance front-end plus two LTC6431 stages gives a preamplifier board with sub-femtocoulomb equivalent noise charge and tens-of-picoseconds timing for LGAD, PIN, and 3D silicon detectors.","lead":"This paper reports a new preamplifier board for reading out low-charge silicon detectors, with a gain of 115 mV·ns/fC and timing resolutions of 36 to 76 picoseconds depending on the sensor. It is a lab tool for characterizing LGAD and 3D sensors in 4D tracking R&D, where signals can be below one femtocoulomb.","discovery_kind":"new_method","skeptic_critique":{"model":"deepseek-v4-flash","headline":"3D detector timing result is internally inconsistent: reported 39.40 ps total resolution is smaller than the electronic jitter floor implied by the measured 594 MHz bandwidth and SNR of 6.46.","rationale":"The reader's weakest assumption (calibration pulse-shape dependence) is reasonable but affects absolute charge and ENC scales, not the timing resolution itself, which is the paper's headline performance metric for 4D tracking. A more serious problem appears in the 3D detector timing result: the reported 39.40 ps total resolution is logically incompatible with the quoted SNR, bandwidth, and jitter. Using the paper's own Eq. (3.4) with the bandwidth implied rise time gives jitter of ~91 ps; using the standard τ/SNR gives ~41.5 ps. Either way the jitter floor exceeds the fitted 39.40 ps sigma, even before adding the ~10 ps MCP-PMT reference. This points to an erroneous rise time assumption in the jitter estimate for the 3D test, and it invalidates a central headline number. The LGAD result (36.41 ps with jitter 10.9 ps) is consistent, and the PIN result (76.10 ps) is above its jitter floor, so the board may still be viable for LGAD and PIN readout; however, the claim that it achieves 39.40 ps with a 3D detector, and the associated suitability claim for 3D sensors, is unsupported. The fix is straightforward: the authors should recompute jitter using the amplifier-limited rise time and re-fit the timing distribution, or remove the 3D timing claim. This is a conditional acceptance with mandatory revision situation, matching the reader's CONDITIONAL verdict and therefore leaving the verdict unchanged.","tokens_in":10527,"tokens_out":13237,"duration_ms":132299,"concrete_test":"Recompute the 3D electronic jitter from the measured bandwidth: σ_jitter = τ/SNR with τ = 1/(2π·594.3 MHz) ≈ 268 ps and SNR = 72.66/11.24 ≈ 6.46, giving ≈ 41.5 ps. If this value exceeds the reported total resolution of 39.40 ps (after subtracting the MCP-PMT reference in quadrature, the DUT-only value is ~38 ps, even worse), the 3D timing result is unphysical. Independently, measure the 10–90% rise time of the recorded 3D output pulses; if it is ~590 ps (as the bandwidth implies), the paper's quoted 31.1 ps jitter cannot be correct.","verdict_should_be":"UNCHANGED","load_bearing_attack":"Section 3.2.3 reports a 3D detector timing resolution of 39.40 ps alongside amplitude MPV = 72.66 mV and RMS noise = 11.24 mV, giving SNR = 6.46 and an electronic jitter estimate of 31.1 ps via Eq. (3.4). That jitter value implies an assumed signal rise time t_r ≈ 31.1 × 6.46 ≈ 201 ps. But Section 3.1.2 measures the -3 dB bandwidth as 594.3 MHz; for a single-pole system this gives τ = 1/(2π·594.3 MHz) ≈ 268 ps and a 10–90% rise time of ~2.2τ ≈ 590 ps. The paper's own formula then gives σ_jitter = t_r/SNR ≈ 590/6.46 ≈ 91 ps, and the standard τ/SNR gives ≈ 41.5 ps. Both exceed the reported 39.40 ps total, and adding the ~10 ps MCP-PMT reference only worsens the contradiction. A total timing resolution cannot be smaller than its jitter component, so the 3D result is internally inconsistent. The likely source is using a detector rise time (~200 ps) instead of the amplifier-limited output rise time in Eq. (3.4). The same inconsistency does not affect the LGAD numbers (jitter 10.9 ps, SNR 63.38, implying t_r ≈ 691 ps, consistent with the bandwidth) and is less acute for the PIN result (total 76.10 ps > jitter floor). This is a more direct threat than the calibration pulse-shape concern, because it targets a headline timing value rather than the absolute charge scale.","agreement_with_reader":"partial"},"referee_report":{"model":"deepseek-v4-flash","summary":"This manuscript presents the design and characterization of a three-stage discrete preamplifier board intended for low-charge semiconductor detectors (LGAD, PIN, and 3D silicon sensors). The board is reported to achieve a charge gain of 115.27 mV·ns/fC over an injected-charge range of 0.5–25 fC, a -3 dB bandwidth from 34.0 MHz to 594.3 MHz, and timing resolutions of 36.41 ps, 76.10 ps, and 39.40 ps with ENC values of 0.18 fC, 0.11 fC, and 0.09 fC for the three detector types, respectively. A six-channel variant is also described and tested for gain uniformity and crosstalk. The central claims are that the board is suitable for laboratory-based 4D tracking detector characterization and that it significantly outperforms the authors' previous USTC-V1 reference design.","tokens_in":10808,"tokens_out":7923,"duration_ms":74031,"significance":"The board fills a practical niche: a discrete, high-bandwidth, low-noise readout that can be coupled to both gain-enhanced and non-gain detectors, with a documented dynamic range and a multi-channel extension. The paper's strengths include a concrete circuit architecture, direct measurements of gain, linearity, and bandwidth, a comparison against an existing USTC-V1 design, and crosstalk checks on the multi-channel board. If the timing and ENC numbers survive reanalysis, this would be a useful reference for laboratory 4D tracking characterization and a stepping stone toward a dedicated ASIC. However, the 3D timing result currently appears internally inconsistent with the reported bandwidth and SNR, and the unquantified pulse-shape dependence of the calibration affects the absolute charge scale, so the quantitative headline claims are not yet established.","major_comments":[{"comment":"The 3D detector timing result is internally inconsistent. With an RMS noise of 11.24 mV, an amplitude MPV of 72.66 mV, and SNR = 6.46, the reported total timing resolution of 39.40 ps cannot be smaller than the electronic jitter component. Using the measured -3 dB bandwidth of 594.3 MHz gives a single-pole time constant τ = 1/(2π·594.3 MHz) ≈ 0.268 ns; Eq. (3.4) then yields an electronic jitter of about 41 ps if one uses τ/SNR, or about 91 ps if one uses the 10–90% output rise time (0.59 ns) in the same formula. The quoted jitter of 31.1 ps implies t_r ≈ 0.20 ns, which is the detector rise time rather than the amplifier-limited output rise time. This claim must be reanalyzed, ideally with a direct measurement of the output rise time and jitter, before the 3D timing result can be accepted.","section":"§3.2.3 and Eq. (3.4)"},{"comment":"The charge calibration is explicitly admitted in Section 2.2.2 to depend on the injected pulse shape, but no uncertainty or cross-check is provided. Because the ENC is computed as Q_MPV/SNR and Q_MPV is derived from the calibrated charge gain, a pulse-shape mismatch changes all ENC values and the comparison with USTC-V1 by a common systematic factor. Please quantify this sensitivity, for example by measuring the gain with different pulse rise times or against a known detector current source, or explicitly state the resulting limitation on the absolute charge scale.","section":"§2.2.2 and Eq. (3.1)"},{"comment":"For the PIN measurement, the feedback resistor of the preamplifier stage was changed to 1.13 kΩ, whereas the quoted charge gain of 115.27 mV·ns/fC was measured with the 1.3 kΩ resistor described in Section 2.1. No recalibration of the charge gain for the 1.13 kΩ configuration is reported. Since reducing R_f from 1.3 kΩ to 1.13 kΩ lowers the transimpedance gain by about 13%, the PIN collected charge and ENC values may be on a different absolute scale; please clarify the resistor change and provide the corresponding calibration.","section":"§3.2.2 vs §2.1"},{"comment":"The headline timing resolutions are quoted to two decimal places without systematic uncertainties, and the MCP-PMT reference contribution is mentioned but never subtracted in quadrature. Please report error bars and the quadrature formula used to separate the detector, electronics, and reference contributions, especially since the 3D jitter estimate is intended to be compared with the total resolution.","section":"§3.2"}],"minor_comments":[{"comment":"The abstract states a PIN ENC of 0.10 fC, while Section 3.2.2 reports 0.11 fC; please reconcile these values.","section":"Abstract and §3.2.2"},{"comment":"The figure reports 'INL: 0.011' while the text states a maximum INL of 1.10%; please clarify whether this is a fractional value or a percentage.","section":"Fig. 5"},{"comment":"Equation (3.4) uses t_r without defining how it was measured or estimated; please define t_r and state the value used for each detector.","section":"Eq. (3.4)"},{"comment":"The text alternates between 'combined time resolution' and 'detector timing resolution' without an explicit formula; please define these quantities and how the reference contribution is removed.","section":"§3.2"},{"comment":"The crosstalk test states that 'no detectable signal' was observed, but no quantitative limit is given; please provide a numerical bound relative to the baseline noise.","section":"§3.3"},{"comment":"There are minor typographical issues, including 'Ampitude' in figure axis labels and inconsistent use of units (mV·ns/fC vs mV ns/fC); these could be cleaned up in revision.","section":"Throughout"}],"recommendation":"major_revision","confidential_remarks":"The bandwidth-versus-jitter inconsistency for the 3D result is real and should be the first issue addressed in revision; I would not reject because the board design and most measurements are plausible, but the 3D timing claim may need to be withdrawn or substantially requalified if the data cannot support it. The PIN feedback-resistor change also needs clarification, and the calibration pulse-shape dependence should be quantified before the ENC values are presented as absolute."},"author_rebuttal":null,"desk_editor":{"model":"deepseek-v4-flash","letter":"Colleague,\n\nTwo things you should know about this paper. First, it's a genuine engineering contribution: a discrete SiGe TIA front-end plus two LTC6431 gain stages that reads out sub-femtocoulomb charges from LGAD, PIN, and 3D detectors, with a six-channel version and crosstalk checks. Second, the headline 3D timing result—39.40 ps total resolution with SNR 6.46 and 594 MHz bandwidth—is internally inconsistent and should not be believed as reported.\n\nWhat's new and good: the board achieves 115.27 mV·ns/fC with good linearity from 0.5–25 fC, and the measured time resolution of 36.41 ps with LGAD and 76.10 ps with PIN are plausible and useful for lab-based 4D tracking R&D. The multi-channel gain uniformity and crosstalk tests are well done. The paper is clearly written and the measurements are described in enough detail to reproduce.\n\nSoft spots, in proportion:\n\n- The 3D jitter/timing inconsistency is the big one. Using their own Eq. (3.4) with the measured SNR of 6.46 and a 594.3 MHz single-pole bandwidth, the electronic jitter is ~91 ps (or ~41 ps using τ/SNR), both larger than the reported total of 39.40 ps. Their 31.1 ps jitter estimate implies a ~201 ps rise time, which conflicts with the measured bandwidth. Either the bandwidth is misreported, the jitter formula is misapplied, or the timing fit is wrong. This needs to be fixed before the 3D result can be used.\n\n- No error bars on the headline numbers (36.41 ps, 76.10 ps, 39.40 ps, all ENC values). For a paper making sub-100 ps claims, this is a significant omission.\n\n- Calibration pulse-shape dependence is admitted in Section 2.2.2. A systematic bias in the charge calibration would shift ENC and charge values. The authors note it but don't quantify it.\n\n- The comparison to USTC-V1 is only to their own prior board. That's fine as a baseline, but \"significantly outperforming previous reference designs\" is overclaimed when the reference is self-referential.\n\nBottom line: this is a useful board and the LGAD/PIN results are credible. The 3D timing number needs a careful re-analysis. I'd send it to review—an expert referee will catch the inconsistency and the authors can fix it. Recommended: conditional accept with mandatory revision, or at least a thorough referee report.","headline":"A genuinely useful low-charge preamplifier board, but the headline 3D timing result is internally inconsistent and needs to be revisited before the paper is used as a reference.","tokens_in":11419,"tokens_out":3036,"would_cite":true,"duration_ms":29824,"reading_group":"maybe","serious_thinker":"no","would_accept_peer_review":true},"rs_alignment":null,"lean_confirmation":null,"pith_extraction":{"msc":[],"pacs":[],"model":"deepseek-v4-flash","headline":"A three-stage transimpedance preamplifier board achieves 115.27 mV·ns/fC charge gain and sub-100 ps timing with LGAD, PIN, and 3D silicon detectors, down to 0.09 fC equivalent noise charge.","keywords":["front-end electronics for detector readout","low-gain avalanche detectors","3D silicon detectors","transimpedance amplifier","timing resolution","equivalent noise charge","4D tracking","charge gain"],"falsifier":"Inject calibrated test pulses with different rise times (e.g., 200 ps versus 1 ns) through the 1 pF injection port and compare the output pulse integral; if the derived charge gain shifts by more than the stated 1.1% integral nonlinearity, the reported ENC values for LGAD, PIN, and 3D detectors would move accordingly.","tokens_in":1626,"feed_emoji":"⚡","tokens_out":1574,"duration_ms":85197,"temperature":0.7,"pith_summary":"This paper reports a laboratory front-end preamplifier board that can read out the very small charge signals from LGAD, PIN, and 3D silicon detectors with one circuit design. The board reaches a charge gain of 115.27 mV·ns/fC, stays linear from 0.5 fC to 25 fC, and has a -3 dB bandwidth of 34.0 MHz to 594.3 MHz. Coupled to detectors under a 90Sr beta source, it achieves time resolutions of 36.41 ps with an LGAD, 76.10 ps with a PIN diode, and 39.40 ps with a 3D detector, with equivalent noise charges of 0.18 fC, 0.11 fC, and 0.09 fC. The significance is that existing discrete readout boards do not work reliably below about 1 fC, so this design provides a practical bench tool for characterizing 4D tracking sensors and a starting point for an ASIC.","feed_headline":"Readout board hits 36 ps timing at charges below 1 fC","feed_subtitle":"Three-stage TIA preamp delivers high gain and low noise for 4D tracking detectors in the lab.","key_machinery":"The load-bearing element is the three-stage amplifier chain. Stage one is a transimpedance amplifier (TIA) with a 1.3 kΩ feedback resistor built around a discrete BFP840FESD SiGe:C NPN transistor with 85 GHz transition frequency; the TIA converts the detector current to a voltage and preserves pulse shape. Stages two and three are resistive-feedback amplifiers using LTC6431 chips (20.8 dB gain, 2 GHz bandwidth) that raise the voltage to an easily measured level. The bandwidth target comes from the TIA relation $f_{-3\\,\\mathrm{dB}} = \\sqrt{\\mathrm{GBWP} / (2\\pi R_f C_\\mathrm{in})}$, and the discrete transistor is what allows a larger $R_f$ than a commercial amplifier could sustain at the same bandwidth. Low-noise regulators, a shielding enclosure, and a calibration port with a 1 pF injection capacitor complete the design.","core_discovery":"The central claim is that a three-stage transimpedance preamplifier, using a discrete SiGe:C bipolar transistor front-end followed by two LTC6431 gain stages, provides enough gain and bandwidth to resolve charges from a few tenths of a femtocoulomb up to 25 fC without changing the detector technology. This makes the board the first discrete readout in the comparison set to give usable signals below 1 fC: the PIN and 3D tests produced sub-femtocoulomb collected charges (0.61 fC and 0.58 fC most probable values) at usable signal-to-noise ratios, while the reference USTC-V1 board could not reliably discriminate such signals. The paper also reports a six-channel version of the same architecture with mean charge gain 115.90 mV·ns/fC, channel-to-channel spread 1.66 mV·ns/fC, and no measurable inter-channel crosstalk in calibration or laser-spot tests.","pith_inferences":["If the calibration-shape dependence is corrected in a future iteration, the reported ENC numbers may move; a detector-like current source with a sub-200 ps rise time would make the charge-gain calibration directly traceable to real signals.","The discrete TIA design could be pushed to even lower charges by raising the feedback resistor or using a faster input transistor, at the cost of bandwidth, with the bandwidth-gain trade-off in Equation (2.1) giving a quantitative path.","A similar topology with active baseline restoration could extend the board from laboratory characterization toward the higher-rate environment of future collider experiments.","The observed 3D-detector timing tail, attributed to non-uniform electric field, suggests that combining this readout with detailed sensor simulations could separate electronics jitter from sensor effects."],"forward_implications":["The same board can characterize LGAD, PIN, and 3D detectors without modification, so a single lab setup covers the main fast-timing sensor technologies.","Sub-femtocoulomb charges (0.58 fC from the 3D detector) are measurable with an equivalent noise charge around 0.09 fC, opening laboratory testing of small-pitch 3D sensors that previous discrete designs could not read out.","With the six-channel variant, a multi-pad detector array can be read out for position-sensitive measurements, since gain uniformity is at the percent level and crosstalk was not observed.","The measurements identify electronic jitter as the dominant timing contribution below 1 fC, telling future ASIC designers where to spend noise budget.","Baseline shift from the AC-coupled chain will require active baseline correction for high-rate operation, though it did not affect these low-rate tests."],"supporting_citations":[{"why":"Supplies the transimpedance-amplifier bandwidth formula used to choose the front-end topology and feedback resistor.","marker":"[17]"},{"why":"Datasheet for the BFP840FESD SiGe:C transistor with 85 GHz transition frequency, enabling the 1.3 kΩ feedback resistor.","marker":"[18]"},{"why":"Describes the USTC-fabricated LGAD sensor used for the timing and SNR measurements.","marker":"[20]"},{"why":"MCP-PMT used as the timing reference detector with about 10 ps resolution.","marker":"[21]"},{"why":"Describes the USTC-V1 reference preamplifier board that serves as the comparison baseline in the LGAD and PIN tests.","marker":"[22]"},{"why":"Provides the jitter formula used to extract electronic jitter from SNR and rise time.","marker":"[24]"},{"why":"Describes the USTC 3D silicon sensor with 25 µm pixel size and 50 µm active thickness used in the 3D detector test.","marker":"[25]"}],"fun_headline_variants":["36 ps timing from sub-femtocoulomb charges","Sub-fC signals resolved: 36 ps timing","Preamplifier delivers 36 ps from sub-fC signals","Discrete preamp resolves sub-femtocoulomb charges"],"cache_read_input_tokens":13440,"weakest_assumption_plain":"The reported charge gain and noise figures assume the test pulse injected through the 1 pF calibration capacitor reproduces the shape of a real detector's current pulse; the paper itself notes the gain still depends on pulse shape.","fun_headline_variants_meta":{"raw":{"variants":["36 ps timing from sub-femtocoulomb charges","Sub-fC signals resolved: 36 ps timing","Preamplifier delivers 36 ps from sub-fC signals","Discrete preamp resolves sub-femtocoulomb charges"]},"model":"deepseek-v4-flash","effort":"low","cost_usd":0.000911,"raw_usage":{"total_tokens":3962,"prompt_tokens":1040,"completion_tokens":2922,"prompt_tokens_details":{"cached_tokens":384},"prompt_cache_hit_tokens":384,"prompt_cache_miss_tokens":656,"completion_tokens_details":{"reasoning_tokens":2855}},"tokens_in":656,"tokens_out":2922,"duration_ms":27100,"temperature":1.0,"reasoning_tokens":2855,"cache_read_input_tokens":384,"cache_creation_input_tokens":0},"cache_creation_input_tokens":0},"created_at":"2026-08-12T00:36:15.199619+00:00","model_set":{"reader":"deepseek-v4-flash"},"falsifier":"Inject calibrated test pulses with different rise times (e.g., 200 ps versus 1 ns) through the 1 pF injection port and compare the output pulse integral; if the derived charge gain shifts by more than the stated 1.1% integral nonlinearity, the reported ENC values for LGAD, PIN, and 3D detectors would move accordingly.","supporting_citations":[{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Supplies the transimpedance-amplifier bandwidth formula used to choose the front-end topology and feedback resistor."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Datasheet for the BFP840FESD SiGe:C transistor with 85 GHz transition frequency, enabling the 1.3 kΩ feedback resistor."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Describes the USTC-fabricated LGAD sensor used for the timing and SNR measurements."},{"cited_title":"Bortfeldt, F","cited_arxiv_id":null,"evidence_quote":"MCP-PMT used as the timing reference detector with about 10 ps resolution."},{"cited_title":null,"cited_arxiv_id":null,"evidence_quote":"Describes the USTC-V1 reference preamplifier board that serves as the comparison baseline in the LGAD and PIN tests."},{"cited_title":"Jadhav, W","cited_arxiv_id":null,"evidence_quote":"Provides the jitter formula used to extract electronic jitter from SNR and rise time."},{"cited_title":"Development of Small-pitch, Ultra-thin 3D Silicon Sensors at USTC","cited_arxiv_id":"2605.13281","evidence_quote":"Describes the USTC 3D silicon sensor with 25 µm pixel size and 50 µm active thickness used in the 3D detector test."}],"review_version":1}