{"total":11,"items":[{"citing_arxiv_id":"2605.21960","ref_index":16,"ref_count":1,"confidence":0.9,"is_internal_anchor":false,"paper_title":"dSABRE: A SABRE-Style Router for Multi-Core Distributed Quantum Computers","primary_cat":"quant-ph","submitted_at":"2026-05-21T03:47:25+00:00","verdict":"ACCEPT","verdict_confidence":"MODERATE","novelty_score":6.0,"formal_verification":"none","one_line_summary":"dSABRE cuts geometric-mean EPR consumption by 41-44% versus TeleSABRE on 18 benchmark circuits through intra-core priority, a five-term teleportation scorer with capacity penalty, proactive congestion relief, and BFS-layer extended sets.","context_count":0,"top_context_role":null,"top_context_polarity":null,"context_text":null},{"citing_arxiv_id":"2605.21662","ref_index":45,"ref_count":1,"confidence":0.9,"is_internal_anchor":false,"paper_title":"Fidelity-Aware Frequency Allocation and Transpilation Co-Design for Tunable Coupler Quantum Systems","primary_cat":"quant-ph","submitted_at":"2026-05-20T19:13:50+00:00","verdict":"UNVERDICTED","verdict_confidence":"LOW","novelty_score":6.0,"formal_verification":"none","one_line_summary":"A co-design method for frequency allocation and noise-aware transpilation in tunable-coupler quantum systems yields 8.9% lower log-infidelity cost and 6.8% shorter circuits than SABRE on SNAIL architectures.","context_count":0,"top_context_role":null,"top_context_polarity":null,"context_text":null},{"citing_arxiv_id":"2605.13638","ref_index":42,"ref_count":1,"confidence":0.9,"is_internal_anchor":false,"paper_title":"CO-MAP: A Reinforcement Learning Approach to the Qubit Allocation Problem","primary_cat":"quant-ph","submitted_at":"2026-05-13T15:04:09+00:00","verdict":"UNVERDICTED","verdict_confidence":"LOW","novelty_score":6.0,"formal_verification":"none","one_line_summary":"Reinforcement learning policy for qubit mapping reduces SWAP overhead by 65-85% versus standard quantum compilers on MQTBench and Queko benchmark circuits.","context_count":0,"top_context_role":null,"top_context_polarity":null,"context_text":null},{"citing_arxiv_id":"2605.12365","ref_index":76,"ref_count":1,"confidence":0.9,"is_internal_anchor":false,"paper_title":"QAP-Router: Tackling Qubit Routing as Dynamic Quadratic Assignment with Reinforcement Learning","primary_cat":"quant-ph","submitted_at":"2026-05-12T16:34:01+00:00","verdict":"UNVERDICTED","verdict_confidence":"LOW","novelty_score":7.0,"formal_verification":"none","one_line_summary":"QAP-Router models qubit routing as dynamic QAP and applies RL with a solution-aware Transformer to cut CNOT counts by 12-30% versus industry compilers on real circuit benchmarks.","context_count":1,"top_context_role":"background","top_context_polarity":"background","context_text":"quantum compilation[ 42, 71]. This process contains two phases: (i) circuit synthesis and optimization, and (ii) qubit mapping and routing (Figure 1). In the first phase, a high-level quantum algorithm is translated into a gate-level circuit over the native instruction set of the target hardware, while compiler optimizations reduce depth and gate count [76, 36, 61, 31]. In the second phase, the logical circuit is compiled to the device constraints; qubit mapping creates an initial logical-to-physical Preprint. arXiv:2605.12365v1 [quant-ph] 12 May 2026 Logical Circuit Synthesis Logical Circuit Optimization Qubit Mapping Qubit Routing Quantum Algorithm Logical Circuit Executable Program Physical Quantum Device"},{"citing_arxiv_id":"2605.11500","ref_index":16,"ref_count":1,"confidence":0.9,"is_internal_anchor":false,"paper_title":"Digital Annealer-Assisted Accuracy-First Quantum Circuit Transpilation with Integrated QUBO Mapping and Routing","primary_cat":"quant-ph","submitted_at":"2026-05-12T04:19:51+00:00","verdict":"UNVERDICTED","verdict_confidence":"LOW","novelty_score":6.0,"formal_verification":"none","one_line_summary":"Digital Annealer-assisted transpilation reduces CNOT counts by 13.7% on average (up to 57.4%) versus Qiskit on structured circuits, with a full-DA variant outperforming ISAAQ by 23.1%.","context_count":0,"top_context_role":null,"top_context_polarity":null,"context_text":null},{"citing_arxiv_id":"2605.09237","ref_index":17,"ref_count":1,"confidence":0.9,"is_internal_anchor":false,"paper_title":"Scaling Qubit Mapping and Routing With Position Graph Abstraction and Memoization","primary_cat":"quant-ph","submitted_at":"2026-05-10T00:35:23+00:00","verdict":"UNVERDICTED","verdict_confidence":"LOW","novelty_score":6.0,"formal_verification":"none","one_line_summary":"Position graph abstraction with memoized SABRE heuristics scales qubit mapping and routing for TI-QCCD architectures by caching repeated evaluations without altering decisions.","context_count":1,"top_context_role":"baseline","top_context_polarity":"baseline","context_text":"It maintains a front layer of executable gates and an extended lookahead layer, and iteratively inserts SW APs according to a heuristic that balances immediate and future routing costs; the same procedure can also be applied bidirection- ally to obtain improved initial layouts. Recently, PAM [16] extended this framework by combining block-based routing with permutation-aware synthesis, while LightSABRE [17] improved robustness, scalability, and routing quality on larger circuits. In trapped-ion and especially QCCD architectures, however, heuristic methods must reason not only about logical remap- ping but also about physical ion transport. Early work there- fore emphasized shuttle-aware initial placement and multi- trap compilation, including shuttle-efficient mapping policies"},{"citing_arxiv_id":"2604.24422","ref_index":14,"ref_count":1,"confidence":0.9,"is_internal_anchor":false,"paper_title":"Noise-aware selection of circuit cutting strategies under hardware noise non-uniformity","primary_cat":"quant-ph","submitted_at":"2026-04-27T12:50:49+00:00","verdict":"UNVERDICTED","verdict_confidence":"LOW","novelty_score":6.0,"formal_verification":"none","one_line_summary":"Noise-aware selection of circuit cutting strategies reduces execution overhead by 5-54x for 20-qubit circuits and makes 50-qubit circuit cutting feasible on non-uniformly noisy hardware.","context_count":0,"top_context_role":null,"top_context_polarity":null,"context_text":null},{"citing_arxiv_id":"2604.19341","ref_index":177,"ref_count":1,"confidence":0.9,"is_internal_anchor":false,"paper_title":"Evaluation-driven Scaling for Scientific Discovery","primary_cat":"cs.LG","submitted_at":"2026-04-21T11:24:09+00:00","verdict":"UNVERDICTED","verdict_confidence":"LOW","novelty_score":6.0,"formal_verification":"none","one_line_summary":"SimpleTES scales test-time evaluation in LLMs to discover state-of-the-art solutions on 21 scientific problems across six domains, outperforming frontier models and optimization pipelines with examples like 2x faster LASSO and new Erdos constructions.","context_count":0,"top_context_role":null,"top_context_polarity":null,"context_text":null},{"citing_arxiv_id":"2604.13812","ref_index":46,"ref_count":1,"confidence":0.9,"is_internal_anchor":false,"paper_title":"AlphaCNOT: Learning CNOT Minimization with Model-Based Planning","primary_cat":"cs.AI","submitted_at":"2026-04-15T12:46:40+00:00","verdict":"UNVERDICTED","verdict_confidence":"LOW","novelty_score":6.0,"formal_verification":"none","one_line_summary":"AlphaCNOT combines reinforcement learning with Monte Carlo Tree Search planning to reduce CNOT gate counts by up to 32% versus heuristics in quantum circuit synthesis.","context_count":0,"top_context_role":null,"top_context_polarity":null,"context_text":null},{"citing_arxiv_id":"2511.04608","ref_index":74,"ref_count":1,"confidence":0.9,"is_internal_anchor":false,"paper_title":"Unifying Qubit Routing Across Diverse Quantum ISAs via Canonical Representation","primary_cat":"quant-ph","submitted_at":"2025-11-06T17:58:53+00:00","verdict":"CONDITIONAL","verdict_confidence":"MODERATE","novelty_score":6.0,"formal_verification":"none","one_line_summary":"Canopus unifies qubit mapping and routing across quantum ISAs by modeling synthesis costs via canonical two-qubit gate forms, achieving 15-35% lower routing overhead than prior methods on varied backends and topologies.","context_count":0,"top_context_role":null,"top_context_polarity":null,"context_text":null},{"citing_arxiv_id":"2505.08928","ref_index":18,"ref_count":1,"confidence":0.9,"is_internal_anchor":false,"paper_title":"TeleSABRE: Layout Synthesis in Multi-Core Quantum Systems with Teleport Interconnect","primary_cat":"quant-ph","submitted_at":"2025-05-13T19:53:04+00:00","verdict":"UNVERDICTED","verdict_confidence":"LOW","novelty_score":6.0,"formal_verification":"none","one_line_summary":"TeleSABRE extends SABRE to combine intra-core SWAPs with inter-core teleportation, reporting a 28% reduction in inter-core operations on benchmarks for multi-core quantum architectures.","context_count":0,"top_context_role":null,"top_context_polarity":null,"context_text":null}],"limit":50,"offset":0}