{"as_of":"2026-08-10T04:47:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:d4b28d70d281cbb0b342987d43b25bc0600f07492eb3ac77f2dc87806237cabe","coverage":[{"denominator":0,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":9,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":9,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-09T06:31:02.800959+00:00","state":"measured"},{"denominator":9,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":9,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-06T17:13:37.885136Z","state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"arxiv_reference","source_observed_at":"2026-07-01T08:15:32.456749Z","state":"measured"}],"external_citation_measurements":[],"inbound":[{"citation":{"cited_paper":{"arxiv_id":"1912.03413","last_updated":"2019-12-07T02:10:19Z","snapshot_observed_at":"2026-08-07T06:17:34.662980Z","submitted_at":"2019-12-07T02:10:19Z","title":"Dissecting the Graphcore IPU Architecture via Microbenchmarking","version":1},"cited_work":{"arxiv_id":"1912.03413","doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":"1912.03413","snapshot_observed_at":"2026-07-01T08:15:32.456749Z","title":"Dissecting the graphcore IPU architecture via microbenchmarking.arXiv preprint","venue":null,"work_id":"e9b2797c-1af7-40f8-a143-51ab3dfbad6b","year":2019},"citing_paper":{"arxiv_id":"2205.14135","last_updated":"2022-06-23T17:53:32Z","snapshot_observed_at":"2026-07-06T13:14:48.753329Z","submitted_at":"2022-05-27T17:53:09Z","title":"FlashAttention: Fast and Memory-Efficient Exact Attention with IO-Awareness","version":2},"reference_index":46,"source":"pdf_text","source_observed_at":"2026-05-12T16:22:08.801066Z"},"links":{"cited_paper":"/paper/1912.03413","citing_paper":"/paper/2205.14135"},"observation_digest":"sha256:359e769b4e491f44b23c2cefa932894c61d350bb0fbc00cee9b498dfed44a1d1","observation_id":"cd75282c-32b4-4d92-a66b-b320668d61e7","resolution":{"observed_at":"2026-05-12T16:22:08.876700Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-09T06:31:02.800959+00:00","source":"crossref"},{"observed_at":"2026-08-09T06:30:57.326959+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"1912.03413","last_updated":"2019-12-07T02:10:19Z","snapshot_observed_at":"2026-08-07T06:17:34.662980Z","submitted_at":"2019-12-07T02:10:19Z","title":"Dissecting the Graphcore IPU Architecture via Microbenchmarking","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"1912.03413","snapshot_observed_at":"2026-08-06T17:13:37.885136Z","title":null,"venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2507.11506","last_updated":"2025-09-08T14:03:34Z","snapshot_observed_at":"2026-08-08T23:13:35.142650Z","submitted_at":"2025-07-15T17:21:31Z","title":"ELK: Exploring the Efficiency of Inter-core Connected AI Chips with Deep Learning Compiler Techniques","version":2},"reference_index":27,"source":"pdf_text","source_observed_at":"2026-08-06T17:13:37.885136Z"},"links":{"cited_paper":"/paper/1912.03413","citing_paper":"/paper/2507.11506"},"observation_digest":"sha256:4811ab566357fe5ebeb2fc36f2644a7c99e3db48ef193a5b91f382232e934132","observation_id":"6bd82abd-d5a8-4094-9232-8f91ef3c306c","resolution":{"observed_at":"2026-08-06T17:13:37.885136Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"1912.03413","last_updated":"2019-12-07T02:10:19Z","snapshot_observed_at":"2026-08-07T06:17:34.662980Z","submitted_at":"2019-12-07T02:10:19Z","title":"Dissecting the Graphcore IPU Architecture via Microbenchmarking","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"1912.03413","snapshot_observed_at":"2026-08-05T16:18:06.824346Z","title":"Dissecting the graphcore IPU architecture via microbenchmarking","venue":null,"work_id":null,"year":1912},"citing_paper":{"arxiv_id":"2508.18850","last_updated":"2025-08-26T09:29:23Z","snapshot_observed_at":"2026-08-08T23:12:33.597472Z","submitted_at":"2025-08-26T09:29:23Z","title":"ClusterFusion: Expanding Operator Fusion Scope for LLM Inference via Cluster-Level Collective Primitive","version":1},"reference_index":16,"source":"pdf_text","source_observed_at":"2026-08-05T16:18:06.824346Z"},"links":{"cited_paper":"/paper/1912.03413","citing_paper":"/paper/2508.18850"},"observation_digest":"sha256:f420bc73c8c7e26c1a257996c7ba5569c8900829ace134ca2c363f9a9560a13f","observation_id":"b323409f-a318-45e1-8c37-3e650a2df2ba","resolution":{"observed_at":"2026-08-05T16:18:06.824346Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"1912.03413","last_updated":"2019-12-07T02:10:19Z","snapshot_observed_at":"2026-08-07T06:17:34.662980Z","submitted_at":"2019-12-07T02:10:19Z","title":"Dissecting the Graphcore IPU Architecture via Microbenchmarking","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"1912.03413","snapshot_observed_at":"2026-08-04T23:46:34.727635Z","title":"Dissecting the Graphcore IPU Architecture via Microbenchmarking,","venue":null,"work_id":null,"year":1912},"citing_paper":{"arxiv_id":"2509.06365","last_updated":"2025-09-08T06:39:23Z","snapshot_observed_at":"2026-08-04T23:46:30.749346Z","submitted_at":"2025-09-08T06:39:23Z","title":"Hardware Acceleration in Portable MRIs: State of the Art and Future Prospects","version":1},"reference_index":120,"source":"pdf_text","source_observed_at":"2026-08-04T23:46:34.727635Z"},"links":{"cited_paper":"/paper/1912.03413","citing_paper":"/paper/2509.06365"},"observation_digest":"sha256:fcd60210198bb9c847000d62832f02feace6302aa491899a8478bad589e1125a","observation_id":"595c9e07-48db-440f-a449-5acc02f58094","resolution":{"observed_at":"2026-08-04T23:46:34.727635Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"1912.03413","last_updated":"2019-12-07T02:10:19Z","snapshot_observed_at":"2026-08-07T06:17:34.662980Z","submitted_at":"2019-12-07T02:10:19Z","title":"Dissecting the Graphcore IPU Architecture via Microbenchmarking","version":1},"cited_work":{"arxiv_id":"1912.03413","doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":"1912.03413","snapshot_observed_at":"2026-07-01T08:15:32.456749Z","title":"Dissecting the graphcore IPU architecture via microbenchmarking.arXiv preprint","venue":null,"work_id":"e9b2797c-1af7-40f8-a143-51ab3dfbad6b","year":2019},"citing_paper":{"arxiv_id":"2512.22168","last_updated":"2026-05-12T10:39:26Z","snapshot_observed_at":"2026-08-08T00:22:50.022619Z","submitted_at":"2025-12-17T11:26:58Z","title":"TileLoom: Automatic Dataflow Planning for Tile-Based Languages on Spatial Dataflow Accelerators","version":2},"reference_index":26,"source":"pdf_text","source_observed_at":"2026-05-16T21:55:59.146697Z"},"links":{"cited_paper":"/paper/1912.03413","citing_paper":"/paper/2512.22168"},"observation_digest":"sha256:419b0ad9ea28a8f5c7d807d9bb6bcd5580a30dedd2735d1e9cb531c31e220f16","observation_id":"05f60e48-f9b2-4048-86f0-08d29fdb2adc","resolution":{"observed_at":"2026-05-16T21:58:35.783137Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-09T06:31:02.800959+00:00","source":"crossref"},{"observed_at":"2026-08-09T06:30:57.326959+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"1912.03413","last_updated":"2019-12-07T02:10:19Z","snapshot_observed_at":"2026-08-07T06:17:34.662980Z","submitted_at":"2019-12-07T02:10:19Z","title":"Dissecting the Graphcore IPU Architecture via Microbenchmarking","version":1},"cited_work":{"arxiv_id":"1912.03413","doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":"1912.03413","snapshot_observed_at":"2026-07-01T08:15:32.456749Z","title":"Dissecting the graphcore IPU architecture via microbenchmarking.arXiv preprint","venue":null,"work_id":"e9b2797c-1af7-40f8-a143-51ab3dfbad6b","year":2019},"citing_paper":{"arxiv_id":"2604.12891","last_updated":"2026-04-14T15:40:30Z","snapshot_observed_at":"2026-08-02T07:31:09.428976Z","submitted_at":"2026-04-14T15:40:30Z","title":"TCL: Enabling Fast and Efficient Cross-Hardware Tensor Program Optimization via Continual Learning","version":1},"reference_index":20,"source":"pdf_text","source_observed_at":"2026-05-10T15:47:02.156274Z"},"links":{"cited_paper":"/paper/1912.03413","citing_paper":"/paper/2604.12891"},"observation_digest":"sha256:dff7795d176f8a44eec4e434d5fad9136b6d391a0c10434888887d8303f4da8e","observation_id":"af4e7913-71f3-4958-94fe-dc07e06a5f9e","resolution":{"observed_at":"2026-05-11T09:51:00.691710Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-09T06:31:02.800959+00:00","source":"crossref"},{"observed_at":"2026-08-09T06:30:57.326959+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"1912.03413","last_updated":"2019-12-07T02:10:19Z","snapshot_observed_at":"2026-08-07T06:17:34.662980Z","submitted_at":"2019-12-07T02:10:19Z","title":"Dissecting the Graphcore IPU Architecture via Microbenchmarking","version":1},"cited_work":{"arxiv_id":"1912.03413","doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":"1912.03413","snapshot_observed_at":"2026-07-01T08:15:32.456749Z","title":"Dissecting the graphcore IPU architecture via microbenchmarking.arXiv preprint","venue":null,"work_id":"e9b2797c-1af7-40f8-a143-51ab3dfbad6b","year":2019},"citing_paper":{"arxiv_id":"2605.07881","last_updated":"2026-05-08T15:33:28Z","snapshot_observed_at":"2026-07-06T23:20:11.042952Z","submitted_at":"2026-05-08T15:33:28Z","title":"AccelSync: Verifying Synchronization Coverage in Accelerator Pipeline Programs","version":1},"reference_index":26,"source":"pdf_text","source_observed_at":"2026-05-11T02:08:27.238196Z"},"links":{"cited_paper":"/paper/1912.03413","citing_paper":"/paper/2605.07881"},"observation_digest":"sha256:37d9d66c6e3818714a17d1e604116721a65ee92857719cf68ace30b421683dc5","observation_id":"ecf7559d-e075-49b3-80db-8d543ef5e0c0","resolution":{"observed_at":"2026-05-11T03:55:55.313243Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-09T06:31:02.800959+00:00","source":"crossref"},{"observed_at":"2026-08-09T06:30:57.326959+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"1912.03413","last_updated":"2019-12-07T02:10:19Z","snapshot_observed_at":"2026-08-07T06:17:34.662980Z","submitted_at":"2019-12-07T02:10:19Z","title":"Dissecting the Graphcore IPU Architecture via Microbenchmarking","version":1},"cited_work":{"arxiv_id":"1912.03413","doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":"1912.03413","snapshot_observed_at":"2026-07-01T08:15:32.456749Z","title":"Dissecting the graphcore IPU architecture via microbenchmarking.arXiv preprint","venue":null,"work_id":"e9b2797c-1af7-40f8-a143-51ab3dfbad6b","year":2019},"citing_paper":{"arxiv_id":"2605.09735","last_updated":"2026-06-30T03:39:11Z","snapshot_observed_at":"2026-07-06T23:21:49.499951Z","submitted_at":"2026-05-10T20:10:26Z","title":"KV-RM: Regularizing KV-Cache Movement for Static-Graph LLM Serving","version":1},"reference_index":19,"source":"pdf_text","source_observed_at":"2026-05-12T03:57:30.104609Z"},"links":{"cited_paper":"/paper/1912.03413","citing_paper":"/paper/2605.09735"},"observation_digest":"sha256:42b9e7879e81b623ade8bef688fa2d669ce98db8289a39724d4cc133054e9acf","observation_id":"ed969cd9-7e89-49db-8714-786f87eb5679","resolution":{"observed_at":"2026-05-12T06:51:27.015966Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-09T06:31:02.800959+00:00","source":"crossref"},{"observed_at":"2026-08-09T06:30:57.326959+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"1912.03413","last_updated":"2019-12-07T02:10:19Z","snapshot_observed_at":"2026-08-07T06:17:34.662980Z","submitted_at":"2019-12-07T02:10:19Z","title":"Dissecting the Graphcore IPU Architecture via Microbenchmarking","version":1},"cited_work":{"arxiv_id":"1912.03413","doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":"1912.03413","snapshot_observed_at":"2026-07-01T08:15:32.456749Z","title":"Dissecting the graphcore IPU architecture via microbenchmarking.arXiv preprint","venue":null,"work_id":"e9b2797c-1af7-40f8-a143-51ab3dfbad6b","year":2019},"citing_paper":{"arxiv_id":"2605.09735","last_updated":"2026-06-30T03:39:11Z","snapshot_observed_at":"2026-07-06T23:21:49.499951Z","submitted_at":"2026-05-10T20:10:26Z","title":"KV-RM: Regularizing KV-Cache Movement for Static-Graph LLM Serving","version":2},"reference_index":19,"source":"pdf_text","source_observed_at":"2026-07-01T08:05:44.256565Z"},"links":{"cited_paper":"/paper/1912.03413","citing_paper":"/paper/2605.09735"},"observation_digest":"sha256:e9ae4389ffe29860180da4f53d1e069796efdb61976a3f6263a2c30acc9f4bf8","observation_id":"8fa3a9d2-97b7-48ea-9d45-bb2d8bc79327","resolution":{"observed_at":"2026-07-01T08:15:32.459887Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-09T06:31:02.800959+00:00","source":"crossref"},{"observed_at":"2026-08-09T06:30:57.326959+00:00","source":"retraction_watch"}],"state":"measured"}}],"links":{"evidence":"/evidence","html":"/paper/1912.03413/citation-record","integrity":"/paper/1912.03413/integrity","json":"/paper/1912.03413/citation-record.json","paper":"/paper/1912.03413"},"outbound":[],"paper":{"arxiv_id":"1912.03413","last_updated":"2019-12-07T02:10:19Z","latest_version":1,"primary_category":"cs.DC","snapshot_observed_at":"2026-08-07T06:17:34.662980Z","submitted_at":"2019-12-07T02:10:19Z","title":"Dissecting the Graphcore IPU Architecture via Microbenchmarking"},"reference_resolution":{"displayed":0,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":0,"verified_exact":0,"verified_fuzzy":0},"total_outbound_references":0},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-09T06:31:02.800959+00:00","source":"crossref"},{"observed_at":"2026-08-09T06:30:57.326959+00:00","source":"retraction_watch"}],"thesis":"As of 10 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 9 inbound Pith citation observations for arXiv:1912.03413."}