{"as_of":"2026-08-10T23:27:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:87d8e5a3d1810929a526a5810e56e5ee470d9662942d11e20a54269a9360de4d","coverage":[{"denominator":0,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":4,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":4,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-10T06:31:04.303077+00:00","state":"measured"},{"denominator":4,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":4,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-10T20:33:37.547647Z","state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"arxiv_reference","source_observed_at":"2026-06-28T20:32:37.991874Z","state":"measured"}],"external_citation_measurements":[],"inbound":[{"citation":{"cited_paper":{"arxiv_id":"2208.11174","last_updated":"2022-08-23T20:02:42Z","snapshot_observed_at":"2026-07-06T13:44:48.609196Z","submitted_at":"2022-08-23T20:02:42Z","title":"Demystifying the Nvidia Ampere Architecture through Microbenchmarking and Instruction-level Analysis","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2208.11174","snapshot_observed_at":"2026-08-10T20:33:37.547647Z","title":null,"venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2501.08071","last_updated":"2025-01-14T12:36:18Z","snapshot_observed_at":"2026-08-10T22:23:44.379195Z","submitted_at":"2025-01-14T12:36:18Z","title":"CuAsmRL: Optimizing GPU SASS Schedules via Deep Reinforcement Learning","version":1},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-08-10T20:33:37.547647Z"},"links":{"cited_paper":"/paper/2208.11174","citing_paper":"/paper/2501.08071"},"observation_digest":"sha256:a7d43e7fa1754a888112ce4389bcdca086b0c96acb11e9e366608a1c8de0e1e0","observation_id":"2fa46678-68de-4cf1-816a-d3a0b4876430","resolution":{"observed_at":"2026-08-10T20:33:37.547647Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2208.11174","last_updated":"2022-08-23T20:02:42Z","snapshot_observed_at":"2026-07-06T13:44:48.609196Z","submitted_at":"2022-08-23T20:02:42Z","title":"Demystifying the Nvidia Ampere Architecture through Microbenchmarking and Instruction-level Analysis","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2208.11174","snapshot_observed_at":"2026-08-08T20:44:48.392762Z","title":"Ailon, N","venue":null,"work_id":null,"year":null},"citing_paper":{"arxiv_id":"2502.05003","last_updated":"2025-06-10T18:01:40Z","snapshot_observed_at":"2026-08-09T18:46:49.510936Z","submitted_at":"2025-02-07T15:23:34Z","title":"QuEST: Stable Training of LLMs with 1-Bit Weights and Activations","version":2},"reference_index":2022,"source":"pdf_text","source_observed_at":"2026-08-08T20:44:48.392762Z"},"links":{"cited_paper":"/paper/2208.11174","citing_paper":"/paper/2502.05003"},"observation_digest":"sha256:317b596f796e8cd4cca6b89ef348353a99753308937defb786bfd1278b53a07c","observation_id":"48ce5bd3-1114-4109-9ed5-56510e59bed9","resolution":{"observed_at":"2026-08-08T20:44:48.392762Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2208.11174","last_updated":"2022-08-23T20:02:42Z","snapshot_observed_at":"2026-07-06T13:44:48.609196Z","submitted_at":"2022-08-23T20:02:42Z","title":"Demystifying the Nvidia Ampere Architecture through Microbenchmarking and Instruction-level Analysis","version":1},"cited_work":{"arxiv_id":"2208.11174","doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":"2208.11174","snapshot_observed_at":"2026-06-28T20:32:37.991874Z","title":"Demystifying the Nvidia Ampere architecture through microbenchmarking and instruction-level analysis,","venue":null,"work_id":"baf5b515-87d0-4679-a2fa-a7cf62ffa11b","year":2022},"citing_paper":{"arxiv_id":"2606.00486","last_updated":"2026-06-02T04:36:50Z","snapshot_observed_at":"2026-08-01T21:53:30.310985Z","submitted_at":"2026-05-30T02:37:54Z","title":"Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures","version":2},"reference_index":2,"source":"pdf_text","source_observed_at":"2026-06-28T18:32:33.189475Z"},"links":{"cited_paper":"/paper/2208.11174","citing_paper":"/paper/2606.00486"},"observation_digest":"sha256:47aa52c64ddfe4de2764175e2e4a722ced8eb848da54f28e1280e3f8fe7af3dd","observation_id":"0e8a28ad-273f-4be0-beee-ec0f50889c3e","resolution":{"observed_at":"2026-06-28T20:32:37.993466Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-10T06:31:04.303077+00:00","source":"crossref"},{"observed_at":"2026-08-10T06:30:57.382061+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2208.11174","last_updated":"2022-08-23T20:02:42Z","snapshot_observed_at":"2026-07-06T13:44:48.609196Z","submitted_at":"2022-08-23T20:02:42Z","title":"Demystifying the Nvidia Ampere Architecture through Microbenchmarking and Instruction-level Analysis","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2208.11174","snapshot_observed_at":"2026-08-01T00:15:00.478533Z","title":null,"venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2607.26340","last_updated":"2026-07-28T23:25:57Z","snapshot_observed_at":"2026-08-01T23:22:35.665693Z","submitted_at":"2026-07-28T23:25:57Z","title":"Incast-Free MoE Rate-Based Scheduling","version":1},"reference_index":6,"source":"pdf_text","source_observed_at":"2026-08-01T00:15:00.478533Z"},"links":{"cited_paper":"/paper/2208.11174","citing_paper":"/paper/2607.26340"},"observation_digest":"sha256:92724752ed781adbc2d57597fa5aa89101a26877e801aeb4a76e76fd94ccfc4a","observation_id":"ba02d514-9b0d-4236-9713-264ed07818bb","resolution":{"observed_at":"2026-08-01T00:15:00.478533Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}}],"links":{"evidence":"/evidence","html":"/paper/2208.11174/citation-record","integrity":"/paper/2208.11174/integrity","json":"/paper/2208.11174/citation-record.json","paper":"/paper/2208.11174"},"outbound":[],"paper":{"arxiv_id":"2208.11174","last_updated":"2022-08-23T20:02:42Z","latest_version":1,"primary_category":"cs.AR","snapshot_observed_at":"2026-07-06T13:44:48.609196Z","submitted_at":"2022-08-23T20:02:42Z","title":"Demystifying the Nvidia Ampere Architecture through Microbenchmarking and Instruction-level Analysis"},"reference_resolution":{"displayed":0,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":0,"verified_exact":0,"verified_fuzzy":0},"total_outbound_references":0},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-10T06:31:04.303077+00:00","source":"crossref"},{"observed_at":"2026-08-10T06:30:57.382061+00:00","source":"retraction_watch"}],"thesis":"As of 10 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 4 inbound Pith citation observations for arXiv:2208.11174."}