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arxiv: 2309.07027 · v2 · submitted 2023-09-13 · 🪐 quant-ph

High performance Boson Sampling simulation via data-flow engines

Pith reviewed 2026-05-24 06:52 UTC · model grok-4.3

classification 🪐 quant-ph
keywords boson samplingpermanent computationBB/FG formulaGray code orderingFPGA data-flow enginequantum simulation
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The pith

Generalizing the BB/FG permanent formula with n-ary Gray codes cuts computation time for boson sampling matrices that have repeated rows.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper generalizes the Balasubramanian-Bax-Franklin-Glynn permanent formula so that it accounts for row multiplicities by ordering the addends according to an n-ary Gray code. This ordering lowers the number of operations needed when some rows repeat, a situation that arises in lossy boson sampling. The authors then map the resulting algorithm onto FPGA data-flow engines and use it to draw samples from 60-mode interferometers with up to 40 photons. The measured rate is roughly 80 seconds per sample on four chips, and the observed scaling matches the Clifford-Clifford bound. The same design works for both ideal and lossy experiments.

Core claim

We generalize the BB/FG permanent formula to account for row multiplicities during permanent evaluation by incorporating n-ary Gray code ordering of the addends; we then implement the algorithm on FPGA-based data-flow engines to draw samples from a 60-mode interferometer at up to 40 photons with an average rate of approximately 80 seconds per sample on four chips.

What carries the argument

Generalized BB/FG permanent formula that uses n-ary Gray code ordering of addends to exploit row multiplicities.

If this is right

  • Boson sampling instances with loss become directly simulable on the same hardware without separate handling of repeated rows.
  • A single scalar parameter extracted from run time versus photon number fully characterizes the performance of any BS simulator built on this method.
  • The FPGA design can be reused for both ideal and lossy experiments without code changes.
  • The approach supplies a concrete hardware benchmark against which future theoretical speed-ups can be compared.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same Gray-code trick could be applied to other permanent-evaluation tasks that encounter repeated rows, such as certain graph-counting problems.
  • If the FPGA implementation scales linearly with the number of chips, a modest cluster could reach the photon numbers where classical simulation is believed to become intractable.
  • A portable performance metric derived from the Clifford-Clifford bound lets different hardware platforms be compared without re-running full experiments.

Load-bearing premise

Ordering the addends of the permanent sum by an n-ary Gray code actually reduces the number of arithmetic operations whenever some rows of the matrix are identical.

What would settle it

Measure the exact number of additions and multiplications performed by the generalized formula on a matrix with known row multiplicities and compare it to the count for the unmodified BB/FG formula on the same matrix.

Figures

Figures reproduced from arXiv: 2309.07027 by \'Agoston Kaposi, Gregory Morse, Micha{\l} Oszmaniec, Oskar Mencer, P\'eter Rakyta, Tam\'as Kozsik, Tomasz Rybotycki, Uro\v{s} Stoj\v{c}i\'c, Zolt\'an Kolarovszki, Zolt\'an Zimbor\'as.

Figure 1
Figure 1. Figure 1: The structure of the computing kernels realized on t [PITH_FULL_IMAGE:figures/full_fig_p007_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Performance comparison of the permanent calculator D [PITH_FULL_IMAGE:figures/full_fig_p010_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Performance comparison of the permanent calculator D [PITH_FULL_IMAGE:figures/full_fig_p011_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: The numerical accuracy of different implementations t [PITH_FULL_IMAGE:figures/full_fig_p012_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Left: A schematic of a standard BS experiment. The blue elements denote beam splitters inside the interferometer. A net of interconnected beam splitters is the usual physical realization of the interferometer. Right: A schematic representation of the loss model we use in this work. On the left side of the diagrammatic equation, we see a lossy channel on a single mode, with particle transmission probability… view at source ↗
Figure 6
Figure 6. Figure 6: Performance of the developed BS simulation design ex [PITH_FULL_IMAGE:figures/full_fig_p015_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: The staggered strategy to calculate the multiplici [PITH_FULL_IMAGE:figures/full_fig_p022_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Batched performance comparison of the permanent calc [PITH_FULL_IMAGE:figures/full_fig_p023_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Batched performance comparison of the permanent calc [PITH_FULL_IMAGE:figures/full_fig_p024_9.png] view at source ↗
read the original abstract

In this work, we generalize the Balasubramanian-Bax-Franklin-Glynn (BB/FG) permanent formula to account for row multiplicities during the permanent evaluation and reduce the complexity of permanent evaluation in scenarios where such multiplicities occur. This is achieved by incorporating n-ary Gray code ordering of the addends during the evaluation. We implemented the designed algorithm on FPGA-based data-flow engines and utilized the developed accessory to speed up boson sampling simulations up to $40$ photons, by drawing samples from a $60$ mode interferometer at an averaged rate of $\sim80$ seconds per sample utilizing $4$ FPGA chips. We also show that the performance of our BS simulator is in line with the theoretical estimation of Clifford \& Clifford \cite{clifford2020faster} providing a way to define a single parameter to characterize the performance of the BS simulator in a portable way. The developed design can be used to simulate both ideal and lossy boson sampling experiments.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The paper generalizes the Balasubramanian-Bax-Franklin-Glynn (BB/FG) permanent formula to account for row multiplicities during permanent evaluation by incorporating n-ary Gray code ordering of the addends. This algorithm is implemented on FPGA-based data-flow engines to accelerate boson sampling simulations, achieving draws from a 60-mode interferometer with up to 40 photons at an average rate of ~80 seconds per sample on 4 FPGA chips. Performance is reported to align with the Clifford & Clifford theoretical bound, enabling a portable single-parameter characterization, and the design supports both ideal and lossy experiments.

Significance. If the generalization is shown to be correct and the implementation verified with explicit checks, the work would advance practical classical simulation of boson sampling at scales relevant to quantum device benchmarking. The hardware mapping to data-flow engines and the use of an independent theoretical bound (rather than self-fitted parameters) for performance characterization are positive features that could aid reproducibility across platforms.

major comments (2)
  1. [Generalization of BB/FG formula and permanent evaluation] The generalization of the BB/FG formula via n-ary Gray code ordering for row multiplicities is stated in the abstract and algorithm description, but supplies neither an explicit derivation of the adjusted addend contributions nor a worked example on a matrix with repeated rows confirming that the sum matches the permanent definition while correctly skipping redundant terms. This directly affects the validity of the claimed complexity reduction and the headline sampling rate.
  2. [Implementation results and performance claims] The results section asserts successful FPGA implementation and agreement with theory for the 40-photon/60-mode case at ~80 s/sample, yet provides no verification details, error analysis, comparison data against exact permanents, or cross-checks that the hardware mapping preserves the generalized formula's output. Without these, the soundness of the reported performance cannot be confirmed.
minor comments (1)
  1. The abstract and text would benefit from a brief statement of the exact matrix dimensions and multiplicity patterns used in the largest reported runs to allow independent reproduction.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive and detailed review. The comments highlight areas where additional clarity would strengthen the manuscript. We address each major comment below and will revise accordingly.

read point-by-point responses
  1. Referee: [Generalization of BB/FG formula and permanent evaluation] The generalization of the BB/FG formula via n-ary Gray code ordering for row multiplicities is stated in the abstract and algorithm description, but supplies neither an explicit derivation of the adjusted addend contributions nor a worked example on a matrix with repeated rows confirming that the sum matches the permanent definition while correctly skipping redundant terms. This directly affects the validity of the claimed complexity reduction and the headline sampling rate.

    Authors: We agree that an explicit derivation and worked example would improve verifiability. The manuscript presents the generalized algorithm and its use of n-ary Gray codes, but we will add a dedicated subsection deriving the adjusted addend contributions for row multiplicities and include a small worked example (e.g., a 3x3 matrix with repeated rows) demonstrating that the result equals the permanent while correctly handling multiplicities and skipping redundancies. This revision will directly address concerns about the complexity reduction. revision: yes

  2. Referee: [Implementation results and performance claims] The results section asserts successful FPGA implementation and agreement with theory for the 40-photon/60-mode case at ~80 s/sample, yet provides no verification details, error analysis, comparison data against exact permanents, or cross-checks that the hardware mapping preserves the generalized formula's output. Without these, the soundness of the reported performance cannot be confirmed.

    Authors: The performance characterization relies on the independent Clifford & Clifford bound rather than self-fitted parameters, which is a strength for portability. We acknowledge that the current draft lacks explicit verification details for the large-scale case. Direct comparison to exact permanents is infeasible at 40 photons due to computational cost. In revision we will add: (i) verification results on smaller instances where exact permanents can be computed, (ii) details of hardware mapping validation via RTL simulation and consistency checks, and (iii) error analysis for the FPGA implementation. These additions will support the reported rates without changing the headline figures. revision: partial

Circularity Check

0 steps flagged

No circularity: empirical performance measured against external theoretical bound

full rationale

The paper's central result is an FPGA implementation achieving measured sampling rates for boson sampling up to 40 photons, reported as aligning with the independent Clifford & Clifford theoretical bound rather than any fitted parameter derived from the authors' own runs. The generalization of the BB/FG formula via n-ary Gray code is presented as a new algorithmic contribution without any self-referential definition or reduction of the reported performance metric to the inputs by construction. No load-bearing step reduces a prediction or uniqueness claim to a self-citation chain or fitted input; the work is self-contained against the external benchmark.

Axiom & Free-Parameter Ledger

0 free parameters · 2 axioms · 0 invented entities

The central claim rests on the validity of the existing BB/FG permanent formula, the correctness of the n-ary Gray code reordering for multiplicity reduction, and the assumption that FPGA data-flow engines can realize the algorithm at the claimed throughput; no free parameters or invented entities are introduced.

axioms (2)
  • standard math The Balasubramanian-Bax-Franklin-Glynn (BB/FG) formula correctly computes the permanent of a matrix.
    The paper explicitly generalizes this established formula.
  • domain assumption n-ary Gray code ordering reduces the number of operations when row multiplicities are present.
    This is the key step asserted in the generalization.

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discussion (0)

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