{"as_of":"2026-08-09T01:39:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:d37ffcead1d79cd60e5bf0300f53adae0db9de6ab816c4654b473ac876426911","coverage":[{"denominator":0,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":15,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":15,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-08T06:32:00.761636+00:00","state":"measured"},{"denominator":15,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":15,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-07T10:45:07.070822Z","state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":1,"source":"arxiv_reference","source_observed_at":"2026-08-05T02:28:24.338817Z","state":"measured"}],"external_citation_measurements":[{"count":16,"observed_at":"2026-08-05T02:28:24.338817Z","source":"arxiv_reference"}],"inbound":[{"citation":{"cited_paper":{"arxiv_id":"2309.07544","last_updated":"2023-12-10T00:23:04Z","snapshot_observed_at":"2026-08-03T23:24:33.278328Z","submitted_at":"2023-09-14T09:15:34Z","title":"VerilogEval: Evaluating Large Language Models for Verilog Code Generation","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2309.07544","snapshot_observed_at":"2026-08-07T10:45:07.070822Z","title":"Verilogeval: Evaluating large language models for verilog code generation,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2506.04544","last_updated":"2025-07-08T19:43:08Z","snapshot_observed_at":"2026-08-08T04:16:00.012369Z","submitted_at":"2025-06-05T01:29:18Z","title":"hdl2v: A Code Translation Dataset for Enhanced LLM Verilog Generation","version":2},"reference_index":20,"source":"pdf_text","source_observed_at":"2026-08-07T10:45:07.070822Z"},"links":{"cited_paper":"/paper/2309.07544","citing_paper":"/paper/2506.04544"},"observation_digest":"sha256:816da51541186643d585d5f6ed6c1a5b6ffe916bb169c84120c9ef0848344ecc","observation_id":"da3d5ac3-c594-4904-8f3c-4f9c62f5a3f5","resolution":{"observed_at":"2026-08-07T10:45:07.070822Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2309.07544","last_updated":"2023-12-10T00:23:04Z","snapshot_observed_at":"2026-08-03T23:24:33.278328Z","submitted_at":"2023-09-14T09:15:34Z","title":"VerilogEval: Evaluating Large Language Models for Verilog Code Generation","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2309.07544","snapshot_observed_at":"2026-08-07T05:43:45.594753Z","title":"Verilogeval: Evaluating large language models for verilog code generation,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2506.07239","last_updated":"2025-06-29T01:51:01Z","snapshot_observed_at":"2026-08-07T05:36:00.643486Z","submitted_at":"2025-06-08T17:53:22Z","title":"VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code","version":2},"reference_index":49,"source":"pdf_text","source_observed_at":"2026-08-07T05:43:45.594753Z"},"links":{"cited_paper":"/paper/2309.07544","citing_paper":"/paper/2506.07239"},"observation_digest":"sha256:3094469d73a793769670f3bfc5010ef827ac289e3c6ac58d27e70fdfc1dc977f","observation_id":"b89db61c-a286-4337-9599-cdc713bc6500","resolution":{"observed_at":"2026-08-07T05:43:45.594753Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2309.07544","last_updated":"2023-12-10T00:23:04Z","snapshot_observed_at":"2026-08-03T23:24:33.278328Z","submitted_at":"2023-09-14T09:15:34Z","title":"VerilogEval: Evaluating Large Language Models for Verilog Code Generation","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2309.07544","snapshot_observed_at":"2026-08-07T00:31:00.458485Z","title":"Verilogeval: Evaluating large language models for verilog code generation,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2506.13905","last_updated":"2025-09-08T18:17:46Z","snapshot_observed_at":"2026-08-07T17:09:46.132647Z","submitted_at":"2025-06-16T18:33:25Z","title":"Spec2RTL-Agent: Automated Hardware Code Generation from Complex Specifications Using LLM Agent Systems","version":2},"reference_index":5,"source":"pdf_text","source_observed_at":"2026-08-07T00:31:00.458485Z"},"links":{"cited_paper":"/paper/2309.07544","citing_paper":"/paper/2506.13905"},"observation_digest":"sha256:462aaa283bb90cbe6307e5334f96c370e62865c20be49f5bab01d942f08ad217","observation_id":"7444a3c0-2d95-422e-8536-a27aff96fcef","resolution":{"observed_at":"2026-08-07T00:31:00.458485Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2309.07544","last_updated":"2023-12-10T00:23:04Z","snapshot_observed_at":"2026-08-03T23:24:33.278328Z","submitted_at":"2023-09-14T09:15:34Z","title":"VerilogEval: Evaluating Large Language Models for Verilog Code Generation","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2309.07544","snapshot_observed_at":"2026-08-06T17:51:02.593071Z","title":"VerilogEval: Evaluating large language models for Verilog code generation,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2507.09948","last_updated":"2025-07-19T21:32:24Z","snapshot_observed_at":"2026-08-06T17:40:59.657771Z","submitted_at":"2025-07-14T05:48:09Z","title":"Iceberg: Enhancing HLS Modeling with Synthetic Data","version":2},"reference_index":3,"source":"pdf_text","source_observed_at":"2026-08-06T17:51:02.593071Z"},"links":{"cited_paper":"/paper/2309.07544","citing_paper":"/paper/2507.09948"},"observation_digest":"sha256:126fb63640c183064dd7a0d264972a696a48cb4495e3653f30c5d53381a32af1","observation_id":"93c00a0d-56fa-4890-a8d4-0e80bcf81c61","resolution":{"observed_at":"2026-08-06T17:51:02.593071Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2309.07544","last_updated":"2023-12-10T00:23:04Z","snapshot_observed_at":"2026-08-03T23:24:33.278328Z","submitted_at":"2023-09-14T09:15:34Z","title":"VerilogEval: Evaluating Large Language Models for Verilog Code Generation","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2309.07544","snapshot_observed_at":"2026-08-06T18:54:03.834957Z","title":null,"venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2507.13369","last_updated":"2025-07-09T17:06:54Z","snapshot_observed_at":"2026-08-08T10:58:07.113782Z","submitted_at":"2025-07-09T17:06:54Z","title":"VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation","version":1},"reference_index":21,"source":"pdf_text","source_observed_at":"2026-08-06T18:54:03.834957Z"},"links":{"cited_paper":"/paper/2309.07544","citing_paper":"/paper/2507.13369"},"observation_digest":"sha256:501ff2ff7d1c59caa42d023ac6747b4724aea20442f72df8f99ac9f1cffb7104","observation_id":"5ec78f87-40c2-408d-9fb4-24fbcba1a705","resolution":{"observed_at":"2026-08-06T18:54:03.834957Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2309.07544","last_updated":"2023-12-10T00:23:04Z","snapshot_observed_at":"2026-08-03T23:24:33.278328Z","submitted_at":"2023-09-14T09:15:34Z","title":"VerilogEval: Evaluating Large Language Models for Verilog Code Generation","version":2},"cited_work":{"arxiv_id":"2309.07544","doi":"10.48550/arxiv.2309.07544","metadata_source":"arxiv_reference","pith_arxiv_id":"2309.07544","snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"VerilogEval: Evaluating large language models for Verilog code generation","venue":"arXiv (Cornell University)","work_id":"bc28a516-2f3e-40d9-a0b7-14aab22dddc0","year":2023},"citing_paper":{"arxiv_id":"2601.14541","last_updated":"2026-04-24T03:33:56Z","snapshot_observed_at":"2026-08-05T05:40:21.259978Z","submitted_at":"2026-01-20T23:45:40Z","title":"Report for NSF Workshop on AI for Electronic Design Automation","version":4},"reference_index":47,"source":"pdf_text","source_observed_at":"2026-05-16T12:35:39.690799Z"},"links":{"cited_paper":"/paper/2309.07544","citing_paper":"/paper/2601.14541"},"observation_digest":"sha256:742f3eeca30bf84b2b47e601605ecc814abab16ede96d72d573a9fe5e50a7a4a","observation_id":"316eca86-dff6-4a51-9b75-050c15e72025","resolution":{"observed_at":"2026-05-16T12:37:53.112506Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2309.07544","last_updated":"2023-12-10T00:23:04Z","snapshot_observed_at":"2026-08-03T23:24:33.278328Z","submitted_at":"2023-09-14T09:15:34Z","title":"VerilogEval: Evaluating Large Language Models for Verilog Code Generation","version":2},"cited_work":{"arxiv_id":"2309.07544","doi":"10.48550/arxiv.2309.07544","metadata_source":"arxiv_reference","pith_arxiv_id":"2309.07544","snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"VerilogEval: Evaluating large language models for Verilog code generation","venue":"arXiv (Cornell University)","work_id":"bc28a516-2f3e-40d9-a0b7-14aab22dddc0","year":2023},"citing_paper":{"arxiv_id":"2604.14989","last_updated":"2026-04-26T15:34:21Z","snapshot_observed_at":"2026-07-06T23:02:40.364114Z","submitted_at":"2026-04-16T13:18:24Z","title":"Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement","version":2},"reference_index":20,"source":"pdf_text","source_observed_at":"2026-05-10T10:48:11.646826Z"},"links":{"cited_paper":"/paper/2309.07544","citing_paper":"/paper/2604.14989"},"observation_digest":"sha256:e233f12585ff8560a92fed4989ca9306a3d5cb3fdae8c4c7f7f5d49b2bfa4eec","observation_id":"f3196897-ce6e-4e89-b5d6-bb63a217a2ab","resolution":{"observed_at":"2026-05-10T10:49:56.176778Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2309.07544","last_updated":"2023-12-10T00:23:04Z","snapshot_observed_at":"2026-08-03T23:24:33.278328Z","submitted_at":"2023-09-14T09:15:34Z","title":"VerilogEval: Evaluating Large Language Models for Verilog Code Generation","version":2},"cited_work":{"arxiv_id":"2309.07544","doi":"10.48550/arxiv.2309.07544","metadata_source":"arxiv_reference","pith_arxiv_id":"2309.07544","snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"VerilogEval: Evaluating large language models for Verilog code generation","venue":"arXiv (Cornell University)","work_id":"bc28a516-2f3e-40d9-a0b7-14aab22dddc0","year":2023},"citing_paper":{"arxiv_id":"2604.27415","last_updated":"2026-04-30T04:35:43Z","snapshot_observed_at":"2026-08-08T21:42:05.972268Z","submitted_at":"2026-04-30T04:35:43Z","title":"ChipLingo: A Systematic Training Framework for Large Language Models in EDA","version":1},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-05-07T09:40:25.666277Z"},"links":{"cited_paper":"/paper/2309.07544","citing_paper":"/paper/2604.27415"},"observation_digest":"sha256:98dc32679fb02fa4a6068d0038014d2d881c6ccff1146d9f6f8e1cc7c39cdf05","observation_id":"60eddfe4-5d7c-4cf5-9c7c-8ce5193266c1","resolution":{"observed_at":"2026-05-12T09:41:27.221550Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2309.07544","last_updated":"2023-12-10T00:23:04Z","snapshot_observed_at":"2026-08-03T23:24:33.278328Z","submitted_at":"2023-09-14T09:15:34Z","title":"VerilogEval: Evaluating Large Language Models for Verilog Code Generation","version":2},"cited_work":{"arxiv_id":"2309.07544","doi":"10.48550/arxiv.2309.07544","metadata_source":"arxiv_reference","pith_arxiv_id":"2309.07544","snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"VerilogEval: Evaluating large language models for Verilog code generation","venue":"arXiv (Cornell University)","work_id":"bc28a516-2f3e-40d9-a0b7-14aab22dddc0","year":2023},"citing_paper":{"arxiv_id":"2606.05253","last_updated":"2026-06-03T14:51:33Z","snapshot_observed_at":"2026-08-01T00:36:11.076649Z","submitted_at":"2026-06-03T14:51:33Z","title":"Alpha-RTL: Test-Time Training for RTL Hardware Optimization","version":1},"reference_index":2,"source":"arxiv_source","source_observed_at":"2026-06-28T07:11:52.187869Z"},"links":{"cited_paper":"/paper/2309.07544","citing_paper":"/paper/2606.05253"},"observation_digest":"sha256:885eb7470d3f07ed92c35c9441548e47adcbebb8f01007767c44cc75ca3d8953","observation_id":"11c2f4ac-8e93-4b49-bae2-cc32dfd90908","resolution":{"observed_at":"2026-07-02T07:06:44.164135Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2309.07544","last_updated":"2023-12-10T00:23:04Z","snapshot_observed_at":"2026-08-03T23:24:33.278328Z","submitted_at":"2023-09-14T09:15:34Z","title":"VerilogEval: Evaluating Large Language Models for Verilog Code Generation","version":2},"cited_work":{"arxiv_id":"2309.07544","doi":"10.48550/arxiv.2309.07544","metadata_source":"arxiv_reference","pith_arxiv_id":"2309.07544","snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"VerilogEval: Evaluating large language models for Verilog code generation","venue":"arXiv (Cornell University)","work_id":"bc28a516-2f3e-40d9-a0b7-14aab22dddc0","year":2023},"citing_paper":{"arxiv_id":"2606.10285","last_updated":"2026-06-09T01:17:46Z","snapshot_observed_at":"2026-07-06T23:49:32.647742Z","submitted_at":"2026-06-09T01:17:46Z","title":"OpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Design","version":1},"reference_index":36,"source":"pdf_text","source_observed_at":"2026-06-27T13:44:50.470339Z"},"links":{"cited_paper":"/paper/2309.07544","citing_paper":"/paper/2606.10285"},"observation_digest":"sha256:6ae44019687183318870229e562bb7ae354f63969710888e12ff9a0f3673ab06","observation_id":"77c7a08d-deb1-4751-bc70-01518cd97f62","resolution":{"observed_at":"2026-07-03T04:37:37.415159Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2309.07544","last_updated":"2023-12-10T00:23:04Z","snapshot_observed_at":"2026-08-03T23:24:33.278328Z","submitted_at":"2023-09-14T09:15:34Z","title":"VerilogEval: Evaluating Large Language Models for Verilog Code Generation","version":2},"cited_work":{"arxiv_id":"2309.07544","doi":"10.48550/arxiv.2309.07544","metadata_source":"arxiv_reference","pith_arxiv_id":"2309.07544","snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"VerilogEval: Evaluating large language models for Verilog code generation","venue":"arXiv (Cornell University)","work_id":"bc28a516-2f3e-40d9-a0b7-14aab22dddc0","year":2023},"citing_paper":{"arxiv_id":"2606.23704","last_updated":"2026-06-10T10:57:23Z","snapshot_observed_at":"2026-08-03T03:43:24.884529Z","submitted_at":"2026-06-10T10:57:23Z","title":"PCB-QA: Evaluating LLMs over the First Printed Circuit Board Design Question-Answer Dataset","version":1},"reference_index":25,"source":"pdf_text","source_observed_at":"2026-06-27T08:15:24.364818Z"},"links":{"cited_paper":"/paper/2309.07544","citing_paper":"/paper/2606.23704"},"observation_digest":"sha256:55841adbfa9f7a6bae56c3012e16fc70bede052086ff038b0c886ccc88a37866","observation_id":"c327e771-2feb-45d6-ae0b-c9a8e14123b4","resolution":{"observed_at":"2026-06-27T08:20:44.917633Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2309.07544","last_updated":"2023-12-10T00:23:04Z","snapshot_observed_at":"2026-08-03T23:24:33.278328Z","submitted_at":"2023-09-14T09:15:34Z","title":"VerilogEval: Evaluating Large Language Models for Verilog Code Generation","version":2},"cited_work":{"arxiv_id":"2309.07544","doi":"10.48550/arxiv.2309.07544","metadata_source":"arxiv_reference","pith_arxiv_id":"2309.07544","snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"VerilogEval: Evaluating large language models for Verilog code generation","venue":"arXiv (Cornell University)","work_id":"bc28a516-2f3e-40d9-a0b7-14aab22dddc0","year":2023},"citing_paper":{"arxiv_id":"2606.28279","last_updated":"2026-06-26T17:21:06Z","snapshot_observed_at":"2026-08-06T17:12:53.583746Z","submitted_at":"2026-06-26T17:21:06Z","title":"Agentic Hardware Design as Repository-Level Code Evolution","version":1},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-06-29T01:49:07.838897Z"},"links":{"cited_paper":"/paper/2309.07544","citing_paper":"/paper/2606.28279"},"observation_digest":"sha256:9a549629ce8960ca40972e483eb4fad831eefc29b79262d3e4c4e9c529ffb225","observation_id":"7ce6bdda-eb4a-4bb3-b26c-2d12951e45af","resolution":{"observed_at":"2026-07-01T18:45:58.289303Z","resolver_source":"arxiv_id","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2309.07544","last_updated":"2023-12-10T00:23:04Z","snapshot_observed_at":"2026-08-03T23:24:33.278328Z","submitted_at":"2023-09-14T09:15:34Z","title":"VerilogEval: Evaluating Large Language Models for Verilog Code Generation","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2309.07544","snapshot_observed_at":"2026-07-12T01:16:50.927415Z","title":null,"venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2607.03601","last_updated":"2026-07-03T20:58:29Z","snapshot_observed_at":"2026-08-03T18:38:21.736479Z","submitted_at":"2026-07-03T20:58:29Z","title":"ArchEval: Measuring AI Agents as Computer Architects","version":1},"reference_index":28,"source":"pdf_text","source_observed_at":"2026-07-12T01:16:50.927415Z"},"links":{"cited_paper":"/paper/2309.07544","citing_paper":"/paper/2607.03601"},"observation_digest":"sha256:9a1fbbb96dfdfc6780b787fd5ec33e8d9576e1197e93a855fe203c136f79d25a","observation_id":"60969956-7511-4124-8465-1829f3a0415f","resolution":{"observed_at":"2026-07-12T01:16:50.927415Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2309.07544","last_updated":"2023-12-10T00:23:04Z","snapshot_observed_at":"2026-08-03T23:24:33.278328Z","submitted_at":"2023-09-14T09:15:34Z","title":"VerilogEval: Evaluating Large Language Models for Verilog Code Generation","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2309.07544","snapshot_observed_at":"2026-08-01T09:49:36.505128Z","title":"VerilogEval: Evaluating Large Language Models for Verilog Code Generation,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2607.20638","last_updated":"2026-07-22T18:10:07Z","snapshot_observed_at":"2026-08-06T04:54:27.491084Z","submitted_at":"2026-07-22T18:10:07Z","title":"WaveformQA: Benchmarking LLM Temporal Reasoning on Digital Waveforms","version":1},"reference_index":22,"source":"pdf_text","source_observed_at":"2026-08-01T09:49:36.505128Z"},"links":{"cited_paper":"/paper/2309.07544","citing_paper":"/paper/2607.20638"},"observation_digest":"sha256:d08cb879a4d4f1841bf37e6e2d14a211f71810aa2a88e376ffa4261ceaab7ffa","observation_id":"fadea7a6-434b-4fc5-bd31-c33dcbceeec9","resolution":{"observed_at":"2026-08-01T09:49:36.505128Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2309.07544","last_updated":"2023-12-10T00:23:04Z","snapshot_observed_at":"2026-08-03T23:24:33.278328Z","submitted_at":"2023-09-14T09:15:34Z","title":"VerilogEval: Evaluating Large Language Models for Verilog Code Generation","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2309.07544","snapshot_observed_at":"2026-08-03T01:29:16.231691Z","title":"VerilogEval: Evaluating large language models for Verilog code generation,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2607.28877","last_updated":"2026-07-30T22:43:33Z","snapshot_observed_at":"2026-08-08T05:46:32.427523Z","submitted_at":"2026-07-30T22:43:33Z","title":"Open-Source LLM-Driven Formal Verification: A Multi-Agent Pipeline for RTL Repair","version":1},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-08-03T01:29:16.231691Z"},"links":{"cited_paper":"/paper/2309.07544","citing_paper":"/paper/2607.28877"},"observation_digest":"sha256:3ea1a1d875cb84bd92cc4c6c07a80536f69234885f017ad4e0ed87bb9ea96966","observation_id":"1a1f72c5-229d-4644-906a-c1ef3c6b6839","resolution":{"observed_at":"2026-08-03T01:29:16.231691Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}}],"links":{"evidence":"/evidence","html":"/paper/2309.07544/citation-record","integrity":"/paper/2309.07544/integrity","json":"/paper/2309.07544/citation-record.json","paper":"/paper/2309.07544"},"outbound":[],"paper":{"arxiv_id":"2309.07544","last_updated":"2023-12-10T00:23:04Z","latest_version":2,"primary_category":"cs.LG","snapshot_observed_at":"2026-08-03T23:24:33.278328Z","submitted_at":"2023-09-14T09:15:34Z","title":"VerilogEval: Evaluating Large Language Models for Verilog Code Generation"},"reference_resolution":{"displayed":0,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":0,"verified_exact":0,"verified_fuzzy":0},"total_outbound_references":0},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"thesis":"As of 9 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 15 inbound Pith citation observations for arXiv:2309.07544."}