{"as_of":"2026-08-23T23:38:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:4e900d1c4752543c6c37aec933b07ca06a515baba7239e255498be872ae7e039","coverage":[{"denominator":0,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":93,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":93,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-23T06:30:58.430688+00:00","state":"measured"},{"denominator":93,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":93,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-16T11:25:20.128414Z","state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":1,"source":"pith","source_observed_at":"2026-08-05T02:28:24.338817Z","state":"measured"}],"external_citation_measurements":[{"count":24,"observed_at":"2026-08-05T02:28:24.338817Z","source":"pith"}],"inbound":[{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-12T15:23:21.447889Z","title":"Chipnemo: Domain- adapted llms for chip design,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2411.14299","last_updated":"2025-03-23T15:39:58Z","snapshot_observed_at":"2026-08-20T15:33:14.479110Z","submitted_at":"2024-11-21T16:50:11Z","title":"Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI","version":5},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-08-12T15:23:21.447889Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2411.14299"},"observation_digest":"sha256:e765fe4fc76cc00a2301919cc4fa6de5865f1ed5f356799f6a116d5df5f0ca25","observation_id":"b6d336b3-521b-45d0-8144-683e7477d087","resolution":{"observed_at":"2026-08-12T15:23:21.447889Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-12T13:36:12.198483Z","title":"Chipnemo: Domain- adapted llms for chip design,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2411.16111","last_updated":"2024-11-25T05:54:06Z","snapshot_observed_at":"2026-08-19T13:45:26.034797Z","submitted_at":"2024-11-25T05:54:06Z","title":"LLMPirate: LLMs for Black-box Hardware IP Piracy","version":1},"reference_index":43,"source":"pdf_text","source_observed_at":"2026-08-12T13:36:12.198483Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2411.16111"},"observation_digest":"sha256:9c014f806b7eb5b76ce9695fc3f051fe2bdf10d316c45cedda42b5aae44c9154","observation_id":"f86c49c3-8d57-4394-96a0-ab935dad1735","resolution":{"observed_at":"2026-08-12T13:36:12.198483Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-12T13:27:04.804481Z","title":"Chipnemo: Domain- adapted llms for chip design,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2411.16238","last_updated":"2024-11-25T09:53:35Z","snapshot_observed_at":"2026-08-17T16:47:24.700702Z","submitted_at":"2024-11-25T09:53:35Z","title":"UVLLM: An Automated Universal RTL Verification Framework using LLMs","version":1},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-08-12T13:27:04.804481Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2411.16238"},"observation_digest":"sha256:72bfed9dcc9f02b8ee59f1162702a5ddab39ca75e3d6da4a6497b12b5146df52","observation_id":"a35e97b2-b227-45f4-9410-4dbc401856be","resolution":{"observed_at":"2026-08-12T13:27:04.804481Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-12T12:02:46.919710Z","title":"Chipnemo: Domain-adapted llms for chip design,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2411.17569","last_updated":"2024-12-13T15:36:48Z","snapshot_observed_at":"2026-08-16T12:08:57.392014Z","submitted_at":"2024-11-26T16:31:18Z","title":"RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generation","version":2},"reference_index":12,"source":"pdf_text","source_observed_at":"2026-08-12T12:02:46.919710Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2411.17569"},"observation_digest":"sha256:7386219fef7671f1f48e2ae00359b7abe812a2455fb3b1826de4d3ecafc2988b","observation_id":"0f856dad-4210-4b13-aeb9-3788326bbb81","resolution":{"observed_at":"2026-08-12T12:02:46.919710Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-12T15:59:15.114765Z","title":"Chipnemo: Domain-adapted llms for chip design,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2412.04485","last_updated":"2024-11-21T00:37:51Z","snapshot_observed_at":"2026-08-15T22:07:01.105247Z","submitted_at":"2024-11-21T00:37:51Z","title":"EDA-Aware RTL Generation with Large Language Models","version":1},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-08-12T15:59:15.114765Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2412.04485"},"observation_digest":"sha256:8597ab51b6b3ed3401752a50ec031fffe016a1fcfbf0482477da93a6422e193c","observation_id":"6a8715f4-247b-4cb1-882e-89e95fe28e39","resolution":{"observed_at":"2026-08-12T15:59:15.114765Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-11T20:31:11.764727Z","title":null,"venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2412.05708","last_updated":"2024-12-07T17:43:21Z","snapshot_observed_at":"2026-08-17T13:14:38.853412Z","submitted_at":"2024-12-07T17:43:21Z","title":"On the effective transfer of knowledge from English to Hindi Wikipedia","version":1},"reference_index":19,"source":"arxiv_source","source_observed_at":"2026-08-11T20:31:11.764727Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2412.05708"},"observation_digest":"sha256:515fbff7b1f80de6446a6671f8dd7556154ed7acfc724bff8983f3d5bdf91f48","observation_id":"f86b032e-1460-4747-ba9e-8c698f476e09","resolution":{"observed_at":"2026-08-11T20:31:11.764727Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-11T18:27:06.432372Z","title":"ChipNemo: Domain- adapted LLMs for chip design,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2412.07822","last_updated":"2024-12-10T21:53:55Z","snapshot_observed_at":"2026-08-18T10:36:03.059650Z","submitted_at":"2024-12-10T21:53:55Z","title":"MAGE: A Multi-Agent Engine for Automated RTL Code Generation","version":1},"reference_index":16,"source":"pdf_text","source_observed_at":"2026-08-11T18:27:06.432372Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2412.07822"},"observation_digest":"sha256:d81096469328ed9ae9fe0a5fa84ae0aa8dd3f718213ebc29a377fe9131083765","observation_id":"ad7fcee6-a5fa-46a6-946d-54650ab88aa3","resolution":{"observed_at":"2026-08-11T18:27:06.432372Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-11T17:48:03.203278Z","title":"Suthar, Varun Tej, Kaizhe Xu, and Haoxing Ren","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2412.08490","last_updated":"2024-12-11T15:54:33Z","snapshot_observed_at":"2026-08-15T07:43:26.279351Z","submitted_at":"2024-12-11T15:54:33Z","title":"SuperCode: Sustainability PER AI-driven CO-DEsign","version":1},"reference_index":34,"source":"pdf_text","source_observed_at":"2026-08-11T17:48:03.203278Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2412.08490"},"observation_digest":"sha256:317e795b6361460cb704ed757b44336ca089cdfc2cb968f9fc42dd33dcd98f8b","observation_id":"4c8e6db9-34fd-4c99-91bc-b58c324dc9e4","resolution":{"observed_at":"2026-08-11T17:48:03.203278Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-11T16:50:14.685619Z","title":"Chipnemo: Domain- adapted llms for chip design,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2412.09745","last_updated":"2024-12-12T22:28:03Z","snapshot_observed_at":"2026-08-16T21:50:29.855707Z","submitted_at":"2024-12-12T22:28:03Z","title":"AiEDA: Agentic AI Design Framework for Digital ASIC System Design","version":1},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-08-11T16:50:14.685619Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2412.09745"},"observation_digest":"sha256:9b779a3ac46c040a38b144ab4ff7ab3efcee8b34c3084b130ad39460ed70c499","observation_id":"658c4514-8baa-4bd5-91b8-e4ec9f3c2d3a","resolution":{"observed_at":"2026-08-11T16:50:14.685619Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-11T15:27:03.572868Z","title":null,"venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2412.11014","last_updated":"2025-06-06T01:25:37Z","snapshot_observed_at":"2026-08-20T21:49:14.436620Z","submitted_at":"2024-12-15T01:58:10Z","title":"CoopetitiveV: Leveraging LLM-powered Coopetitive Multi-Agent Prompting for High-quality Verilog Generation","version":2},"reference_index":14,"source":"arxiv_source","source_observed_at":"2026-08-11T15:27:03.572868Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2412.11014"},"observation_digest":"sha256:8eef448d2a86ad210060e610c06b496f73b17507c9a47393cca491fe5c74eeeb","observation_id":"e4d67d81-b126-4820-9134-ca2d5c7d1b00","resolution":{"observed_at":"2026-08-11T15:27:03.572868Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-11T11:04:15.896116Z","title":null,"venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2412.15891","last_updated":"2024-12-20T13:47:02Z","snapshot_observed_at":"2026-08-11T15:11:14.947889Z","submitted_at":"2024-12-20T13:47:02Z","title":"TelcoLM: collecting data, adapting, and benchmarking language models for the telecommunication domain","version":1},"reference_index":25,"source":"arxiv_source","source_observed_at":"2026-08-11T11:04:15.896116Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2412.15891"},"observation_digest":"sha256:79deb1df2e4c90e6d287c2c5e55b56de565b49d5cee6fbeda0668aa97338c768","observation_id":"daefe541-683d-46de-b032-2710c7e42a3c","resolution":{"observed_at":"2026-08-11T11:04:15.896116Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-11T15:25:11.078920Z","title":"Chipnemo: Domain-adapted llms for chip design","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2412.19819","last_updated":"2025-07-15T21:47:40Z","snapshot_observed_at":"2026-08-19T08:36:13.184056Z","submitted_at":"2024-12-15T04:21:24Z","title":"ChipAlign: Instruction Alignment in Large Language Models for Chip Design via Geodesic Interpolation","version":2},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-08-11T15:25:11.078920Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2412.19819"},"observation_digest":"sha256:85a9e18d9a956ee1a8305d85ffe56537c6d7bef627f0bfafeb2a8c0a0440a958","observation_id":"34b0e947-1c03-494f-84a2-15495c6af29d","resolution":{"observed_at":"2026-08-11T15:25:11.078920Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-10T23:11:12.732955Z","title":"Chipnemo: Domain- adapted llms for chip design,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2412.20954","last_updated":"2025-01-21T08:38:01Z","snapshot_observed_at":"2026-08-14T22:08:04.437821Z","submitted_at":"2024-12-30T13:50:20Z","title":"AGON: Automated Design Framework for Customizing Processors from ISA Documents","version":2},"reference_index":50,"source":"pdf_text","source_observed_at":"2026-08-10T23:11:12.732955Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2412.20954"},"observation_digest":"sha256:8762e6e5fd3ea2ff1f41c674f1c6c425a5b90e60df8db88c7e2a8f39cb30435f","observation_id":"b4a34495-09aa-498c-b691-042258fa2f7c","resolution":{"observed_at":"2026-08-10T23:11:12.732955Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-10T21:26:20.578132Z","title":"Chipnemo: Domain-adapted llms for chip design,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2501.04908","last_updated":"2025-01-09T01:47:41Z","snapshot_observed_at":"2026-08-12T10:00:40.188983Z","submitted_at":"2025-01-09T01:47:41Z","title":"HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineers","version":1},"reference_index":30,"source":"pdf_text","source_observed_at":"2026-08-10T21:26:20.578132Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2501.04908"},"observation_digest":"sha256:0c77762db7a941e91456c19d091ffc2344f942cc215dd11dad440888d2ec4a8a","observation_id":"734068f0-e1d5-4a51-bc6c-b44eb7b2e300","resolution":{"observed_at":"2026-08-10T21:26:20.578132Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-10T19:49:55.580207Z","title":null,"venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2501.09655","last_updated":"2025-01-16T16:51:59Z","snapshot_observed_at":"2026-08-17T13:09:52.130334Z","submitted_at":"2025-01-16T16:51:59Z","title":"A Survey of Research in Large Language Models for Electronic Design Automation","version":1},"reference_index":33,"source":"pdf_text","source_observed_at":"2026-08-10T19:49:55.580207Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2501.09655"},"observation_digest":"sha256:3bf0acd22dfcb369deddc61da5508173e355b6e7d46dfa1384dd3e9ebebe8b79","observation_id":"6cd2a899-aee2-4558-a0d8-745fe79052a0","resolution":{"observed_at":"2026-08-10T19:49:55.580207Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-10T16:56:24.934730Z","title":"ChipNeMo: Domain- adapted llms for chip design,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2501.12702","last_updated":"2025-01-22T08:18:37Z","snapshot_observed_at":"2026-08-15T04:36:43.824536Z","submitted_at":"2025-01-22T08:18:37Z","title":"Paradigm-Based Automatic HDL Code Generation Using LLMs","version":1},"reference_index":13,"source":"pdf_text","source_observed_at":"2026-08-10T16:56:24.934730Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2501.12702"},"observation_digest":"sha256:6576f64040a96a5912ed82c89642679553578ac9c77fdafb7150938fa30a32fa","observation_id":"048ec5db-0bc3-4810-9337-7d7c54c608c7","resolution":{"observed_at":"2026-08-10T16:56:24.934730Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-10T16:58:06.912772Z","title":"Liu et al","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2502.00028","last_updated":"2025-01-22T08:36:29Z","snapshot_observed_at":"2026-08-15T15:01:17.903365Z","submitted_at":"2025-01-22T08:36:29Z","title":"VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency","version":1},"reference_index":13,"source":"pdf_text","source_observed_at":"2026-08-10T16:58:06.912772Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2502.00028"},"observation_digest":"sha256:4ed75a94c2a4f468ab17b9718b25c2bb76a7c22be9a0b9ffee1c0a10847e3df2","observation_id":"c68d8d40-6e50-4334-8b9f-157d47d58147","resolution":{"observed_at":"2026-08-10T16:58:06.912772Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-16T11:25:20.128414Z","title":"Chipnemo: Domain- adapted llms for chip design,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2504.15659","last_updated":"2025-08-24T19:32:34Z","snapshot_observed_at":"2026-08-17T20:04:15.047150Z","submitted_at":"2025-04-22T07:32:46Z","title":"VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validation","version":2},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-08-16T11:25:20.128414Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2504.15659"},"observation_digest":"sha256:72e00167cabac53f1846692f5956be56706cbb96d56ecf653277c6f0d2af88b9","observation_id":"5a7f2889-c2de-49ff-a6dd-4d55e3186ec1","resolution":{"observed_at":"2026-08-16T11:25:20.128414Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-16T05:29:32.601505Z","title":"arXiv preprint arXiv:2311.00176 (2023)","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2504.20653","last_updated":"2026-06-30T07:17:34Z","snapshot_observed_at":"2026-08-16T05:21:22.243406Z","submitted_at":"2025-04-29T11:22:06Z","title":"SysVCoder: An LLM-Driven Framework for Systematic Generation of System-Level Design","version":3},"reference_index":8,"source":"pdf_text","source_observed_at":"2026-08-16T05:29:32.601505Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2504.20653"},"observation_digest":"sha256:f17263dc909b01f857b01d78747196c16e50890757e5dc3c2fbb548f08080bf4","observation_id":"18d48241-51c3-4295-bb3f-7e1cd1abe029","resolution":{"observed_at":"2026-08-16T05:29:32.601505Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-16T01:04:34.105269Z","title":"Chipnemo: Domain-adapted LLMs for chip design,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2505.02105","last_updated":"2025-05-04T13:18:58Z","snapshot_observed_at":"2026-08-16T00:59:06.455710Z","submitted_at":"2025-05-04T13:18:58Z","title":"Deep Representation Learning for Electronic Design Automation","version":1},"reference_index":52,"source":"pdf_text","source_observed_at":"2026-08-16T01:04:34.105269Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2505.02105"},"observation_digest":"sha256:a4182ecfb6f397bba0f95b92e35512b5e2c98b260edbaae79105485feb7c3052","observation_id":"4aa35965-42a3-417f-992d-d0c4d8bc8a26","resolution":{"observed_at":"2026-08-16T01:04:34.105269Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-15T21:31:23.423752Z","title":"Chipnemo: Domain adapted llms for chip design,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2505.09610","last_updated":"2025-05-14T17:58:40Z","snapshot_observed_at":"2026-08-18T10:00:00.910268Z","submitted_at":"2025-05-14T17:58:40Z","title":"Customizing a Large Language Model for VHDL Design of High-Performance Microprocessors","version":1},"reference_index":3,"source":"pdf_text","source_observed_at":"2026-08-15T21:31:23.423752Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2505.09610"},"observation_digest":"sha256:dcff799e7e3f0fd0d28bc2f66a1c525a795717d2062a79714afed780e4001f46","observation_id":"329d3e58-f3ae-41d8-858c-75595eaf0e6d","resolution":{"observed_at":"2026-08-15T21:31:23.423752Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-15T20:50:02.566968Z","title":"Oberman, Sujeet Omar, Sreedhar Pratty, Jonathan Raiman, Ambar Sarkar, Zhengjiang Shao, Hanfei Sun, Pratik P","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2505.11849","last_updated":"2025-05-17T05:25:01Z","snapshot_observed_at":"2026-08-20T07:52:54.404393Z","submitted_at":"2025-05-17T05:25:01Z","title":"VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation","version":1},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-08-15T20:50:02.566968Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2505.11849"},"observation_digest":"sha256:aa4da5d8905de3069bbd23e912642186d33fa1dbcf0148800c977429314f6fcd","observation_id":"db7dd468-c459-4b4b-92d5-c2bef169f1cd","resolution":{"observed_at":"2026-08-15T20:50:02.566968Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-15T22:36:25.174737Z","title":"Chipnemo: Domain-adapted llms for chip design,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2505.13479","last_updated":"2025-05-11T00:17:26Z","snapshot_observed_at":"2026-08-18T07:29:24.663338Z","submitted_at":"2025-05-11T00:17:26Z","title":"RTL++: Graph-enhanced LLM for RTL Code Generation","version":1},"reference_index":26,"source":"pdf_text","source_observed_at":"2026-08-15T22:36:25.174737Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2505.13479"},"observation_digest":"sha256:bd42ba2d5e5a32644bc7eaa5a7aebc54a64b346f647d52511fc9bd43202dab03","observation_id":"bf4d0259-9c38-4104-9530-139bf18e52e7","resolution":{"observed_at":"2026-08-15T22:36:25.174737Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-07T15:29:58.345442Z","title":"Liu, T.-D","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2505.14978","last_updated":"2025-08-15T23:31:27Z","snapshot_observed_at":"2026-08-13T19:04:03.037878Z","submitted_at":"2025-05-20T23:40:57Z","title":"JARVIS: A Multi-Agent Code Assistant for High-Quality EDA Script Generation","version":2},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-08-07T15:29:58.345442Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2505.14978"},"observation_digest":"sha256:0fe8d5720c8705b169bd1ef2cc699f8c2c9606c9bdc31d2737677fb1cbad2423","observation_id":"c30b3468-dfe9-459f-828e-11caee1e7a4f","resolution":{"observed_at":"2026-08-07T15:29:58.345442Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-07T11:16:39.900583Z","title":"Chipnemo: Domain-adapted llms for chip design","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2506.02929","last_updated":"2025-06-03T14:30:52Z","snapshot_observed_at":"2026-08-19T07:36:10.789989Z","submitted_at":"2025-06-03T14:30:52Z","title":"Large Processor Chip Model","version":1},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-08-07T11:16:39.900583Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2506.02929"},"observation_digest":"sha256:63901cf0bbd6af33c6adb63fc85350602cfb19d669835e36a8b47abfb4c74579","observation_id":"1efcae57-5a48-4b53-8288-8174b3c25b30","resolution":{"observed_at":"2026-08-07T11:16:39.900583Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-07T10:34:04.390109Z","title":"Chipnemo: Domain- adapted llms for chip design,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2506.05007","last_updated":"2025-06-05T13:17:50Z","snapshot_observed_at":"2026-08-13T19:04:03.997216Z","submitted_at":"2025-06-05T13:17:50Z","title":"QiMeng: Fully Automated Hardware and Software Design for Processor Chip","version":1},"reference_index":40,"source":"pdf_text","source_observed_at":"2026-08-07T10:34:04.390109Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2506.05007"},"observation_digest":"sha256:66697ec2375e239a5b252f22795f29412eec01df3c4c2d1afc13a6d69e8024e5","observation_id":"8709c41c-5ea0-4614-841a-2f1e946dd382","resolution":{"observed_at":"2026-08-07T10:34:04.390109Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-07T05:58:41.255690Z","title":"Chipnemo: Domain- adapted llms for chip design,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2506.06500","last_updated":"2025-06-06T19:50:51Z","snapshot_observed_at":"2026-08-14T14:30:36.556918Z","submitted_at":"2025-06-06T19:50:51Z","title":"Improving LLM-Powered EDA Assistants with RAFT","version":1},"reference_index":3,"source":"pdf_text","source_observed_at":"2026-08-07T05:58:41.255690Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2506.06500"},"observation_digest":"sha256:7ef015638bec0c27ae4df4a144d48932ac52c2a44307ae033aef91bd2d78b2d0","observation_id":"16f06fc9-3bf9-4abd-8f94-6422c7a6a43f","resolution":{"observed_at":"2026-08-07T05:58:41.255690Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":"2311.00176","doi":"10.48550/arxiv.2311.00176","metadata_source":"pith","pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"Liu, T.-D","venue":"cs.CL","work_id":"74982c93-ddcb-4766-ac17-f5a05c462de7","year":2023},"citing_paper":{"arxiv_id":"2506.08332","last_updated":"2026-04-30T06:20:26Z","snapshot_observed_at":"2026-08-13T05:01:30.944770Z","submitted_at":"2025-06-10T01:38:57Z","title":"ORFS-agent: Tool-Using Agents for Chip Design Optimization","version":3},"reference_index":34,"source":"pdf_text","source_observed_at":"2026-05-19T11:23:29.010807Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2506.08332"},"observation_digest":"sha256:20e6cc917e0e24ad3530dd5b7a17fa1525b8e1faf78b9a83a435387194d94480","observation_id":"5c463dec-6ff9-4442-ac68-2deabe2ddb34","resolution":{"observed_at":"2026-05-19T11:27:16.033954Z","resolver_source":"arxiv_id","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"crossref_status_cache"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"openalex_status_cache"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-07T00:31:00.534847Z","title":"Chipnemo: Domain- adapted llms for chip design,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2506.13905","last_updated":"2025-09-08T18:17:46Z","snapshot_observed_at":"2026-08-13T17:40:18.739360Z","submitted_at":"2025-06-16T18:33:25Z","title":"Spec2RTL-Agent: Automated Hardware Code Generation from Complex Specifications Using LLM Agent Systems","version":2},"reference_index":19,"source":"pdf_text","source_observed_at":"2026-08-07T00:31:00.534847Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2506.13905"},"observation_digest":"sha256:7d609d058e970e860e3da4859e42d8f33275a1dff1e3267265a4ee5c844901a0","observation_id":"7457b8ea-3bfe-48f0-b7e6-974eca57251e","resolution":{"observed_at":"2026-08-07T00:31:00.534847Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-15T19:55:12.368221Z","title":"Chipnemo: Domain-adapted llms for chip design","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2506.14567","last_updated":"2025-06-17T14:25:32Z","snapshot_observed_at":"2026-08-19T20:55:11.734243Z","submitted_at":"2025-06-17T14:25:32Z","title":"Controlling Context: Generative AI at Work in Integrated Circuit Design and Other High-Precision Domains","version":1},"reference_index":88,"source":"pdf_text","source_observed_at":"2026-08-15T19:55:12.368221Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2506.14567"},"observation_digest":"sha256:fdc26df5463079ae5ba2970dd4aeb94b3c77d099d22ccc94897b8b0f653f25a7","observation_id":"0f9544b8-b7ea-4cf4-9c72-4914bd5024ba","resolution":{"observed_at":"2026-08-15T19:55:12.368221Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-06T23:04:14.214754Z","title":null,"venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2506.19993","last_updated":"2025-06-24T20:27:51Z","snapshot_observed_at":"2026-08-11T04:22:29.804489Z","submitted_at":"2025-06-24T20:27:51Z","title":"CoVE: Compressed Vocabulary Expansion Makes Better LLM-based Recommender Systems","version":1},"reference_index":58,"source":"arxiv_source","source_observed_at":"2026-08-06T23:04:14.214754Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2506.19993"},"observation_digest":"sha256:4f148b1a5a7d80e86027c05579269f12c9c1f1f2122aa73927062992dd67013d","observation_id":"839bcfdf-a8e5-473f-b830-8521ffc9377b","resolution":{"observed_at":"2026-08-06T23:04:14.214754Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-06T16:52:52.921854Z","title":null,"venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2507.12308","last_updated":"2025-07-16T15:05:30Z","snapshot_observed_at":"2026-08-15T03:18:25.186558Z","submitted_at":"2025-07-16T15:05:30Z","title":"Chain-of-Descriptions: Improving Code LLMs for VHDL Code Generation and Summarization","version":1},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-08-06T16:52:52.921854Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2507.12308"},"observation_digest":"sha256:31043d17d599c1462b0af99719d43d2e74cf69b60f3f9d51f700b532e77f05c4","observation_id":"c77d895e-bf08-40f0-9a46-664ca1ce78ac","resolution":{"observed_at":"2026-08-06T16:52:52.921854Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-06T15:51:34.443963Z","title":"Chipnemo: Domain-adapted llms for chip design,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2507.14776","last_updated":"2025-07-20T00:28:55Z","snapshot_observed_at":"2026-08-14T09:41:16.336800Z","submitted_at":"2025-07-20T00:28:55Z","title":"VeriOpt: PPA-Aware High-Quality Verilog Generation via Multi-Role LLMs","version":1},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-08-06T15:51:34.443963Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2507.14776"},"observation_digest":"sha256:eb3697a4639940e6e59b6254cd61593e029c3e08e01b788bc996793c6d19166a","observation_id":"0d275e55-c261-41aa-b739-32a09efee9e5","resolution":{"observed_at":"2026-08-06T15:51:34.443963Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-06T15:46:52.306589Z","title":"Chipnemo: Domain-adapted llms for chip design,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2507.15104","last_updated":"2026-06-15T19:35:17Z","snapshot_observed_at":"2026-08-13T10:11:17.212034Z","submitted_at":"2025-07-20T19:57:07Z","title":"AnalogFed: Privacy-Preserving Discovery of Analog Circuits at Scale with Federated Generative AI","version":2},"reference_index":8,"source":"pdf_text","source_observed_at":"2026-08-06T15:46:52.306589Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2507.15104"},"observation_digest":"sha256:56aa914fc6e8910a1c99442d5f58c6403ae8870d05ad2d43ab51f4f4246c4d45","observation_id":"e3cfb70a-f518-49b2-a5a2-0e6b4e8297e6","resolution":{"observed_at":"2026-08-06T15:46:52.306589Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-06T15:19:52.190982Z","title":"Chipnemo: Domain- adapted llms for chip design,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-17T16:25:09.865664Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":3,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:52.190982Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:f09ab70ec39eb98f80f955c5d7491dab5c9e11b91a7686dbc452bed76a0bed39","observation_id":"f498e9d2-442d-4d49-b3b7-b86199dfd14f","resolution":{"observed_at":"2026-08-06T15:19:52.190982Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-06T15:47:16.050716Z","title":"Chipnemo: Domain- adapted llms for chip design,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2507.16844","last_updated":"2025-07-20T14:52:29Z","snapshot_observed_at":"2026-08-20T12:38:15.228622Z","submitted_at":"2025-07-20T14:52:29Z","title":"TD-Interpreter: Enhancing the Understanding of Timing Diagrams with Visual-Language Learning","version":1},"reference_index":4,"source":"pdf_text","source_observed_at":"2026-08-06T15:47:16.050716Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2507.16844"},"observation_digest":"sha256:6cc64ff330cc761c3a136dfc9aaa66487a6e2ab9957c598f3a621885df817ce4","observation_id":"22a39c2f-567a-43f2-981d-f245ad845bac","resolution":{"observed_at":"2026-08-06T15:47:16.050716Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-06T15:51:16.912733Z","title":"Chipnemo: Domain-adapted llms for chip design,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2507.19525","last_updated":"2025-07-20T05:46:32Z","snapshot_observed_at":"2026-08-19T00:39:42.936329Z","submitted_at":"2025-07-20T05:46:32Z","title":"MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMs","version":1},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-08-06T15:51:16.912733Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2507.19525"},"observation_digest":"sha256:3278523046a250dc2f9265691c05d208003ceab5959fffa5c364f923f13eb82a","observation_id":"a419aeb3-04f8-4616-8ac4-741362428b3c","resolution":{"observed_at":"2026-08-06T15:51:16.912733Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-06T14:21:43.846626Z","title":"Chipnemo: Domain- adapted llms for chip design,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2507.19570","last_updated":"2025-07-25T17:16:26Z","snapshot_observed_at":"2026-08-14T07:27:51.987558Z","submitted_at":"2025-07-25T17:16:26Z","title":"MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization","version":1},"reference_index":12,"source":"pdf_text","source_observed_at":"2026-08-06T14:21:43.846626Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2507.19570"},"observation_digest":"sha256:e35005014c93621f3b900e17c5ae51beddbb52de96cea01f8f231c76c6757d58","observation_id":"080b4bb0-8274-4c8b-a57b-151e6778a486","resolution":{"observed_at":"2026-08-06T14:21:43.846626Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-06T22:33:16.045541Z","title":null,"venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2508.13156","last_updated":"2025-06-26T13:32:25Z","snapshot_observed_at":"2026-08-15T13:37:38.455829Z","submitted_at":"2025-06-26T13:32:25Z","title":"EvoVerilog: Large Langugage Model Assisted Evolution of Verilog Code","version":1},"reference_index":12,"source":"arxiv_source","source_observed_at":"2026-08-06T22:33:16.045541Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2508.13156"},"observation_digest":"sha256:7d70d9843fc46f5e6f3254be0f408c3e0c6141b65b9aef8bcd83f43717e4b871","observation_id":"24b2c6a6-704a-4d0d-ac56-820639849178","resolution":{"observed_at":"2026-08-06T22:33:16.045541Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-15T17:20:07.041839Z","title":"ChipNeMo: Domain-adapted LLMs for chip design,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2508.14123","last_updated":"2025-08-18T18:20:32Z","snapshot_observed_at":"2026-08-17T21:29:54.330521Z","submitted_at":"2025-08-18T18:20:32Z","title":"AI Agents for Photonic Integrated Circuit Design Automation","version":1},"reference_index":24,"source":"pdf_text","source_observed_at":"2026-08-15T17:20:07.041839Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2508.14123"},"observation_digest":"sha256:400d4e0958007f472a1edd78068ab775eb4fa29274b30408215f91cc2b98e844","observation_id":"1c37ef7d-051f-4b90-8f92-b34ed77ba6e7","resolution":{"observed_at":"2026-08-15T17:20:07.041839Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-05T16:28:25.147288Z","title":"Liu et al., ``Chipnemo: Domain-adapted llms for chip design,'' arXiv preprint arXiv:2311.00176, 2023","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2508.18462","last_updated":"2025-08-25T20:20:44Z","snapshot_observed_at":"2026-08-14T17:38:54.470556Z","submitted_at":"2025-08-25T20:20:44Z","title":"VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning","version":1},"reference_index":37,"source":"arxiv_source","source_observed_at":"2026-08-05T16:28:25.147288Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2508.18462"},"observation_digest":"sha256:3b3033ce2fa2a840520e069c4913ddec4fbe2f39a52ec18d254e0523a14ea928","observation_id":"66784273-8fd1-4643-8000-716b39dad172","resolution":{"observed_at":"2026-08-05T16:28:25.147288Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-15T16:57:19.144331Z","title":"Chipnemo: Domain-adapted llms for chip design","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2508.19393","last_updated":"2025-08-26T19:39:10Z","snapshot_observed_at":"2026-08-19T08:44:43.186146Z","submitted_at":"2025-08-26T19:39:10Z","title":"GENIE-ASI: Generative Instruction and Executable Code for Analog Subcircuit Identification","version":1},"reference_index":20,"source":"pdf_text","source_observed_at":"2026-08-15T16:57:19.144331Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2508.19393"},"observation_digest":"sha256:af3349d936d64d8fd5d19f01402d403d6460cab87ac98c6bed6971b108a576ff","observation_id":"0dca62c8-f567-4a86-a3d8-d1f43838059d","resolution":{"observed_at":"2026-08-15T16:57:19.144331Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-05T05:50:29.847849Z","title":"Chipnemo: Domain-adapted llms for chip design,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-17T17:13:21.111218Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":22,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.847849Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:042a0d78ce13f6f4945890ccf7460b2e789e66e6056d985e2c569161e0877151","observation_id":"c732ae9d-b738-4392-908c-b06fd4192373","resolution":{"observed_at":"2026-08-05T05:50:29.847849Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-04T16:31:32.483801Z","title":"Chipnemo: Domain-adapted llms for chip design.arXiv preprint arXiv:2311.00176, 2023","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2509.13557","last_updated":"2026-05-30T18:21:39Z","snapshot_observed_at":"2026-08-16T13:44:23.820672Z","submitted_at":"2025-09-16T21:52:04Z","title":"MACO: A Multi-Agent LLM Framework for Automated CGRA Hardware/Software Co-Design","version":7},"reference_index":24,"source":"pdf_text","source_observed_at":"2026-08-04T16:31:32.483801Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2509.13557"},"observation_digest":"sha256:912e98d55e11917f63602c700db557039f06d2241967cc382f978f701d37c52f","observation_id":"46b5e136-0550-46e8-b01d-d7340d7cce24","resolution":{"observed_at":"2026-08-04T16:31:32.483801Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-02T18:17:31.071509Z","title":"Chipnemo: Domain-adapted llms for chip design","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2603.13767","last_updated":"2026-07-28T10:13:22Z","snapshot_observed_at":"2026-08-14T00:27:21.064754Z","submitted_at":"2026-03-14T05:36:53Z","title":"Retrieve, Schedule, Reflect: LLM Agents for Chip QoR Optimization","version":2},"reference_index":14,"source":"arxiv_source","source_observed_at":"2026-08-02T18:17:31.071509Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2603.13767"},"observation_digest":"sha256:c9ceb3cf2730b65a092e1ce60566966c2c28e4258dc7a6b1713f5f6f06a5ea05","observation_id":"e46a6dd1-4559-4f4e-b119-e62ad1ebbfeb","resolution":{"observed_at":"2026-08-02T18:17:31.071509Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":"2311.00176","doi":"10.48550/arxiv.2311.00176","metadata_source":"pith","pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"Liu, T.-D","venue":"cs.CL","work_id":"74982c93-ddcb-4766-ac17-f5a05c462de7","year":2023},"citing_paper":{"arxiv_id":"2604.03245","last_updated":"2026-07-20T21:40:17Z","snapshot_observed_at":"2026-08-16T19:29:48.345948Z","submitted_at":"2026-03-06T21:41:28Z","title":"FVRuleLearner: Operator-Level Reasoning Tree (Op-Tree)-Based Rules Learning for Formal Verification","version":1},"reference_index":8,"source":"pdf_text","source_observed_at":"2026-05-15T14:31:36.233977Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2604.03245"},"observation_digest":"sha256:eaa1eb352c378ce9def2890f048864dec650ce9cc5ac5ca8811a2b4db4c9031b","observation_id":"7d1f6c68-4538-4543-8d0c-6dfb2caa38e7","resolution":{"observed_at":"2026-05-15T14:35:55.951522Z","resolver_source":"arxiv_id","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"crossref_status_cache"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"openalex_status_cache"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-02T18:43:42.900544Z","title":"Chipnemo: Domain-adapted llms for chip design,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2604.03245","last_updated":"2026-07-20T21:40:17Z","snapshot_observed_at":"2026-08-16T19:29:48.345948Z","submitted_at":"2026-03-06T21:41:28Z","title":"FVRuleLearner: Operator-Level Reasoning Tree (Op-Tree)-Based Rules Learning for Formal Verification","version":2},"reference_index":8,"source":"pdf_text","source_observed_at":"2026-08-02T18:43:42.900544Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2604.03245"},"observation_digest":"sha256:8a6be286384b3020adbcc0093c1ef2666e42f120bc1d480bd89e9622299c6fca","observation_id":"c213a339-dff1-4b2d-8f4e-435b1eb5e232","resolution":{"observed_at":"2026-08-02T18:43:42.900544Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":"2311.00176","doi":"10.48550/arxiv.2311.00176","metadata_source":"pith","pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"Liu, T.-D","venue":"cs.CL","work_id":"74982c93-ddcb-4766-ac17-f5a05c462de7","year":2023},"citing_paper":{"arxiv_id":"2604.05983","last_updated":"2026-04-27T03:24:25Z","snapshot_observed_at":"2026-08-12T22:24:49.120868Z","submitted_at":"2026-04-07T15:12:14Z","title":"Arch: An AI-Native Hardware Description Language for Register-Transfer Clocked Hardware Design","version":3},"reference_index":31,"source":"pdf_text","source_observed_at":"2026-05-10T18:33:01.330543Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2604.05983"},"observation_digest":"sha256:a4a4d20e9c6483c1d114bd9b299c5593da846a31b00322364a0b04f92092d51a","observation_id":"a3feb579-92b8-4431-b723-9a21f1b3ce4e","resolution":{"observed_at":"2026-05-11T00:25:50.584105Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"crossref_status_cache"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"openalex_status_cache"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":"2311.00176","doi":"10.48550/arxiv.2311.00176","metadata_source":"pith","pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"Liu, T.-D","venue":"cs.CL","work_id":"74982c93-ddcb-4766-ac17-f5a05c462de7","year":2023},"citing_paper":{"arxiv_id":"2604.13523","last_updated":"2026-07-12T19:35:34Z","snapshot_observed_at":"2026-08-13T01:40:26.479285Z","submitted_at":"2026-04-15T06:15:56Z","title":"TensorLift: Automatic Extraction of Tensor-Level ISA Semantics from Accelerator RTL via MLIR Semantic Lifting","version":1},"reference_index":30,"source":"pdf_text","source_observed_at":"2026-05-10T12:38:45.687975Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2604.13523"},"observation_digest":"sha256:c93793a22234fc07b0c6315b211f111b90056892d4d1ac4b9c6a6f1273ab8185","observation_id":"91486680-4756-449c-ae9d-756a8a90e57b","resolution":{"observed_at":"2026-05-11T11:46:20.371356Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"crossref_status_cache"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"openalex_status_cache"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":"2311.00176","doi":"10.48550/arxiv.2311.00176","metadata_source":"pith","pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"Liu, T.-D","venue":"cs.CL","work_id":"74982c93-ddcb-4766-ac17-f5a05c462de7","year":2023},"citing_paper":{"arxiv_id":"2604.15001","last_updated":"2026-04-17T09:58:55Z","snapshot_observed_at":"2026-08-21T12:52:06.221487Z","submitted_at":"2026-04-16T13:26:52Z","title":"COEVO: Co-Evolutionary Framework for Joint Functional Correctness and PPA Optimization in LLM-Based RTL Generation","version":2},"reference_index":15,"source":"pdf_text","source_observed_at":"2026-05-10T10:34:03.353104Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2604.15001"},"observation_digest":"sha256:3afb89c03ed111040e9318412bfe1ba514f57290a70202a071cbd9ebc312ace2","observation_id":"ac99d122-614f-4154-9580-2e0a47f7d23a","resolution":{"observed_at":"2026-05-10T10:34:28.877695Z","resolver_source":"arxiv_id","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"crossref_status_cache"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"openalex_status_cache"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":"2311.00176","doi":"10.48550/arxiv.2311.00176","metadata_source":"pith","pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"Liu, T.-D","venue":"cs.CL","work_id":"74982c93-ddcb-4766-ac17-f5a05c462de7","year":2023},"citing_paper":{"arxiv_id":"2604.18834","last_updated":"2026-04-20T20:58:52Z","snapshot_observed_at":"2026-08-14T07:18:30.579258Z","submitted_at":"2026-04-20T20:58:52Z","title":"Structural Verification for Reliable EDA Code Generation without Tool-in-the-Loop Debugging","version":1},"reference_index":10,"source":"arxiv_source","source_observed_at":"2026-05-10T03:52:02.372376Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2604.18834"},"observation_digest":"sha256:9dc3a8e097d483b448fb2a914f23506392c53bb069e91b7a9fdc88cf5889ceef","observation_id":"04db953c-9080-4d9d-b375-be4e50f173a6","resolution":{"observed_at":"2026-05-11T12:21:04.109633Z","resolver_source":"arxiv_id","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"crossref_status_cache"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"openalex_status_cache"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":"2311.00176","doi":"10.48550/arxiv.2311.00176","metadata_source":"pith","pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"Liu, T.-D","venue":"cs.CL","work_id":"74982c93-ddcb-4766-ac17-f5a05c462de7","year":2023},"citing_paper":{"arxiv_id":"2604.21952","last_updated":"2026-04-23T05:27:39Z","snapshot_observed_at":"2026-08-16T07:06:54.874409Z","submitted_at":"2026-04-23T05:27:39Z","title":"Focus Session: Hardware and Software Techniques for Accelerating Multimodal Foundation Models","version":1},"reference_index":57,"source":"pdf_text","source_observed_at":"2026-05-09T23:02:07.554154Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2604.21952"},"observation_digest":"sha256:58d03fb3d0ad3de048300274686049e7f148f3242e03003d8e46351b90aba624","observation_id":"0e41e962-e2af-46d0-9bec-6e9295ce94c7","resolution":{"observed_at":"2026-05-09T23:04:17.786077Z","resolver_source":"arxiv_id","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"crossref_status_cache"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"openalex_status_cache"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":"2311.00176","doi":"10.48550/arxiv.2311.00176","metadata_source":"pith","pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"Liu, T.-D","venue":"cs.CL","work_id":"74982c93-ddcb-4766-ac17-f5a05c462de7","year":2023},"citing_paper":{"arxiv_id":"2604.23355","last_updated":"2026-05-18T06:50:33Z","snapshot_observed_at":"2026-08-15T19:55:12.790664Z","submitted_at":"2026-04-25T15:44:48Z","title":"LEGO: An LLM Skill-Based Front-End Design Generation Platform","version":1},"reference_index":6,"source":"pdf_text","source_observed_at":"2026-05-08T08:22:04.845485Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2604.23355"},"observation_digest":"sha256:83fe0ecf57f973c0485a13b064ca76b860ebf0b004052474e8b3c3e84838e9db","observation_id":"9664b8a5-b618-4d18-8489-6c79b9d2759d","resolution":{"observed_at":"2026-05-11T20:41:10.244597Z","resolver_source":"arxiv_id","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"crossref_status_cache"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"openalex_status_cache"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":"2311.00176","doi":"10.48550/arxiv.2311.00176","metadata_source":"pith","pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"Liu, T.-D","venue":"cs.CL","work_id":"74982c93-ddcb-4766-ac17-f5a05c462de7","year":2023},"citing_paper":{"arxiv_id":"2604.23355","last_updated":"2026-05-18T06:50:33Z","snapshot_observed_at":"2026-08-15T19:55:12.790664Z","submitted_at":"2026-04-25T15:44:48Z","title":"LEGO: An LLM Skill-Based Front-End Design Generation Platform","version":2},"reference_index":6,"source":"pdf_text","source_observed_at":"2026-05-21T09:15:26.963601Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2604.23355"},"observation_digest":"sha256:1bf4751779273b67382038b727d49547ec2c09ee6b4f0ee3638a9760bac2a03f","observation_id":"5a2e03f7-98cf-4f57-9761-2642a53d8e47","resolution":{"observed_at":"2026-05-21T09:19:56.721693Z","resolver_source":"arxiv_id","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"crossref_status_cache"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"openalex_status_cache"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":"2311.00176","doi":"10.48550/arxiv.2311.00176","metadata_source":"pith","pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"Liu, T.-D","venue":"cs.CL","work_id":"74982c93-ddcb-4766-ac17-f5a05c462de7","year":2023},"citing_paper":{"arxiv_id":"2604.23602","last_updated":"2026-04-26T08:29:20Z","snapshot_observed_at":"2026-08-11T01:49:06.235364Z","submitted_at":"2026-04-26T08:29:20Z","title":"TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog","version":1},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-05-08T05:19:55.032967Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2604.23602"},"observation_digest":"sha256:c6d5557dde1a77693a56b96a69d3470cc7951445c85558730f88e1c2ad5802ee","observation_id":"1f92ed4d-c71b-4d86-bd3b-a53e8922a7b4","resolution":{"observed_at":"2026-05-11T21:31:14.800195Z","resolver_source":"arxiv_id","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"crossref_status_cache"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"openalex_status_cache"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":"2311.00176","doi":"10.48550/arxiv.2311.00176","metadata_source":"pith","pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"Liu, T.-D","venue":"cs.CL","work_id":"74982c93-ddcb-4766-ac17-f5a05c462de7","year":2023},"citing_paper":{"arxiv_id":"2604.24218","last_updated":"2026-04-27T09:22:02Z","snapshot_observed_at":"2026-08-15T14:20:02.496765Z","submitted_at":"2026-04-27T09:22:02Z","title":"RefEvo: Agentic Design with Co-Evolutionary Verification for Agile Reference Model Generation","version":1},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-05-08T03:16:00.089055Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2604.24218"},"observation_digest":"sha256:9e7c18cbc1868beaf99febb9fabd924291d3dffde06644ef0599c2561cb6486c","observation_id":"e5110ecb-bac9-48e9-8faf-0e3354783c0e","resolution":{"observed_at":"2026-05-11T22:11:14.596825Z","resolver_source":"arxiv_id","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"crossref_status_cache"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"openalex_status_cache"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":"2311.00176","doi":"10.48550/arxiv.2311.00176","metadata_source":"pith","pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"Liu, T.-D","venue":"cs.CL","work_id":"74982c93-ddcb-4766-ac17-f5a05c462de7","year":2023},"citing_paper":{"arxiv_id":"2604.27415","last_updated":"2026-04-30T04:35:43Z","snapshot_observed_at":"2026-08-08T21:42:05.972268Z","submitted_at":"2026-04-30T04:35:43Z","title":"ChipLingo: A Systematic Training Framework for Large Language Models in EDA","version":1},"reference_index":3,"source":"pdf_text","source_observed_at":"2026-05-07T09:40:25.666277Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2604.27415"},"observation_digest":"sha256:43900b54d85d8eeb5d90311e5801bac25da98e166b301e283c026fd30b20c439","observation_id":"33d57c97-faaf-42bf-ae2b-ccb01156590e","resolution":{"observed_at":"2026-05-12T09:41:27.237981Z","resolver_source":"arxiv_id","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"crossref_status_cache"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"openalex_status_cache"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":"2311.00176","doi":"10.48550/arxiv.2311.00176","metadata_source":"pith","pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"Liu, T.-D","venue":"cs.CL","work_id":"74982c93-ddcb-4766-ac17-f5a05c462de7","year":2023},"citing_paper":{"arxiv_id":"2604.27643","last_updated":"2026-04-30T09:35:32Z","snapshot_observed_at":"2026-08-18T02:51:16.408650Z","submitted_at":"2026-04-30T09:35:32Z","title":"HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs","version":1},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-05-07T05:32:07.097013Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2604.27643"},"observation_digest":"sha256:b9dda745e90078bc6c9402ee3fc08ae808105b014b9030641812d6a1c8a83517","observation_id":"78dc3399-6702-4e22-ae83-99f425bcb586","resolution":{"observed_at":"2026-05-12T10:36:29.744822Z","resolver_source":"arxiv_id","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"crossref_status_cache"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"openalex_status_cache"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":"2311.00176","doi":"10.48550/arxiv.2311.00176","metadata_source":"pith","pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"Liu, T.-D","venue":"cs.CL","work_id":"74982c93-ddcb-4766-ac17-f5a05c462de7","year":2023},"citing_paper":{"arxiv_id":"2605.01338","last_updated":"2026-05-02T09:21:30Z","snapshot_observed_at":"2026-08-13T02:39:25.211742Z","submitted_at":"2026-05-02T09:21:30Z","title":"DiagramNet: An End-to-End Recognition Framework and Dataset for Non-Standard System-Level Diagrams","version":1},"reference_index":13,"source":"arxiv_source","source_observed_at":"2026-05-09T14:37:35.517734Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2605.01338"},"observation_digest":"sha256:1b6adafc777323540e3f1b8860b02e2c3534ad848c865fa52b031860947cb915","observation_id":"200722e7-5f4c-450a-8e8d-b491f732e5f7","resolution":{"observed_at":"2026-05-11T16:51:09.203520Z","resolver_source":"arxiv_id","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"crossref_status_cache"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"openalex_status_cache"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":"2311.00176","doi":"10.48550/arxiv.2311.00176","metadata_source":"pith","pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"Liu, T.-D","venue":"cs.CL","work_id":"74982c93-ddcb-4766-ac17-f5a05c462de7","year":2023},"citing_paper":{"arxiv_id":"2605.06936","last_updated":"2026-07-21T15:06:04Z","snapshot_observed_at":"2026-08-17T16:25:54.034957Z","submitted_at":"2026-05-07T20:54:07Z","title":"Bridging the Last Mile of Circuit Design: PostEDA-Bench, a Hierarchical Benchmark for PPA Convergence and DRC Fixing","version":1},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-05-11T01:01:55.596476Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2605.06936"},"observation_digest":"sha256:8968da79f4a895530e5daf30a92e18321f8dde4b57584e2595a8377ac14ad181","observation_id":"986ac8de-1a2f-47df-961d-9d28d9678af2","resolution":{"observed_at":"2026-05-11T04:50:57.316257Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"crossref_status_cache"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"openalex_status_cache"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":"2311.00176","doi":"10.48550/arxiv.2311.00176","metadata_source":"pith","pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"Liu, T.-D","venue":"cs.CL","work_id":"74982c93-ddcb-4766-ac17-f5a05c462de7","year":2023},"citing_paper":{"arxiv_id":"2605.06936","last_updated":"2026-07-21T15:06:04Z","snapshot_observed_at":"2026-08-17T16:25:54.034957Z","submitted_at":"2026-05-07T20:54:07Z","title":"Bridging the Last Mile of Circuit Design: PostEDA-Bench, a Hierarchical Benchmark for PPA Convergence and DRC Fixing","version":2},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-05-25T06:50:35.571290Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2605.06936"},"observation_digest":"sha256:a83d3b0f11ef796026748279e2199eeffcd3831db24f47cff831eeac75e4b7c6","observation_id":"035b0f39-04e9-4a5d-8e1e-ded8c6be387e","resolution":{"observed_at":"2026-05-25T06:55:26.237713Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"crossref_status_cache"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"openalex_status_cache"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-02T14:44:28.799059Z","title":"Liu, T.-D","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2605.06936","last_updated":"2026-07-21T15:06:04Z","snapshot_observed_at":"2026-08-17T16:25:54.034957Z","submitted_at":"2026-05-07T20:54:07Z","title":"Bridging the Last Mile of Circuit Design: PostEDA-Bench, a Hierarchical Benchmark for PPA Convergence and DRC Fixing","version":3},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-08-02T14:44:28.799059Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2605.06936"},"observation_digest":"sha256:be75c675fdb4b398af2b3e316c5b443d0d023efcac0a3f08ee1f9e8597efd5d3","observation_id":"1495336c-a5c4-43f3-bdc7-610e4a7f074e","resolution":{"observed_at":"2026-08-02T14:44:28.799059Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":"2311.00176","doi":"10.48550/arxiv.2311.00176","metadata_source":"pith","pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"Liu, T.-D","venue":"cs.CL","work_id":"74982c93-ddcb-4766-ac17-f5a05c462de7","year":2023},"citing_paper":{"arxiv_id":"2605.08291","last_updated":"2026-05-08T08:24:33Z","snapshot_observed_at":"2026-08-12T20:32:06.601773Z","submitted_at":"2026-05-08T08:24:33Z","title":"Graph Computation Meets Circuit Algebra: A Task-Aligned Analysis of Graph Neural Networks for Electronic Design Automation","version":1},"reference_index":76,"source":"pdf_text","source_observed_at":"2026-05-12T02:10:57.066057Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2605.08291"},"observation_digest":"sha256:7d4e227d8b17e0938f1796f0feed7d1036a74aaeebd37494ccf9bb9329bdc339","observation_id":"e7cdceb6-a98e-4126-be54-b1a098435483","resolution":{"observed_at":"2026-05-12T02:11:15.322440Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"crossref_status_cache"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"openalex_status_cache"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":"2311.00176","doi":"10.48550/arxiv.2311.00176","metadata_source":"pith","pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"Liu, T.-D","venue":"cs.CL","work_id":"74982c93-ddcb-4766-ac17-f5a05c462de7","year":2023},"citing_paper":{"arxiv_id":"2605.26498","last_updated":"2026-05-26T03:21:32Z","snapshot_observed_at":"2026-08-12T20:33:34.461804Z","submitted_at":"2026-05-26T03:21:32Z","title":"Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation","version":1},"reference_index":4,"source":"pdf_text","source_observed_at":"2026-06-29T18:49:52.243940Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2605.26498"},"observation_digest":"sha256:f7cbbece901990274d31a989884ef9dd8140c8d9e0a4c18121fac1057d52b406","observation_id":"6623a9ef-e0bd-4ef8-86b9-4f0ba56022c6","resolution":{"observed_at":"2026-06-29T18:53:51.281060Z","resolver_source":"arxiv_id","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"crossref_status_cache"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"openalex_status_cache"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":"2311.00176","doi":"10.48550/arxiv.2311.00176","metadata_source":"pith","pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"Liu, T.-D","venue":"cs.CL","work_id":"74982c93-ddcb-4766-ac17-f5a05c462de7","year":2023},"citing_paper":{"arxiv_id":"2606.04246","last_updated":"2026-06-02T21:52:48Z","snapshot_observed_at":"2026-08-15T06:49:23.495831Z","submitted_at":"2026-06-02T21:52:48Z","title":"StepPRM-RTL: Stepwise Process-Reward Guided LLM Fine-Tuning for Enhanced RTL Synthesis","version":1},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-06-28T09:35:34.571333Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2606.04246"},"observation_digest":"sha256:201b2c39fc9c5c2eb62dd8b828f38cf47472f0d71384c5ea637652df0a949ef0","observation_id":"4c7e3355-2b0a-43a0-b16f-28a86b689cf6","resolution":{"observed_at":"2026-07-02T03:56:34.641967Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"crossref_status_cache"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"openalex_status_cache"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":"2311.00176","doi":"10.48550/arxiv.2311.00176","metadata_source":"pith","pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"Liu, T.-D","venue":"cs.CL","work_id":"74982c93-ddcb-4766-ac17-f5a05c462de7","year":2023},"citing_paper":{"arxiv_id":"2606.05253","last_updated":"2026-06-03T14:51:33Z","snapshot_observed_at":"2026-08-16T14:55:09.814269Z","submitted_at":"2026-06-03T14:51:33Z","title":"Alpha-RTL: Test-Time Training for RTL Hardware Optimization","version":1},"reference_index":29,"source":"arxiv_source","source_observed_at":"2026-06-28T07:11:52.187869Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2606.05253"},"observation_digest":"sha256:326565b8f4174de8cfc7b5c1a32f35f06226e6fe5e08df7f94b71e4e9f32fe95","observation_id":"552109fe-9bd4-4134-8389-a27fdf4347e1","resolution":{"observed_at":"2026-07-02T07:06:44.160827Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"crossref_status_cache"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"openalex_status_cache"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":"2311.00176","doi":"10.48550/arxiv.2311.00176","metadata_source":"pith","pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"Liu, T.-D","venue":"cs.CL","work_id":"74982c93-ddcb-4766-ac17-f5a05c462de7","year":2023},"citing_paper":{"arxiv_id":"2606.07521","last_updated":"2026-04-19T16:03:11Z","snapshot_observed_at":"2026-08-14T11:19:38.455756Z","submitted_at":"2026-04-19T16:03:11Z","title":"Evaluating Hallucinations in Domain-Adapted Large Language Models","version":1},"reference_index":11,"source":"arxiv_source","source_observed_at":"2026-07-05T17:15:33.341956Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2606.07521"},"observation_digest":"sha256:d3b1ed71f2485057410f1463efc775d0bed846c95a67b09cf800f564013236be","observation_id":"fcd90944-e598-4d1f-9718-de958251cfdd","resolution":{"observed_at":"2026-07-05T17:21:18.073391Z","resolver_source":"local_arxiv","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"crossref_status_cache"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"openalex_status_cache"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":"2311.00176","doi":"10.48550/arxiv.2311.00176","metadata_source":"pith","pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"Liu, T.-D","venue":"cs.CL","work_id":"74982c93-ddcb-4766-ac17-f5a05c462de7","year":2023},"citing_paper":{"arxiv_id":"2606.11247","last_updated":"2026-06-08T07:06:11Z","snapshot_observed_at":"2026-08-15T07:17:39.207943Z","submitted_at":"2026-06-08T07:06:11Z","title":"Physics-informed generative AI for semiconductor manufacturing: Enforcing hard physical constraints in generative models by construction","version":1},"reference_index":30,"source":"pdf_text","source_observed_at":"2026-06-27T17:35:41.070876Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2606.11247"},"observation_digest":"sha256:d18dc97800005b01bc2136ea6dba1954f2ca11f65cb2de06e47489a1bb2b327f","observation_id":"f6acce64-0037-445b-a8fb-d91692b6fa23","resolution":{"observed_at":"2026-07-02T23:57:28.982890Z","resolver_source":"arxiv_id","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"crossref_status_cache"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"openalex_status_cache"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":"2311.00176","doi":"10.48550/arxiv.2311.00176","metadata_source":"pith","pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"Liu, T.-D","venue":"cs.CL","work_id":"74982c93-ddcb-4766-ac17-f5a05c462de7","year":2023},"citing_paper":{"arxiv_id":"2606.12683","last_updated":"2026-06-10T21:14:10Z","snapshot_observed_at":"2026-08-17T05:56:28.912396Z","submitted_at":"2026-06-10T21:14:10Z","title":"From AGI to ASI","version":1},"reference_index":5,"source":"pdf_text","source_observed_at":"2026-06-27T09:44:53.656543Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2606.12683"},"observation_digest":"sha256:e2b26297d55f5435a55e41bb798bbed9e6f07ac79184c96fe8ef76a77eae31fb","observation_id":"edc77d70-1aa2-4aa6-b30c-2f861a487335","resolution":{"observed_at":"2026-06-27T09:50:48.675786Z","resolver_source":"arxiv_id","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"crossref_status_cache"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"openalex_status_cache"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":"2311.00176","doi":"10.48550/arxiv.2311.00176","metadata_source":"pith","pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"Liu, T.-D","venue":"cs.CL","work_id":"74982c93-ddcb-4766-ac17-f5a05c462de7","year":2023},"citing_paper":{"arxiv_id":"2606.17253","last_updated":"2026-06-15T19:54:57Z","snapshot_observed_at":"2026-08-16T23:39:09.214827Z","submitted_at":"2026-06-15T19:54:57Z","title":"PDAGENT-BENCH: Characterizing, Grounding, and Architecting LLM Agents for VLSI Physical Design","version":1},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-06-27T02:11:34.174504Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2606.17253"},"observation_digest":"sha256:88baac67194ada17e29849f3a46e5ef3718e338b0ab980556d9cecccd16ae63b","observation_id":"0ba6fd65-f87f-4c54-8aaf-d70e30437568","resolution":{"observed_at":"2026-07-03T19:08:49.838744Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"crossref_status_cache"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"openalex_status_cache"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":"2311.00176","doi":"10.48550/arxiv.2311.00176","metadata_source":"pith","pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"Liu, T.-D","venue":"cs.CL","work_id":"74982c93-ddcb-4766-ac17-f5a05c462de7","year":2023},"citing_paper":{"arxiv_id":"2606.21836","last_updated":"2026-06-20T02:08:52Z","snapshot_observed_at":"2026-08-21T13:29:24.025662Z","submitted_at":"2026-06-20T02:08:52Z","title":"AgentDSE: Reasoning-Augmented Architectural Design Space Exploration","version":1},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-06-26T11:31:41.471831Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2606.21836"},"observation_digest":"sha256:5c226eca0909afff14aaac8afb199fb246750abacf0bd4bdede63c6de9dc2999","observation_id":"b0d3310d-f243-48a5-88f7-9931cd09ae5b","resolution":{"observed_at":"2026-07-04T08:29:42.245159Z","resolver_source":"arxiv_id","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"crossref_status_cache"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"openalex_status_cache"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-07-12T00:33:59.659330Z","title":null,"venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2607.03701","last_updated":"2026-07-04T04:37:57Z","snapshot_observed_at":"2026-08-16T22:27:56.189581Z","submitted_at":"2026-07-04T04:37:57Z","title":"SABLE: An NDA-Safe Closed-Loop LLM Framework for Analog Circuit Optimization in Industrial EDA Flows","version":1},"reference_index":11,"source":"pdf_text","source_observed_at":"2026-07-12T00:33:59.659330Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2607.03701"},"observation_digest":"sha256:1c858a217b15dfe53e553d4622d548b335c37de072023320739920ef6da27e59","observation_id":"2e99f962-bd86-4a03-91f1-7c8396d4917d","resolution":{"observed_at":"2026-07-12T00:33:59.659330Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":"2311.00176","doi":"10.48550/arxiv.2311.00176","metadata_source":"pith","pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"Liu, T.-D","venue":"cs.CL","work_id":"74982c93-ddcb-4766-ac17-f5a05c462de7","year":2023},"citing_paper":{"arxiv_id":"2607.05915","last_updated":"2026-08-03T09:30:57Z","snapshot_observed_at":"2026-08-14T10:45:20.885322Z","submitted_at":"2026-07-07T07:09:46Z","title":"PCBWorld: A Benchmark Environment for Engine-Grounded PCB Design Automation","version":1},"reference_index":48,"source":"pdf_text","source_observed_at":"2026-07-08T21:09:25.719945Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2607.05915"},"observation_digest":"sha256:24c3c9ac90098b578ba55d54a3bbfb0e5be19df6508acb51e6591aa866a880b7","observation_id":"d942894e-6ea3-4f31-aa13-451918a8bafa","resolution":{"observed_at":"2026-07-08T21:15:39.006302Z","resolver_source":"local_arxiv","status":"metadata_mismatch"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-23T06:30:58.430688+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"crossref_status_cache"},{"observed_at":"2026-08-06T23:08:11.154462+00:00","source":"openalex_status_cache"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-04T04:32:27.701483Z","title":"Suthar, Varun Tej, Walker Turner, Kaizhe Xu, and Haoxing Ren","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2607.05915","last_updated":"2026-08-03T09:30:57Z","snapshot_observed_at":"2026-08-14T10:45:20.885322Z","submitted_at":"2026-07-07T07:09:46Z","title":"PCBWorld: A Benchmark Environment for Engine-Grounded PCB Design Automation","version":2},"reference_index":36,"source":"pdf_text","source_observed_at":"2026-08-04T04:32:27.701483Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2607.05915"},"observation_digest":"sha256:328cffab9c216a197431902ad97ee91be74fce5c8e9c92b6cf6fd6e974a2f3f4","observation_id":"b7f8512d-87da-4ed7-b774-d2ac7fea0ba8","resolution":{"observed_at":"2026-08-04T04:32:27.701483Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-07-13T01:43:21.579040Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2607.09616","last_updated":"2026-07-10T17:15:54Z","snapshot_observed_at":"2026-08-08T18:56:16.949948Z","submitted_at":"2026-07-10T17:15:54Z","title":"LLM for EDA in Front-End Design: Challenges and Opportunities","version":1},"reference_index":2,"source":"pdf_text","source_observed_at":"2026-07-13T01:43:21.579040Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2607.09616"},"observation_digest":"sha256:4b37e20b391892450ffa3ba64f2c47686d079877a37cf9cff3ecbc06a2c09fb3","observation_id":"9485b45d-8e27-40a5-82ab-39aa169926c7","resolution":{"observed_at":"2026-07-13T01:43:21.579040Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-07-14T00:43:41.682200Z","title":"Liu et al","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2607.10057","last_updated":"2026-07-11T00:54:52Z","snapshot_observed_at":"2026-08-16T18:14:29.426615Z","submitted_at":"2026-07-11T00:54:52Z","title":"Quantum Circuit Vision: Cost-Aware Evaluation of Visual AI Agents for Quantum Code Generation","version":1},"reference_index":25,"source":"pdf_text","source_observed_at":"2026-07-14T00:43:41.682200Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2607.10057"},"observation_digest":"sha256:e63969b6df148b5994e4416106844409bebec17fdba4c81f74de154df157e2e7","observation_id":"95bea97d-52a7-43d8-8ce7-b24173f256e2","resolution":{"observed_at":"2026-07-14T00:43:41.682200Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-02T05:12:20.243527Z","title":"Chipnemo: Domain-adapted llms for chip design,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2607.14165","last_updated":"2026-07-15T05:19:35Z","snapshot_observed_at":"2026-08-02T10:40:59.594748Z","submitted_at":"2026-07-15T05:19:35Z","title":"Towards Reliable AI-Assisted Analog Design: Template-Constrained LLM Agents for SAR ADC Generation","version":1},"reference_index":4,"source":"pdf_text","source_observed_at":"2026-08-02T05:12:20.243527Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2607.14165"},"observation_digest":"sha256:c5ea9cade74cb5394ad86072f8276b88a621e79c3594a829f56804dc94bd9424","observation_id":"ef7842fe-968d-4e3c-8dd3-eaaa7d713a5d","resolution":{"observed_at":"2026-08-02T05:12:20.243527Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-01T15:13:01.763198Z","title":"ChipNeMo: Domain-adapted LLMs for chip design","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2607.18536","last_updated":"2026-07-20T22:02:22Z","snapshot_observed_at":"2026-08-16T09:41:43.436322Z","submitted_at":"2026-07-20T22:02:22Z","title":"MAGE: Human-Like Macro Placement via Agentic Multimodal Reasoning","version":1},"reference_index":37,"source":"pdf_text","source_observed_at":"2026-08-01T15:13:01.763198Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2607.18536"},"observation_digest":"sha256:f302f3a434b03b938f048ad0e420bda821251ea7afda3ea9577fd72ec0c4048a","observation_id":"b453e823-35d9-4085-bc38-c69922c78be9","resolution":{"observed_at":"2026-08-01T15:13:01.763198Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-01T14:27:13.511460Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2607.18772","last_updated":"2026-07-21T06:53:09Z","snapshot_observed_at":"2026-08-09T04:18:05.685307Z","submitted_at":"2026-07-21T06:53:09Z","title":"RF-Agent: A Practical Framework for Building Language Agents for RFIC Design","version":1},"reference_index":12,"source":"pdf_text","source_observed_at":"2026-08-01T14:27:13.511460Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2607.18772"},"observation_digest":"sha256:11ea815960f0d3116bbc48b4712d287570ecd5c616b99f2532bc3050d7f4fb93","observation_id":"13c02990-6943-4398-8a6e-a921cb4ec70a","resolution":{"observed_at":"2026-08-01T14:27:13.511460Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-01T11:48:46.331011Z","title":"arXiv preprint arXiv:2311.00176 , year=","venue":null,"work_id":null,"year":null},"citing_paper":{"arxiv_id":"2607.19767","last_updated":"2026-07-22T05:27:30Z","snapshot_observed_at":"2026-08-16T09:37:32.742039Z","submitted_at":"2026-07-22T05:27:30Z","title":"Symbol and Footprint Database for Electronic Components by Agentic Recognition and Generation","version":1},"reference_index":29,"source":"arxiv_source","source_observed_at":"2026-08-01T11:48:46.331011Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2607.19767"},"observation_digest":"sha256:ec7deea1b4d341859b587347bc90031c3c9965adae1e4f2c11b1107c613dfecb","observation_id":"d5f0c0ab-79a6-4309-a5da-e00ae4c4feb4","resolution":{"observed_at":"2026-08-01T11:48:46.331011Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-01T06:36:59.134968Z","title":"Chipnemo: Domain-adapted llms for chip design,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2607.21850","last_updated":"2026-07-23T22:38:04Z","snapshot_observed_at":"2026-08-18T00:49:10.796519Z","submitted_at":"2026-07-23T22:38:04Z","title":"SCALE: Self-Supervised Constraint-Aware Layout GEneration for Local P&R DRV Fixing at Advanced Nodes","version":1},"reference_index":11,"source":"pdf_text","source_observed_at":"2026-08-01T06:36:59.134968Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2607.21850"},"observation_digest":"sha256:bb7dfcbf198d0405a4eebc1a4c2363ecebba937f5df90cdb40ede2d39fb4aa06","observation_id":"4c3f1343-d94d-4624-a3ef-712a6308ed92","resolution":{"observed_at":"2026-08-01T06:36:59.134968Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-01T06:38:42.228129Z","title":null,"venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2607.22761","last_updated":"2026-07-23T21:22:36Z","snapshot_observed_at":"2026-08-17T03:28:04.627442Z","submitted_at":"2026-07-23T21:22:36Z","title":"DRC-Aid: Design-Rule Correction via Agentic Framework utilizing Inference-Time Large Language Models","version":1},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-08-01T06:38:42.228129Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2607.22761"},"observation_digest":"sha256:0046452b39294fd8192201984cd915f9a4894f2a28b9f55bd6973c3dc3e015b9","observation_id":"2c39ef54-712d-47ff-bb08-26fe3cdac384","resolution":{"observed_at":"2026-08-01T06:38:42.228129Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-01T02:55:32.794380Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2607.25283","last_updated":"2026-07-28T04:41:13Z","snapshot_observed_at":"2026-08-13T19:04:41.405021Z","submitted_at":"2026-07-28T04:41:13Z","title":"ContractHIL-HLS: Contract-Aligned Multi-Agent Workflow with Hardware-in-the-Loop Feedback for HLS Design","version":1},"reference_index":13,"source":"pdf_text","source_observed_at":"2026-08-01T02:55:32.794380Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2607.25283"},"observation_digest":"sha256:6ac8e513e9cb19170a7dbaeea7a078e26bb5e4aee11c5b94a56ee9d5e8a1ad4d","observation_id":"a95d31db-4cbd-4f22-ac8b-00f65cc41dcb","resolution":{"observed_at":"2026-08-01T02:55:32.794380Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-07-31T23:48:04.702842Z","title":null,"venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2607.27879","last_updated":"2026-07-30T08:53:32Z","snapshot_observed_at":"2026-08-19T17:54:16.852437Z","submitted_at":"2026-07-30T08:53:32Z","title":"ARES: Adaptive Reasoning-Effort Steering for PPA- and Cost-Aware RTL Optimization with LLM Agents","version":1},"reference_index":16,"source":"pdf_text","source_observed_at":"2026-07-31T23:48:04.702842Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2607.27879"},"observation_digest":"sha256:0f51a4aadabf6139e45f2c9f20994c5c13e7e50e662f60c0076cf862ca2463fc","observation_id":"e6aa986e-093a-44d1-80d9-3bb422714b44","resolution":{"observed_at":"2026-07-31T23:48:04.702842Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-06T00:45:24.542140Z","title":"CoRR , volume =","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2608.00909","last_updated":"2026-08-02T00:30:13Z","snapshot_observed_at":"2026-08-16T21:52:09.512119Z","submitted_at":"2026-08-02T00:30:13Z","title":"FinHardBench: Can LLMs Generate Latency-Aware Hardware for Financial Computing?","version":1},"reference_index":23,"source":"arxiv_source","source_observed_at":"2026-08-06T00:45:24.542140Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2608.00909"},"observation_digest":"sha256:9c1a04c80ea866e44ecbc35834da3bdf678b491755c2706e16e9ec4e7daa5651","observation_id":"e3a642ab-b41d-4ecd-93d2-3edef7f48e43","resolution":{"observed_at":"2026-08-06T00:45:24.542140Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-04T20:50:44.998646Z","title":null,"venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2608.01791","last_updated":"2026-08-06T01:35:04Z","snapshot_observed_at":"2026-08-13T05:45:05.953144Z","submitted_at":"2026-08-03T07:03:24Z","title":"PICopilot: An LLM-based Agentic Framework for Assisting Photonic Integrated Circuit Design via Script Generation","version":1},"reference_index":22,"source":"pdf_text","source_observed_at":"2026-08-04T20:50:44.998646Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2608.01791"},"observation_digest":"sha256:2b1d66f86d956b228f1733725542195c3c0ddc3b904f94c5f0e7054ebe74d58d","observation_id":"62844f13-f3d4-4e08-9298-0fb537be6e66","resolution":{"observed_at":"2026-08-04T20:50:44.998646Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-07T00:13:00.316260Z","title":null,"venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2608.01791","last_updated":"2026-08-06T01:35:04Z","snapshot_observed_at":"2026-08-13T05:45:05.953144Z","submitted_at":"2026-08-03T07:03:24Z","title":"PICopilot: An LLM-based Agentic Framework for Assisting Photonic Integrated Circuit Design via Script Generation","version":2},"reference_index":22,"source":"pdf_text","source_observed_at":"2026-08-07T00:13:00.316260Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2608.01791"},"observation_digest":"sha256:f90281eb5b9bd0c1ef19a2ac2f0607fcc29fbc6004a1e79d894458a891d86f3e","observation_id":"f5945962-75ee-4175-963b-ddacc535ca87","resolution":{"observed_at":"2026-08-07T00:13:00.316260Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-07T00:59:47.940557Z","title":null,"venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2608.01791","last_updated":"2026-08-06T01:35:04Z","snapshot_observed_at":"2026-08-13T05:45:05.953144Z","submitted_at":"2026-08-03T07:03:24Z","title":"PICopilot: An LLM-based Agentic Framework for Assisting Photonic Integrated Circuit Design via Script Generation","version":3},"reference_index":22,"source":"pdf_text","source_observed_at":"2026-08-07T00:59:47.940557Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2608.01791"},"observation_digest":"sha256:f3b238bc4d66758803cd6e87d97ed29ab47512035f70c38f08ae92edaabcd3fb","observation_id":"505af35d-6ddc-4fc1-a462-74daabbe08d1","resolution":{"observed_at":"2026-08-07T00:59:47.940557Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-15T15:01:10.196660Z","title":"Chipnemo: Domain- adapted llms for chip design,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2608.02878","last_updated":"2026-08-03T21:00:58Z","snapshot_observed_at":"2026-08-18T20:57:32.520191Z","submitted_at":"2026-08-03T21:00:58Z","title":"VeriTrace: Human-Like Temporal Exploration Completes Agentic Action Space","version":1},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-08-15T15:01:10.196660Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2608.02878"},"observation_digest":"sha256:0530e74b60878f98e5d1e7bb8a0d2ad3e42ab812f61fc0cf1ce67338aee0938b","observation_id":"0a36b807-6318-448b-912c-fed9612c360f","resolution":{"observed_at":"2026-08-15T15:01:10.196660Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-05T13:48:51.410723Z","title":"Liu, M.; Ene, T.-D.; Kirby, R.; Cheng, C.; Pinckney, N.; Liang,R.;Alben,J.;Anand,H.;Banerjee,S.;Bayraktaroglu, I.;etal.2023","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2608.03738","last_updated":"2026-08-04T14:32:43Z","snapshot_observed_at":"2026-08-14T19:27:40.202749Z","submitted_at":"2026-08-04T14:32:43Z","title":"AgenticECO: An Agentic Framework for ECO on 3D Integrated Circuits","version":1},"reference_index":11,"source":"pdf_text","source_observed_at":"2026-08-05T13:48:51.410723Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2608.03738"},"observation_digest":"sha256:3e0b4edd629bc89708fa3f86418735aa9badfcd0876ebf4e698edc9722116b8e","observation_id":"d02870cf-8007-4015-9d80-0b8351ee3853","resolution":{"observed_at":"2026-08-05T13:48:51.410723Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-16T00:17:57.219775Z","title":null,"venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2608.12197","last_updated":"2026-08-12T15:51:52Z","snapshot_observed_at":"2026-08-18T20:20:02.722666Z","submitted_at":"2026-08-12T15:51:52Z","title":"NetlistBench: Evaluating LLM Reliability in SPICE Netlist Recognition and Manipulation","version":1},"reference_index":16,"source":"pdf_text","source_observed_at":"2026-08-16T00:17:57.219775Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2608.12197"},"observation_digest":"sha256:5148994525ada63a4d0989bd3f140fd1a036415aad8f3df8020c9ac926999525","observation_id":"f1d1db51-f5b5-471e-9c6f-b16c0cc75019","resolution":{"observed_at":"2026-08-16T00:17:57.219775Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-16T00:06:27.567975Z","title":"ChipNemo: Domain-adapted LLMs for chip design,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2608.12751","last_updated":"2026-08-14T02:39:08Z","snapshot_observed_at":"2026-08-19T23:09:30.442993Z","submitted_at":"2026-08-13T03:02:25Z","title":"SynAct: A Reasoning-Acting Large Language Model Agent for Adaptive Synthesis Optimization","version":1},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-08-16T00:06:27.567975Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2608.12751"},"observation_digest":"sha256:e560ccd41cace1ef1ef86fc2bd11d652aec30058b104dde9370b1eb5dfb1c68a","observation_id":"75c0c99c-f7ac-4918-80a7-24c84152557c","resolution":{"observed_at":"2026-08-16T00:06:27.567975Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-15T18:26:17.053085Z","title":"Chipnemo: Domain-adapted llms for chip design,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2608.13027","last_updated":"2026-08-13T09:54:38Z","snapshot_observed_at":"2026-08-19T23:32:41.964262Z","submitted_at":"2026-08-13T09:54:38Z","title":"Why Do Prefetchers Fail? Let Agents Answer","version":1},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-08-15T18:26:17.053085Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2608.13027"},"observation_digest":"sha256:b25c61aacf89aabbc2d74ca2b4f1c40f098ab47d20532c127b71d297343c8b9f","observation_id":"f972c912-d010-4a23-b269-5c6b023cdc61","resolution":{"observed_at":"2026-08-15T18:26:17.053085Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}}],"links":{"evidence":"/evidence","html":"/paper/2311.00176/citation-record","integrity":"/paper/2311.00176/integrity","json":"/paper/2311.00176/citation-record.json","paper":"/paper/2311.00176"},"outbound":[],"paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","latest_version":5,"primary_category":"cs.CL","snapshot_observed_at":"2026-08-19T22:56:40.589361Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design"},"reference_resolution":{"displayed":0,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":0,"verified_exact":0,"verified_fuzzy":0},"total_outbound_references":0},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"thesis":"As of 23 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 93 inbound Pith citation observations for arXiv:2311.00176."}