{"as_of":"2026-08-14T17:39:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:33bd6765aa53ca3f952317804869eab9d5931e24c3bd2a7b83386b8ce9738488","coverage":[{"denominator":0,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":1,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":1,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-14T06:32:32.682623+00:00","state":"measured"},{"denominator":1,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":1,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-12T17:35:34.221249Z","state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"pith","source_observed_at":"2026-08-12T17:35:34.902413Z","state":"measured"}],"external_citation_measurements":[],"inbound":[{"citation":{"cited_paper":{"arxiv_id":"2406.17796","last_updated":"2024-06-12T14:17:21Z","snapshot_observed_at":"2026-08-14T13:53:30.938267Z","submitted_at":"2024-06-12T14:17:21Z","title":"Hypervisor Extension for a RISC-V Processor","version":1},"cited_work":{"arxiv_id":"2406.17796","doi":null,"metadata_source":"pith","pith_arxiv_id":"2406.17796","snapshot_observed_at":"2026-08-12T17:35:34.902413Z","title":"Hypervisor Extension for a RISC-V Processor","venue":"cs.AR","work_id":"d3936a57-7535-4196-9291-9a8e7290990b","year":2024},"citing_paper":{"arxiv_id":"2411.12444","last_updated":"2024-11-20T09:39:33Z","snapshot_observed_at":"2026-08-12T17:28:34.111513Z","submitted_at":"2024-11-19T12:07:40Z","title":"Advancing Cloud Computing Capabilities on gem5 by Implementing the RISC-V Hypervisor Extension","version":2},"reference_index":18,"source":"pdf_text","source_observed_at":"2026-08-12T17:35:34.221249Z"},"links":{"cited_paper":"/paper/2406.17796","citing_paper":"/paper/2411.12444"},"observation_digest":"sha256:f9d574b9d490a64639e2fed7fe726789806041d0f3db4366c8acaa0fa3f18224","observation_id":"1324a08c-20b7-444d-bba2-a3fe6a78913a","resolution":{"observed_at":"2026-08-12T17:35:34.910796Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-14T06:32:32.682623+00:00","source":"crossref"},{"observed_at":"2026-08-14T06:32:18.44784+00:00","source":"retraction_watch"}],"state":"measured"}}],"links":{"evidence":"/evidence","html":"/paper/2406.17796/citation-record","integrity":"/paper/2406.17796/integrity","json":"/paper/2406.17796/citation-record.json","paper":"/paper/2406.17796"},"outbound":[],"paper":{"arxiv_id":"2406.17796","last_updated":"2024-06-12T14:17:21Z","latest_version":1,"primary_category":"cs.AR","snapshot_observed_at":"2026-08-14T13:53:30.938267Z","submitted_at":"2024-06-12T14:17:21Z","title":"Hypervisor Extension for a RISC-V Processor"},"reference_resolution":{"displayed":0,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":0,"verified_exact":0,"verified_fuzzy":0},"total_outbound_references":0},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-14T06:32:32.682623+00:00","source":"crossref"},{"observed_at":"2026-08-14T06:32:18.44784+00:00","source":"retraction_watch"}],"thesis":"As of 14 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 1 inbound Pith citation observation for arXiv:2406.17796."}