{"as_of":"2026-08-10T19:35:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:104bde6212d182d3ddfef55d839df37385c589699b3e40deb24f7173cdb79f42","coverage":[{"denominator":0,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":3,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":3,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-10T06:31:04.303077+00:00","state":"measured"},{"denominator":3,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":3,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-07T23:14:10.485794Z","state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"pith","source_observed_at":"2026-08-07T23:14:10.593552Z","state":"measured"}],"external_citation_measurements":[],"inbound":[{"citation":{"cited_paper":{"arxiv_id":"2407.18272","last_updated":"2024-07-22T20:32:16Z","snapshot_observed_at":"2026-08-02T21:40:46.566272Z","submitted_at":"2024-07-22T20:32:16Z","title":"AICircuit: A Multi-Level Dataset and Benchmark for AI-Driven Analog Integrated Circuit Design","version":1},"cited_work":{"arxiv_id":"2407.18272","doi":null,"metadata_source":"pith","pith_arxiv_id":"2407.18272","snapshot_observed_at":"2026-08-07T23:14:10.593552Z","title":"AICircuit: A Multi-Level Dataset and Benchmark for AI-Driven Analog Integrated Circuit Design","venue":"cs.AR","work_id":"15a0d3ad-b8fe-41bc-8d06-33d4cc0c0f89","year":2024},"citing_paper":{"arxiv_id":"2502.08949","last_updated":"2025-05-19T17:23:05Z","snapshot_observed_at":"2026-08-09T18:30:14.935745Z","submitted_at":"2025-02-13T04:15:20Z","title":"DICE: Device-level Integrated Circuits Encoder with Graph Contrastive Pretraining","version":2},"reference_index":71,"source":"pdf_text","source_observed_at":"2026-08-07T23:14:10.485794Z"},"links":{"cited_paper":"/paper/2407.18272","citing_paper":"/paper/2502.08949"},"observation_digest":"sha256:5558867fbc7020b5ebd7e05828a271173f5735bfa2bc475cc1767a6f5b7893c4","observation_id":"a4c2df60-ce6f-458e-8224-78bf0884c093","resolution":{"observed_at":"2026-08-07T23:14:10.601142Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-10T06:31:04.303077+00:00","source":"crossref"},{"observed_at":"2026-08-10T06:30:57.382061+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2407.18272","last_updated":"2024-07-22T20:32:16Z","snapshot_observed_at":"2026-08-02T21:40:46.566272Z","submitted_at":"2024-07-22T20:32:16Z","title":"AICircuit: A Multi-Level Dataset and Benchmark for AI-Driven Analog Integrated Circuit Design","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2407.18272","snapshot_observed_at":"2026-07-12T00:33:59.659330Z","title":"arXiv:2407.18272 https://arxiv.org/abs/2407.18272","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2607.03701","last_updated":"2026-07-04T04:37:57Z","snapshot_observed_at":"2026-08-05T00:39:12.704859Z","submitted_at":"2026-07-04T04:37:57Z","title":"SABLE: An NDA-Safe Closed-Loop LLM Framework for Analog Circuit Optimization in Industrial EDA Flows","version":1},"reference_index":13,"source":"pdf_text","source_observed_at":"2026-07-12T00:33:59.659330Z"},"links":{"cited_paper":"/paper/2407.18272","citing_paper":"/paper/2607.03701"},"observation_digest":"sha256:d403a71201f1825438f76a161a068f6b0442841e31940cfdc38079c38834e46e","observation_id":"859e8ef6-01e4-4fb9-bae5-d4e82717b440","resolution":{"observed_at":"2026-07-12T00:33:59.659330Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2407.18272","last_updated":"2024-07-22T20:32:16Z","snapshot_observed_at":"2026-08-02T21:40:46.566272Z","submitted_at":"2024-07-22T20:32:16Z","title":"AICircuit: A Multi-Level Dataset and Benchmark for AI-Driven Analog Integrated Circuit Design","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2407.18272","snapshot_observed_at":"2026-08-02T05:22:44.203481Z","title":null,"venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2607.13416","last_updated":"2026-07-15T03:35:14Z","snapshot_observed_at":"2026-08-02T11:04:17.487297Z","submitted_at":"2026-07-15T03:35:14Z","title":"EXPLORE: Exploration with Guided Search for Analog Topology Generation using Language Models","version":1},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-08-02T05:22:44.203481Z"},"links":{"cited_paper":"/paper/2407.18272","citing_paper":"/paper/2607.13416"},"observation_digest":"sha256:c185e30fdecd5861a506901d5ad5ad2852754720d2d4ff8721701eed5eb46b63","observation_id":"6d98ba00-5e2d-446f-9108-2385927e5376","resolution":{"observed_at":"2026-08-02T05:22:44.203481Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}}],"links":{"evidence":"/evidence","html":"/paper/2407.18272/citation-record","integrity":"/paper/2407.18272/integrity","json":"/paper/2407.18272/citation-record.json","paper":"/paper/2407.18272"},"outbound":[],"paper":{"arxiv_id":"2407.18272","last_updated":"2024-07-22T20:32:16Z","latest_version":1,"primary_category":"cs.AR","snapshot_observed_at":"2026-08-02T21:40:46.566272Z","submitted_at":"2024-07-22T20:32:16Z","title":"AICircuit: A Multi-Level Dataset and Benchmark for AI-Driven Analog Integrated Circuit Design"},"reference_resolution":{"displayed":0,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":0,"verified_exact":0,"verified_fuzzy":0},"total_outbound_references":0},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-10T06:31:04.303077+00:00","source":"crossref"},{"observed_at":"2026-08-10T06:30:57.382061+00:00","source":"retraction_watch"}],"thesis":"As of 10 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 3 inbound Pith citation observations for arXiv:2407.18272."}