{"as_of":"2026-08-15T11:29:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:71b897bf3e0af6eb0281c98b298f2fff3f7935da62411ef34540a3b38aab779a","coverage":[{"denominator":205,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":100,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-11T11:14:55.561082Z","state":"measured"},{"denominator":102,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":102,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-15T06:32:42.880941+00:00","state":"measured"},{"denominator":2,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":2,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-07T11:35:24.030784Z","state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"arxiv_reference","source_observed_at":"2026-05-09T22:29:06.765074Z","state":"measured"}],"external_citation_measurements":[],"inbound":[{"citation":{"cited_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2412.15666","snapshot_observed_at":"2026-08-07T11:35:24.030784Z","title":null,"venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2506.01869","last_updated":"2025-06-02T16:56:21Z","snapshot_observed_at":"2026-08-14T20:39:04.418158Z","submitted_at":"2025-06-02T16:56:21Z","title":"Frugal Machine Learning for Energy-efficient, and Resource-aware Artificial Intelligence","version":1},"reference_index":81,"source":"pdf_text","source_observed_at":"2026-08-07T11:35:24.030784Z"},"links":{"cited_paper":"/paper/2412.15666","citing_paper":"/paper/2506.01869"},"observation_digest":"sha256:e39a4e6ff23673f33badcd6e453d90534918f749574cc6bc63c40304a9b6b2fa","observation_id":"bc16ad82-9219-4cd8-ac53-e783e63cdf9b","resolution":{"observed_at":"2026-08-07T11:35:24.030784Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"cited_work":{"arxiv_id":"2412.15666","doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":"2412.15666","snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"A survey on fpga-based accelerator for ml models","venue":null,"work_id":"2d14dd28-9d63-4eb6-9d08-b0e0058ce9d8","year":2024},"citing_paper":{"arxiv_id":"2604.21290","last_updated":"2026-04-23T05:09:54Z","snapshot_observed_at":"2026-08-14T13:28:18.730975Z","submitted_at":"2026-04-23T05:09:54Z","title":"GraphLeap: Decoupling Graph Construction and Convolution for Vision GNN Acceleration on FPGA","version":1},"reference_index":49,"source":"pdf_text","source_observed_at":"2026-05-09T22:27:03.473914Z"},"links":{"cited_paper":"/paper/2412.15666","citing_paper":"/paper/2604.21290"},"observation_digest":"sha256:54180f6be768fa64b9e69309812214406e3cc74246f1b64ecc59efc15d2e04a5","observation_id":"886f0f19-3049-4286-aeb6-6015cd9f5ecd","resolution":{"observed_at":"2026-05-09T22:29:06.766683Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-15T06:32:42.880941+00:00","source":"crossref"},{"observed_at":"2026-08-15T06:32:39.529945+00:00","source":"retraction_watch"}],"state":"measured"}}],"links":{"evidence":"/evidence","html":"/paper/2412.15666/citation-record","integrity":"/paper/2412.15666/integrity","json":"/paper/2412.15666/citation-record.json","paper":"/paper/2412.15666"},"outbound":[{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.347845Z","title":"Lung ct image segmen- tation using deep neural networks,","venue":null,"work_id":null,"year":2018},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.347845Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:6deda37b96b944b9ade24ad6d67829102358ee512d2f8ccb9a89c3fa3f81d2ac","observation_id":"db3813c0-44ed-43a2-bc7b-7a9c0ebdf3d6","resolution":{"observed_at":"2026-08-11T11:14:55.347845Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.350639Z","title":"Imagenet classification with deep convolutional neural networks,","venue":null,"work_id":null,"year":2012},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":2,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.350639Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:0fa8ed38587b5c20f6c042f2c067809b113d44059f7ab0ca20db6ab09a5d7a92","observation_id":"71907c4f-4feb-46e6-98a1-ff54af93f1e6","resolution":{"observed_at":"2026-08-11T11:14:55.350639Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.353622Z","title":"Deep residual learning for image recognition,","venue":null,"work_id":null,"year":2016},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":3,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.353622Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:93a66aaa28932ed87baba5a7805256499dec18929c8838de017a5cec1de107b7","observation_id":"1d0d910f-611f-4ae1-82b7-2408fab2ed14","resolution":{"observed_at":"2026-08-11T11:14:55.353622Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2004.10934","last_updated":"2020-04-23T02:10:02Z","snapshot_observed_at":"2026-07-06T09:14:32.318388Z","submitted_at":"2020-04-23T02:10:02Z","title":"YOLOv4: Optimal Speed and Accuracy of Object Detection","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2004.10934","snapshot_observed_at":"2026-08-11T11:14:55.355686Z","title":"Yolov4: Op- timal speed and accuracy of object detection,","venue":null,"work_id":null,"year":2004},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":4,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.355686Z"},"links":{"cited_paper":"/paper/2004.10934","citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:7d637b464032c494e845465a3e9c6951fbce6a3473c5d5d688d78de6b8606cd9","observation_id":"af236a1e-e7ca-4916-95cd-61d6a886b59b","resolution":{"observed_at":"2026-08-11T11:14:55.355686Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.358245Z","title":"A state of art techniques on machine learning algorithms: a perspective of supervised learning approaches in data classification,","venue":null,"work_id":null,"year":2018},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":5,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.358245Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:9b3a5732a6818f31fb67f8b4fbad0de21bec3ae798e1f3d71174441930519879","observation_id":"99c346ef-4b5c-428a-9cec-de25ca4be406","resolution":{"observed_at":"2026-08-11T11:14:55.358245Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.360426Z","title":"Machine learning and natural language processing in psychotherapy research: Alliance as example use case","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":6,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.360426Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:d01f2d6e1952c30741b6d598f7cf5a039234826d05e8c9febb422160bf575157","observation_id":"f5d358b0-1310-43a3-ba44-f5e4910b0d03","resolution":{"observed_at":"2026-08-11T11:14:55.360426Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.363321Z","title":"Resource- aware on-device deep learning for supermarket hazard detection,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.363321Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:bcce891a0a834641442d6dab5dbf8b93a8e08b8d55f95ce32338b92bec49bbb4","observation_id":"a53d3011-f221-4559-ac48-d46edc0ae86c","resolution":{"observed_at":"2026-08-11T11:14:55.363321Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.365300Z","title":"Sciann: A keras/tensorflow wrapper for scientific computations and physics-informed deep learning using artificial neural networks,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":8,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.365300Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:6dd28f353a2d05449ab38b55db2c80ea527a7bc406861ddaea01195bc136ad74","observation_id":"3e819b12-8c12-4483-a602-9d6ddd76f453","resolution":{"observed_at":"2026-08-11T11:14:55.365300Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.367183Z","title":"Autockt: Deep reinforcement learning of analog circuit designs,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.367183Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:81ec7382697e17be67a97dfc7c4968bfca4d0646ec9879b53d7821f942d62954","observation_id":"4569d6eb-a0e3-4266-9a91-9adcf999f390","resolution":{"observed_at":"2026-08-11T11:14:55.367183Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.369727Z","title":"Learning both weights and connections for efficient neural network,","venue":null,"work_id":null,"year":2015},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.369727Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:3cabc9fb19e6268a1ed944b2ab08a3f47d8ad88de1a04d934d98bffdb2865292","observation_id":"ffd38fc4-2043-4d03-a880-fd3f96122caf","resolution":{"observed_at":"2026-08-11T11:14:55.369727Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.372266Z","title":"A real-time object detection accelerator with compressed ss- dlite on fpga,","venue":null,"work_id":null,"year":2018},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":11,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.372266Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:9e2595440dd1dd909a47a0a2376a5c20f8408f0169d8ea9da54ee554f375e218","observation_id":"e34fcc0b-a007-4770-bed6-0b7e945748d6","resolution":{"observed_at":"2026-08-11T11:14:55.372266Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.374889Z","title":"Accelerated real-time classification of evolving data streams using adaptive random forests,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":12,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.374889Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:37a8358e49d3825b1fcd932041b50fe723868ed0f553d2c88ed1a8b159031a22","observation_id":"a38db559-f160-474a-a6f4-55b1fe2226f3","resolution":{"observed_at":"2026-08-11T11:14:55.374889Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.377213Z","title":"Towards an efficient accelerator for dnn-based remote sensing image segmentation on fpgas,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":13,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.377213Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:a51d6bdf37782078c21b52161c8fa738c1b1bfa1902dece763cf4689658bbc03","observation_id":"2eb50692-51e2-4524-846e-f671c46dfe67","resolution":{"observed_at":"2026-08-11T11:14:55.377213Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.379209Z","title":"Req-yolo: A resource-aware, efficient quantization framework for object detection on fpgas,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.379209Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:8e3d4ee58d85a03cdef6da1a985a5d6648d8b3a92fdcb940ba8bc3197027d70c","observation_id":"70e4b331-3499-4428-8ef6-2ea5dfc7d909","resolution":{"observed_at":"2026-08-11T11:14:55.379209Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.381761Z","title":"A lightweight yolov2: A binarized cnn with a parallel support vector regression for an fpga,","venue":null,"work_id":null,"year":2018},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":15,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.381761Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:96a03eebf66f243deca294842e09a15327c735af6208c66c4baf41393e5e9acc","observation_id":"a3a0808a-7cd6-4b0e-a198-497eb7abfdc0","resolution":{"observed_at":"2026-08-11T11:14:55.381761Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.384594Z","title":"Zynet: automating deep neural network implementation on low-cost reconfigurable edge computing platforms,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":16,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.384594Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:32fac5cf2b05a3eb405bcebd445db3a30d99a8f2ea869ffee592c6c8c05c915d","observation_id":"10e7c540-c4a2-40c6-a7e1-514282b8f965","resolution":{"observed_at":"2026-08-11T11:14:55.384594Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.386735Z","title":"Squeezejet-3: an accelerator utilizing fpga mpsocs for edge cnn applications,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.386735Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:5c8e9d881c683b179356cbd9b6c1e6b3fb5be9e24702159622cee85ddbc317fd","observation_id":"dbec09cc-aa07-4c7d-aa31-2174bd02a8c9","resolution":{"observed_at":"2026-08-11T11:14:55.386735Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.388688Z","title":"Netpu: Prototyping a generic reconfigurable neural network accelerator architecture,","venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":18,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.388688Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:5f4f6565dc595201fd7fb6fcacddcfd32c4259db1f314ac89918a6327e3f4a89","observation_id":"296ddb9d-7122-4c5b-9c0e-41c6506e97f5","resolution":{"observed_at":"2026-08-11T11:14:55.388688Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.391732Z","title":"N3h-core: Neuron-designed neural network accelerator via fpga- based heterogeneous computing cores,","venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":19,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.391732Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:b5bb94d8046d50c0ea0825412cc86614cf2250b60cafe3d50124f0fe81a5f513","observation_id":"39ee4750-a100-48a4-baff-ec624d525e84","resolution":{"observed_at":"2026-08-11T11:14:55.391732Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.394676Z","title":"Mafia: Machine learning acceleration on fpgas for iot applications,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":20,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.394676Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:f886476c122d9a80e4d67ad6c3c613b3437dd3afa050f9f6c2695441a7ef8fd0","observation_id":"a7858039-4370-49d7-8c07-736f37ad489e","resolution":{"observed_at":"2026-08-11T11:14:55.394676Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.396807Z","title":"Design of high- throughput mixed-precision cnn accelerators on fpga,","venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":21,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.396807Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:f13edfc06cc280cf903c23f1ec67f74d6ebbc280422c5821682d0bf5e97b206b","observation_id":"869c9abc-e7ac-48bf-b31d-be4144f01569","resolution":{"observed_at":"2026-08-11T11:14:55.396807Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.398855Z","title":"Exploration of low numeric precision deep learning infer- ence using intel® fpgas,","venue":null,"work_id":null,"year":2018},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":22,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.398855Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:a7f7e82d99c569b94dd04aa1215c61dcd5280d4e173c4e94179b75e05acaf559","observation_id":"7a34f221-cc54-473a-af6b-5dc1c5284aef","resolution":{"observed_at":"2026-08-11T11:14:55.398855Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.401191Z","title":"A high-performance cnn processor based on fpga for mobilenets,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":23,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.401191Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:fd90007bfc5abe478241f96ddd1366866c0c1a0699cafe54e07d834dfe94a2a9","observation_id":"65a813c1-6515-43e9-983e-7495755a1a8d","resolution":{"observed_at":"2026-08-11T11:14:55.401191Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.403754Z","title":"A reconfigurable multithreaded accelerator for recurrent neural networks,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":24,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.403754Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:6d58109adb6fc9eff228d058d047bdffd92ab12cb8920d7956c37e4f9637ee5b","observation_id":"4fd76d8e-f506-4fba-9942-f8a4cddfb4ff","resolution":{"observed_at":"2026-08-11T11:14:55.403754Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.406027Z","title":"Accelerating bayesian inference on structured graphs using parallel gibbs sampling,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":25,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.406027Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:da1f7d8e1647fac0caf21e9d54a7280cfa14e71633fc6a297fe00ae667dbcdb6","observation_id":"63d89b12-20fe-4c35-8b61-8a52f1544976","resolution":{"observed_at":"2026-08-11T11:14:55.406027Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.408267Z","title":"An fpga-based low-latency acceler- ator for randomly wired neural networks,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":26,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.408267Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:f5a9cbbbf01eb41a51eb9333e9c0c32c869d07b017180de68ec1f3fae233a4f1","observation_id":"3ef4e796-62be-4559-8a9d-13b4c0a4d1ae","resolution":{"observed_at":"2026-08-11T11:14:55.408267Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.410698Z","title":"An fpga-based upper- limb rehabilitation device for gesture recognition and motion evaluation using multi-task recurrent neural networks,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":27,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.410698Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:ce164bf5ef46a2e91dd93f55c0796ec67b878b1917a6b0ec1717bac002090f0d","observation_id":"ab0767c2-a09d-462c-9339-594eecbbe268","resolution":{"observed_at":"2026-08-11T11:14:55.410698Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.412888Z","title":"Effi- cient stride 2 winograd convolution method using unified transforma- tion matrices on fpga,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":28,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.412888Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:9243681356a2b825323ac7a79e6cfbd91ac0597120eb755a4757ecef5b24b28f","observation_id":"f45104ff-f907-4a01-b6a0-a172ebcfc6ef","resolution":{"observed_at":"2026-08-11T11:14:55.412888Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.415148Z","title":"Esca: Event- based split-cnn architecture with data-level parallelism on ultrascale+ fpga,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":29,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.415148Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:c4d33475af6325578a1a409293def1e9c72f89ad62cf5e8ed70a8c419f619693","observation_id":"1841570c-fa3f-4be0-85ca-58c27fcd1905","resolution":{"observed_at":"2026-08-11T11:14:55.415148Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.417323Z","title":"Explor- ing resource-efficient acceleration algorithm for transposed convolu- tion of gans on fpga,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":30,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.417323Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:ccb218d0f8fdf435114623dc3b248e2acd366a709911c761b9b157504fa93661","observation_id":"545c8c6c-53a2-4a95-9a92-42c6985d9dfc","resolution":{"observed_at":"2026-08-11T11:14:55.417323Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.419354Z","title":"Leveraging fine-grained structured sparsity for cnn inference on systolic array architectures,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":31,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.419354Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:ef23b8a69c69bec03a30f3a4620edf897530157e7c4197e7fdf806126f14f548","observation_id":"c430fb71-a4c5-44e9-9f89-bbb706ecce4c","resolution":{"observed_at":"2026-08-11T11:14:55.419354Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.421985Z","title":"Optimizing reconfigurable recurrent neural networks,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":32,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.421985Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:3493aa40d1bd060831f38d39bb59c7e72eeeb614b296ad7e155d40f042cafea7","observation_id":"a123290d-a806-4eff-8e09-696e65a19f5b","resolution":{"observed_at":"2026-08-11T11:14:55.421985Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.424580Z","title":"Rna: Reconfigurable lstm accel- erator with near data approximate processing,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":33,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.424580Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:c2be585f8ff9f4f4db2ef545f5102310e682bd25b038c2f6e33b5f881804c080","observation_id":"7e99eef3-468b-401f-8079-0af4c7939e9f","resolution":{"observed_at":"2026-08-11T11:14:55.424580Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.426327Z","title":"When massive GPU parallelism ain’t enough: A novel hardware architectureof 2d-lstm neural network,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":34,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.426327Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:67d07545ffa55f08d197585313a1a17d6f41dae5c8f44679abffee3fba9d3b36","observation_id":"52e4197e-57fb-4a17-82e9-da1823b2e530","resolution":{"observed_at":"2026-08-11T11:14:55.426327Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.428258Z","title":"Bramac: Compute-in-bram architec- tures for multiply-accumulate on fpgas,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":35,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.428258Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:a783b6a8cff5fdab9b150ab274f4797f6fe49c3787ccd0edb3a8004c2aaadccf","observation_id":"a82c4cec-cfdd-4f95-86bb-b11a2978e5c0","resolution":{"observed_at":"2026-08-11T11:14:55.428258Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.430025Z","title":"A system-level transprecision fpga accelerator for blstm using on-chip memory reshaping,","venue":null,"work_id":null,"year":2018},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":36,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.430025Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:8d677cb3a8a1a143936cf1f92007f44483238c15818b5c5dd4040225b342722c","observation_id":"243be754-be27-41fe-95da-2a7cb9769bdc","resolution":{"observed_at":"2026-08-11T11:14:55.430025Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.432059Z","title":"Evaluating low-memory gemms for convolutional neural network inference on fpgas,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":37,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.432059Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:31f2c37dd921e5968f59ad19bf6c845d90c1d61abc39503012c403289408874b","observation_id":"c9ca3f93-d299-4b17-a377-25bdbfb5f86d","resolution":{"observed_at":"2026-08-11T11:14:55.432059Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.434843Z","title":"All adder neural networks for on-board remote sensing scene classification,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":38,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.434843Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:be64f21968c1c1cb8045db057ac5437b35d029c4a98c1292f2c4f41e12376883","observation_id":"1d72c18f-d6d8-4baf-bb4b-fe73d9a9bd27","resolution":{"observed_at":"2026-08-11T11:14:55.434843Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.437089Z","title":"An opencl-based fpga accelerator for compressed yolov2,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":39,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.437089Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:dbad59fe52cf5199b10f754c7c8839afc68c6296d66833d3525095578779a3ea","observation_id":"cee14a68-960d-49d6-aa7a-e16c73abc673","resolution":{"observed_at":"2026-08-11T11:14:55.437089Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.438856Z","title":"Boostgcn: A framework for optimizing gcn inference on fpga,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":40,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.438856Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:e152e28cde07edbd610695a5f2fc2ca933bec6cdbd552c111c2ac0fe57e5e130","observation_id":"bee48d03-b089-49f2-b4a1-429035fcf155","resolution":{"observed_at":"2026-08-11T11:14:55.438856Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.440509Z","title":"C- lstm: Enabling efficient lstm using structured compression techniques on fpgas,","venue":null,"work_id":null,"year":2018},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":41,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.440509Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:08d1af3c4dcca8993d2d7f1ecad22aed3b817264aa85a893d85ba6cc614b86d6","observation_id":"2300a57c-c1f7-4306-bd0f-6822c588c9dd","resolution":{"observed_at":"2026-08-11T11:14:55.440509Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.442368Z","title":"Efficient and effective sparse lstm on fpga with bank-balanced sparsity,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":42,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.442368Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:523e045736bf34f0f2d86b71424d4c3fb92e004bcd9960449a7d869c996e5039","observation_id":"7055e401-b1d3-4ee8-b24d-c8b6fd8daf03","resolution":{"observed_at":"2026-08-11T11:14:55.442368Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.444345Z","title":"Fixyfpga: Efficient fpga accelerator for deep neural networks with high element-wise sparsity and without external memory access,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":43,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.444345Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:d2caa987aeaee2c598b83b0e709f7821daf182a6b86a0eebaa322b13fa603dab","observation_id":"e6855b04-93bb-4c93-93e7-c6c03dbbdf08","resolution":{"observed_at":"2026-08-11T11:14:55.444345Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.446443Z","title":"Grasu: A fast graph update library for fpga-based dynamic graph processing,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":44,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.446443Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:6350f1061d8cb8ccfd13633c46e0de73e633a098ba4de9131e20ad1e44f40992","observation_id":"adfdc58a-919d-4119-a356-19d770033d51","resolution":{"observed_at":"2026-08-11T11:14:55.446443Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.448264Z","title":"Memory-efficient architecture for accelerating genera- tive networks on fpga,","venue":null,"work_id":null,"year":2018},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":45,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.448264Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:f2aa01884917316fb59250654b27ab818b1fec36eed1fb57946d40007aa13bd8","observation_id":"2dac8e17-1c52-4e4c-ac1f-f94d11293d41","resolution":{"observed_at":"2026-08-11T11:14:55.448264Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.450042Z","title":"Sdma: An efficient and flexible sparse-dense matrix-multiplication architecture for gnns,","venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":46,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.450042Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:29de8cd7d8a16a4babeef5b6142b4c64c6b6b0fd814ef46c1c8ae698bc55e82f","observation_id":"f9a4e5c7-7364-41c7-848e-07e9369b5c6e","resolution":{"observed_at":"2026-08-11T11:14:55.450042Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.451863Z","title":"Simbnn: A similarity-aware binarized neural network acceleration framework,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":47,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.451863Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:56cf4c715552424dcd62db1625d664b7dde78feb83dd8ab1b5683c8b56cac700","observation_id":"680bd521-d29c-4fcc-b9a8-dc2a5456bc48","resolution":{"observed_at":"2026-08-11T11:14:55.451863Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.454441Z","title":"Syncnn: Evaluating and accel- erating spiking neural networks on fpgas,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":48,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.454441Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:9f4bb97c8c8fe8ee859ab2925714a5772bca030c5cbd756090cc9dd2f1b30b9f","observation_id":"b4cffd1a-dde7-438b-a1df-8a4c911d2797","resolution":{"observed_at":"2026-08-11T11:14:55.454441Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.456460Z","title":"Tfr-gcn: A gcn accelerator with tile- fusing strategy,","venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":49,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.456460Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:a4f368cb19a047f2e271be7170230952b0fdb4e80afa8cb5979251de8b4eb0ad","observation_id":"25314a78-4d0e-4a8b-b423-d345d58d651b","resolution":{"observed_at":"2026-08-11T11:14:55.456460Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.458430Z","title":"M4bram: Mixed-precision matrix-matrix multiplication in fpga block rams,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":50,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.458430Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:ccbedd2257212ca9dceccf5af2accb5378b0a901dee9b02629b1862887064dc0","observation_id":"eb140855-1361-44eb-bb73-9c0fcc9b29e4","resolution":{"observed_at":"2026-08-11T11:14:55.458430Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.460433Z","title":"Mp-opu: A mixed precision fpga-based overlay processor for convolutional neural networks,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":51,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.460433Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:afb5f2f318bbd35eec8d9adea4e3a0ca46c5fbc2414afb00922ddab9e90de112","observation_id":"258ef026-2d10-46f9-a707-9455ee9c14fc","resolution":{"observed_at":"2026-08-11T11:14:55.460433Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.463493Z","title":"A data-center fpga acceleration platform for convolutional neural networks,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":52,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.463493Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:79c16319b71059c837315161564d3aef33d506e82fecec3900411f8b32983809","observation_id":"6ef9e07f-6efd-4c48-b2fa-d762f6b58dc3","resolution":{"observed_at":"2026-08-11T11:14:55.463493Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.465495Z","title":"A low-cost reconfigurable nonlinear core for embedded dnn applications,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":53,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.465495Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:eb8514826103ac8512bf928c1ca165292c4bc25c90e3c17648a063bc7613d77e","observation_id":"4cc7dd83-9605-44c7-82db-e3bfb41b5aef","resolution":{"observed_at":"2026-08-11T11:14:55.465495Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.467454Z","title":"An fpga-based mobilenet accelerator considering network structure characteristics,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":54,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.467454Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:996c38cc7fe9754efc2fcb124f9f402f51fde1d530b9e9f3bef193fad8136a69","observation_id":"580ea8f5-0d94-4175-8afd-3422bda70735","resolution":{"observed_at":"2026-08-11T11:14:55.467454Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.469696Z","title":"Film-qnn: Efficient fpga acceleration of deep neural networks with intra-layer, mixed-precision quantization,","venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":55,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.469696Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:0839d9a198ce26a04b2ca3e45c5182edaf5ae7983ea568ed2b5cd2505e95d4b3","observation_id":"7968d430-b7da-45d4-a6fb-5846756f19b3","resolution":{"observed_at":"2026-08-11T11:14:55.469696Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.472386Z","title":"Msd: Mixing signed digit representations for hardware-efficient dnn acceleration on fpga with heterogeneous resources,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":56,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.472386Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:5d681069f323d2d3636e4c8a667213de9466eddf3c66c78169a0f148b1a5483d","observation_id":"db1bd6bd-bc94-4c7b-bfab-4f54a6db5d03","resolution":{"observed_at":"2026-08-11T11:14:55.472386Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.474578Z","title":"Hybrid dot-product calculation for convolutional neural networks in fpga,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":57,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.474578Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:2c2c0382a2c69313cf4448e269f4e60482ae6cd8b09844932f42f9f9d288b4c1","observation_id":"80da683d-764c-4e32-9617-7123bbfe2f1b","resolution":{"observed_at":"2026-08-11T11:14:55.474578Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.476423Z","title":"Increasing flexibility of fpga-based cnn accelerators with dynamic partial reconfiguration,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":58,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.476423Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:fae7fde4226cb5ac657383452dec8cfd7a31d6bbe206d27ad77ee2185ec8a0f7","observation_id":"fd333d14-7026-4a23-9f85-32687a84bfa1","resolution":{"observed_at":"2026-08-11T11:14:55.476423Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.478582Z","title":"Light-opu: An fpga-based overlay processor for lightweight convolutional neural networks,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":59,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.478582Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:b80005215dd1a921f5850b33b4dda8ef0c404b67c9e035fee6a50d91e876f2d1","observation_id":"8ee96026-88e5-4029-8fab-d8a0241ebdc5","resolution":{"observed_at":"2026-08-11T11:14:55.478582Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.480580Z","title":"Reconfigurable con- volutional kernels for neural networks on fpgas,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":60,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.480580Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:1265cb25c5ffe03c397ea017cd1b2e7b3172c4ee41c816667f3af81446bb5f4a","observation_id":"1ad05904-975c-46e0-b106-fba571a66586","resolution":{"observed_at":"2026-08-11T11:14:55.480580Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.482435Z","title":"Towards the efficient multi-platform execution of deep neural networks,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":61,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.482435Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:dcabce6507a9fc23d85a279b235c6863f11b7cec73b097075dc01c5a685f3dc9","observation_id":"28b97999-b55d-40fc-9a3e-a21ea42da9b2","resolution":{"observed_at":"2026-08-11T11:14:55.482435Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.484434Z","title":"unzipfpga: Enhancing fpga-based cnn engines with on-the-fly weights genera- tion,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":62,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.484434Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:7e16114ea603c47e92907b9327e41107d833ea3649d9449ab04f2e1c8f2a27ed","observation_id":"c7d8d2b2-22b1-48c5-af9b-95d6a38f3e7a","resolution":{"observed_at":"2026-08-11T11:14:55.484434Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.486496Z","title":"Fpnet: Customized convolutional neural network for fpga platforms,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":63,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.486496Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:55d13eb1803d2980c4c0b5f4154b40423ab1a14885b9404b0a9721f47ec59904","observation_id":"e31a2678-1fbc-4a16-a309-3211d8302cf4","resolution":{"observed_at":"2026-08-11T11:14:55.486496Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.488416Z","title":"Hardware-friendly acceleration for deep neural networks with micro- structured compression,","venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":64,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.488416Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:89f7728853d131aaa32ce792dbe3bf135c4494048571c861eb176fc23dd37e26","observation_id":"637eebf0-2710-41c9-bcfd-4cd6f3105efe","resolution":{"observed_at":"2026-08-11T11:14:55.488416Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.490336Z","title":"From tensorflow graphs to luts and wires: Automated sparse and physically aware cnn hardware generation,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":65,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.490336Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:f6a2fee132c9a3267c8c1c56e41f8d26628b3c3336ef51f6e1e86dc44bbd0bce","observation_id":"47f11eea-54a9-4359-b98e-651088566b99","resolution":{"observed_at":"2026-08-11T11:14:55.490336Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.492174Z","title":"Memory-efficient dataflow inference for deep cnns on fpga,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":66,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.492174Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:af546b8b5b300fc5557796f161bc31ad6670f62510529447d3d914221130f1d0","observation_id":"c4a486f9-dd3a-4f06-a2bc-9b039c1cd96d","resolution":{"observed_at":"2026-08-11T11:14:55.492174Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.494666Z","title":"Atheena: A toolflow for hardware early-exit network automation,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":67,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.494666Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:b80f6fa4f2a6496a398d21fa22e42f5d786e3b183cfa6cfd49f02fe500622d53","observation_id":"ee0a7453-3fc1-4271-8522-e288ad033bcf","resolution":{"observed_at":"2026-08-11T11:14:55.494666Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.496558Z","title":"Cnn- based feature-point extraction for real-time visual slam on embedded fpga,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":68,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.496558Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:daf0c7b8134e1a8e0e9b29790f198367effb762871edb8b74ea18a4c98e89dab","observation_id":"f06c4b38-8e84-498c-9eca-c4e2fae7f3aa","resolution":{"observed_at":"2026-08-11T11:14:55.496558Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.498318Z","title":"Dynamap: Dynamic algorithm mapping framework for low latency cnn infer- ence,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":69,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.498318Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:3b8d122aa0e69abe09fb6ba3232643b63eb5349a92189168b6894114a15df62e","observation_id":"debca538-fac5-4865-8d23-bbd10304e79c","resolution":{"observed_at":"2026-08-11T11:14:55.498318Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.500074Z","title":"Extending data flow architectures for convolutional neural networks to multiple fpgas,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":70,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.500074Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:35aaac63d1a7e1c43567c1d76228efe15068972d2009e5fdfc1bb3615e104fce","observation_id":"7c75bd7c-9acd-4ca4-9c67-1bb76f82fec6","resolution":{"observed_at":"2026-08-11T11:14:55.500074Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.501867Z","title":"Accelerating continual learning on edge fpga,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":71,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.501867Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:64d703267cee5c28570d8d9e0cae1fab250b0bdda969e67d579542d0c3a476d2","observation_id":"a244140f-8437-478d-af22-6142727dbad8","resolution":{"observed_at":"2026-08-11T11:14:55.501867Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.503539Z","title":"Eciton: Very low- power lstm neural network accelerator for predictive maintenance at the edge,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":72,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.503539Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:4f518c49ba6a1db59dc8f71396e243a6fac3d6cd7676e01dc78b9e8b9e41962f","observation_id":"a9804017-c7d6-4b7d-9d50-637226542498","resolution":{"observed_at":"2026-08-11T11:14:55.503539Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.505226Z","title":"Deltarnn: A power-efficient recurrent neural network accelerator,","venue":null,"work_id":null,"year":2018},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":73,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.505226Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:fc928715d91924ac7e41d441c0a7137495ff36d604b56eed72d1b7e78985d84d","observation_id":"271e2779-bcda-4ccb-957a-971ae2f2265b","resolution":{"observed_at":"2026-08-11T11:14:55.505226Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.507148Z","title":"A high energy- efficiency fpga-based lstm accelerator architecture design by structured pruning and normalized linear quantization,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":74,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.507148Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:91829997e397ecb659014739f26b0fb15957c320951940fc6c95ddd74f7700bc","observation_id":"91cd2b1e-d1a1-4e31-b271-6064d68e3658","resolution":{"observed_at":"2026-08-11T11:14:55.507148Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.509215Z","title":"A flexible design automation tool for accelerating quantized spectral cnns,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":75,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.509215Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:c2a293289625c66abe9e627c7facdc821531564571591ef059c391312f0933ad","observation_id":"b0f47729-16b2-44ad-ba7f-ce575e6ee378","resolution":{"observed_at":"2026-08-11T11:14:55.509215Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.511336Z","title":"Apir-dsp: An approximate pir-dsp architecture for error- tolerant applications,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":76,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.511336Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:3e7665a9ea87444578205979aca2321140c1c0392c0dae20e7341d0ec6145ed6","observation_id":"ec6a5803-4156-4d12-ac22-25e55370cfba","resolution":{"observed_at":"2026-08-11T11:14:55.511336Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.513189Z","title":"Customizing low-precision deep neural networks for fpgas,","venue":null,"work_id":null,"year":2018},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":77,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.513189Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:9ff44bc2308ef262493c988a5ea04675f4222ec2ea44d62d17b0b39e42f18506","observation_id":"c4a0dab5-e0ec-4f58-bc72-bda1fa130667","resolution":{"observed_at":"2026-08-11T11:14:55.513189Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.515138Z","title":"Dsp-packing: Squeezing low-precision arithmetic into fpga dsp blocks,","venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":78,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.515138Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:aff6e79cec97f191bf6ed3d88978b4f0980c3f2ba45539cfa804356e0aafec04","observation_id":"afa8a68a-ec2a-48d4-aa8a-9f95f61856d9","resolution":{"observed_at":"2026-08-11T11:14:55.515138Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.517366Z","title":"Embracing diversity: Enhanced dsp blocks for low-precision deep learning on fpgas,","venue":null,"work_id":null,"year":2018},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":79,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.517366Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:e3b0b8a7c36a880ef3e316248b40d0c88cb4ae240fa4a17b7e34d02d74b5945b","observation_id":"236a77e9-33fd-4c03-8155-f413472b59e6","resolution":{"observed_at":"2026-08-11T11:14:55.517366Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.519523Z","title":"Ssimd: Supporting six signed multiplications in a dsp block for low-precision cnn on fpgas,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":80,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.519523Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:8920443474e67e0600f48d4c85639d7bd97a6b47612952d50bb45fbdb18deaf8","observation_id":"d98daad1-a668-4999-aff3-64e5288bd58d","resolution":{"observed_at":"2026-08-11T11:14:55.519523Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.522276Z","title":"Msbf-lstm: Most- significant bit-first lstm accelerators with energy efficiency optimisa- tions,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":81,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.522276Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:e1db4a22bcbd39ac406e926c9719ad19c9788402bb9346d92ac5ba1fb9ca9140","observation_id":"a14b5d4f-0de5-48e5-969e-2e30160e2e61","resolution":{"observed_at":"2026-08-11T11:14:55.522276Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.524975Z","title":"Beyond peak performance: Comparing the real performance of ai-optimized fpgas and gpus,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":82,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.524975Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:1a58fa6a4461c0791ce8fe15f6b041216e4993b782dba1e0fc03d208cd1dd6df","observation_id":"b7e3f94c-8658-4f7e-b1fa-9addc63c68f7","resolution":{"observed_at":"2026-08-11T11:14:55.524975Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.527108Z","title":"When massive gpu parallelism ain’t enough: A novel hardware architecture of 2d-lstm neural network,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":83,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.527108Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:005ec53532fa4ddfd29172d56872992f6a08cb4827660b4c3cf943cbe13deb1e","observation_id":"9d08b959-c98a-42af-b870-cf96154bf07c","resolution":{"observed_at":"2026-08-11T11:14:55.527108Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.529156Z","title":"Exploiting the potential of approximate arithmetic in dsp & ai hardware accelerators,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":84,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.529156Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:b88acfc2b1ca6c80612114e2903f153c82024733b1813880b6f77ebc116ee45f","observation_id":"063da0ec-0b0d-48cc-bd68-5e32e28a733f","resolution":{"observed_at":"2026-08-11T11:14:55.529156Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.531637Z","title":"In-package domain-specific asics for intel® stratix® 10 fpgas: A case study of accelerating deep learning using tensortile asic (abstract only),","venue":null,"work_id":null,"year":2018},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":85,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.531637Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:0842791f885aaed8165b2f64325837130b3c83ebdf739e6db4f71edca31fc3cc","observation_id":"d2c9b974-a182-481b-9b4b-ecf1923b08cd","resolution":{"observed_at":"2026-08-11T11:14:55.531637Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.533541Z","title":"Scaling the cascades: Interconnect-aware fpga implementation of machine learning prob- lems,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":86,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.533541Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:87b5653c32fe68bb7d6aa2b6b6106682174c689443e79caa05cc72df4a2003c9","observation_id":"ecb7a3e8-b52d-432b-8004-f02f6bb7911a","resolution":{"observed_at":"2026-08-11T11:14:55.533541Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.535547Z","title":"Why compete when you can work together: Fpga-asic integration for persistent rnns,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":87,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.535547Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:028c7949ce6b5175e41f8c384d1b4a9d8b006c9966c87db8ba4b748b835a7f0e","observation_id":"778da9dc-c5ef-492c-9a5a-6e9815f45d3e","resolution":{"observed_at":"2026-08-11T11:14:55.535547Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.537675Z","title":"Causalearn: Automated framework for scalable streaming-based causal bayesian learning using fpgas,","venue":null,"work_id":null,"year":2018},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":88,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.537675Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:68d52263397f03ff675e077dfeaebd9481d308d92827e050fcaa9b8661bbce4b","observation_id":"dd77cd88-e8c5-4b7c-9965-ce78e818962b","resolution":{"observed_at":"2026-08-11T11:14:55.537675Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.539629Z","title":"Lightweight programmable dsp block overlay for streaming neural network acceleration,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":89,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.539629Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:ac7211635b975aad5ad996c570f9d6541ad0cc0f1996ea9713448c629349f5d1","observation_id":"03efe3ac-46c1-437d-bbd8-93f2bae1fb0e","resolution":{"observed_at":"2026-08-11T11:14:55.539629Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.541857Z","title":"Pass: Exploiting post-activation sparsity in streaming architectures for cnn acceleration,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":90,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.541857Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:a5d2b53bc761fa3c42bdca4ee792bcd07a90cc38f245a45669a6a757bf239fe8","observation_id":"8472ce53-361a-4087-95f7-b018f00008cd","resolution":{"observed_at":"2026-08-11T11:14:55.541857Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.543817Z","title":"Reducing dynamic power in streaming cnn hardware accelerators by exploiting computational redundancies,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":91,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.543817Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:8425fd5afdad7c2862e111ac006c9056b6800efa48529cb836f8e0981bfd47f1","observation_id":"960d5751-0132-41ec-b6c9-78fc9cd304af","resolution":{"observed_at":"2026-08-11T11:14:55.543817Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.545791Z","title":"S2n2: A fpga accelerator for streaming spiking neural networks,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":92,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.545791Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:ce86f9a9b09b85e8768b8799a5dab93fc7a57256127a9427c464aacb5d8b1e73","observation_id":"6bdb0141-cab7-4d82-9a7d-1c842cb47549","resolution":{"observed_at":"2026-08-11T11:14:55.545791Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.547693Z","title":"Samo: Opti- mised mapping of convolutional neural networks to streaming architec- tures,","venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":93,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.547693Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:d875100cb83ddfa871362ae2a33373b1da129fdd5615b2b9120322cec1b8d7aa","observation_id":"7de7f374-a73c-4c99-a416-c1e5207c7634","resolution":{"observed_at":"2026-08-11T11:14:55.547693Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.549610Z","title":"Satay: a streaming architecture toolflow for accelerating yolo models on fpga devices,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":94,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.549610Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:80dd8129a32462a9a425a7c33b088202548b32fc8ae90d8ce418fd2b85ade867","observation_id":"6a05b9f8-f095-4add-b92a-59690f99478e","resolution":{"observed_at":"2026-08-11T11:14:55.549610Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.551463Z","title":"Tiny on-chip memory realization of weight sparseness split-cnns on low-end fpgas,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":95,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.551463Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:1b536442d45999974a61e3017d60bd6170d516211d8fbf0c1fd7c0c2786279c4","observation_id":"a9e23e81-2b6b-4bf5-8736-58eaa09e0b2b","resolution":{"observed_at":"2026-08-11T11:14:55.551463Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.553821Z","title":"Compute-capable block rams for efficient deep learning acceleration on fpgas,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":96,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.553821Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:da3988a0a7a2c8d0fd17a7fd9ac7244b4d07fffeb93709b4498cc0b8db6de2a2","observation_id":"721959fd-b47a-49f3-b9a7-b15047438582","resolution":{"observed_at":"2026-08-11T11:14:55.553821Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.555618Z","title":"A framework for graph machine learning on heterogeneous architecture,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":97,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.555618Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:67724a65878ca0a8ae10fb411e1433eca723853a48b690b27e0a813dd1178591","observation_id":"953a203c-1845-4896-8166-7a859dcde0f2","resolution":{"observed_at":"2026-08-11T11:14:55.555618Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.557639Z","title":"Automatic compiler based fpga accelerator for cnn training,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":98,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.557639Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:bec181eadbe9d619c6467088d288a505c9200e5d1e5fb2b1548fcb9306e3b9c3","observation_id":"fc18b453-4035-4575-8a22-cd79e9cca234","resolution":{"observed_at":"2026-08-11T11:14:55.557639Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.559432Z","title":"Hp-gnn: Generating high throughput gnn training implementation on cpu-fpga heterogeneous platform,","venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":99,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.559432Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:6c26bffe2429a8e0f1dac1cf88bd17591f1af2e79ff4bfa331f845a85bfb86b7","observation_id":"661b13bf-47ee-4758-b227-bdc445f24ff8","resolution":{"observed_at":"2026-08-11T11:14:55.559432Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-11T11:14:55.561082Z","title":"Logicnets: Co- designed neural networks and circuits for extreme-throughput applica- tions,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models","version":1},"reference_index":100,"source":"pdf_text","source_observed_at":"2026-08-11T11:14:55.561082Z"},"links":{"citing_paper":"/paper/2412.15666"},"observation_digest":"sha256:e54b3d6673e74f0a7c7756ba860765516155e3017e23e05628527b309df181f2","observation_id":"05778e3b-3de4-4465-a1dc-3eb5af74280a","resolution":{"observed_at":"2026-08-11T11:14:55.561082Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}}],"paper":{"arxiv_id":"2412.15666","last_updated":"2024-12-20T08:30:40Z","latest_version":1,"primary_category":"cs.AR","snapshot_observed_at":"2026-08-11T11:10:18.285823Z","submitted_at":"2024-12-20T08:30:40Z","title":"A survey on FPGA-based accelerator for ML models"},"reference_resolution":{"displayed":100,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":100,"verified_exact":0,"verified_fuzzy":0},"total_outbound_references":205},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-15T06:32:42.880941+00:00","source":"crossref"},{"observed_at":"2026-08-15T06:32:39.529945+00:00","source":"retraction_watch"}],"thesis":"As of 15 August 2026, this Paper Citation Record lists 100 of 205 outbound references and 2 inbound Pith citation observations for arXiv:2412.15666."}