{"as_of":"2026-08-10T12:08:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:6815983b3306c1597e3ee7591a7a604fabff1bf82e438879c6d68649fb16e7c8","coverage":[{"denominator":39,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":39,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-07T05:27:36.184407Z","state":"measured"},{"denominator":40,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":40,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-10T06:31:04.303077+00:00","state":"measured"},{"denominator":1,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":1,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-04T10:19:31.688560Z","state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"cited_works","source_observed_at":null,"state":"measured"}],"external_citation_measurements":[],"inbound":[{"citation":{"cited_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2506.07945","snapshot_observed_at":"2026-08-04T10:19:31.688560Z","title":"ProtocolLLM: RTL benchmark for systemverilog generation of communication protocols,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2510.10895","last_updated":"2026-06-30T06:03:20Z","snapshot_observed_at":"2026-08-08T22:52:00.691955Z","submitted_at":"2025-10-13T01:47:24Z","title":"LLM-Empowered Agentic MAC Protocols: A Dynamic Stackelberg Game Approach","version":2},"reference_index":18,"source":"pdf_text","source_observed_at":"2026-08-04T10:19:31.688560Z"},"links":{"cited_paper":"/paper/2506.07945","citing_paper":"/paper/2510.10895"},"observation_digest":"sha256:db1f209d73b75d406f213d320678f0e977585e4715858262acb1ace3910deaf2","observation_id":"1c7d73f9-2bc9-4f73-8e73-1350c7470e07","resolution":{"observed_at":"2026-08-04T10:19:31.688560Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}}],"links":{"evidence":"/evidence","html":"/paper/2506.07945/citation-record","integrity":"/paper/2506.07945/integrity","json":"/paper/2506.07945/citation-record.json","paper":"/paper/2506.07945"},"outbound":[{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:27:37.024402Z","title":"Claude opus","venue":null,"work_id":"68178411-64dd-4831-9f50-b253c3d7edfa","year":null},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:35.990595Z"},"links":{"citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:6fc898e01452491b3d3267d1468075fdb2db07a84a7645c8205a7f56d04a23d2","observation_id":"7e4aca70-e1da-4573-b35a-4c31622712d1","resolution":{"observed_at":"2026-08-07T05:27:37.029310Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-10T06:31:04.303077+00:00","source":"crossref"},{"observed_at":"2026-08-10T06:30:57.382061+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:27:37.008933Z","title":"Claude sonnet","venue":null,"work_id":"c2704aaf-40e7-4e56-bc81-cb7b1f313744","year":null},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":2,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:35.996217Z"},"links":{"citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:d9588dc04e5431310901c7ed353f8d92ce393f04f8b43c7fc735f0f4e7e1e54c","observation_id":"4bee1b3a-5dce-4ffd-ae65-163d76dac0a4","resolution":{"observed_at":"2026-08-07T05:27:37.014043Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-10T06:31:04.303077+00:00","source":"crossref"},{"observed_at":"2026-08-10T06:30:57.382061+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:27:36.993353Z","title":null,"venue":null,"work_id":"5e695bc7-4a58-42ed-9a5a-169d51078085","year":2020},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":3,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:36.001049Z"},"links":{"citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:006a44a9a26d36a3f00397fd47032cc73e4601634e622761bc7402884e7689e8","observation_id":"5f542a62-f6d1-43b7-81f7-30077eebce20","resolution":{"observed_at":"2026-08-07T05:27:36.998236Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-10T06:31:04.303077+00:00","source":"crossref"},{"observed_at":"2026-08-10T06:30:57.382061+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:27:36.978055Z","title":"Pyhdl- eval: An llm evaluation framework for hardware design using python- embedded dsls,","venue":null,"work_id":"16d8d4d3-0ed2-4af2-9c34-aaeca69f0739","year":2024},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":4,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:36.005841Z"},"links":{"citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:b0cd3445f4a95e489d0845cf925da8ff89f60d082ae17ffa2d1e22a97f300539","observation_id":"bb815a44-a833-4675-96c0-887dcbc83e43","resolution":{"observed_at":"2026-08-07T05:27:36.982900Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-10T06:31:04.303077+00:00","source":"crossref"},{"observed_at":"2026-08-10T06:30:57.382061+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:27:36.960195Z","title":"Smart communication in a wired sensor- and actuator-network of a modular robot actuator system using a hop- protocol with delta-routing,","venue":null,"work_id":"b6f2b8da-743b-4c3d-a423-cabb073713ab","year":2010},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":5,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:36.011019Z"},"links":{"citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:b8a045851ff21f192536c9af3bfb2aaa666a958ce66a6c01f37d896879ebb87e","observation_id":"1611d0de-f386-44e7-bd0d-06d3e76cd285","resolution":{"observed_at":"2026-08-07T05:27:36.965830Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-10T06:31:04.303077+00:00","source":"crossref"},{"observed_at":"2026-08-10T06:30:57.382061+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:27:36.015930Z","title":"Chipgpt: How far are we from natural language hardware design,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":6,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:36.015930Z"},"links":{"citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:2ac95b05d3575a1cb5582274ceec9646043bfc0a6d9c100ed6e6c3de4b4a25f9","observation_id":"f5b14f88-5514-41d2-a174-7af720141848","resolution":{"observed_at":"2026-08-07T05:27:36.015930Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2507.06261","last_updated":"2025-12-19T14:25:46Z","snapshot_observed_at":"2026-07-06T02:11:23.670680Z","submitted_at":"2025-07-07T17:36:04Z","title":"Gemini 2.5: Pushing the Frontier with Advanced Reasoning, Multimodality, Long Context, and Next Generation Agentic Capabilities","version":6},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2507.06261","snapshot_observed_at":"2026-08-07T05:27:36.020854Z","title":"Gemini 2.5: Pushing the frontier with advanced reasoning, multimodality, long context, and next generation agentic capabilities,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:36.020854Z"},"links":{"cited_paper":"/paper/2507.06261","citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:23c3e0ef1cb0b8a5a2107b39a7908e28629c868c85cb6549b73a0bdc27f08105","observation_id":"a13aab40-fade-4027-ac33-0a1050142589","resolution":{"observed_at":"2026-08-07T05:27:36.020854Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:27:36.944169Z","title":"Exploring and characterizing large language models for embedded system development and debugging,","venue":null,"work_id":"6a82d8e3-5e0e-4e09-9b91-d9c922fde8ba","year":null},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":8,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:36.026097Z"},"links":{"citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:9e73392cfc26ca5b112da5e4106026d44d24985764154aaf839ad7c7a6050dd7","observation_id":"81d4d43d-c720-47ba-882f-61fbd6922e57","resolution":{"observed_at":"2026-08-07T05:27:36.949302Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-10T06:31:04.303077+00:00","source":"crossref"},{"observed_at":"2026-08-10T06:30:57.382061+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:27:36.036648Z","title":"Assertllm: Generating and evaluating hardware verification assertions from design specifications via multi-llms,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:36.036648Z"},"links":{"citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:b9decf473557e9035fa5b91904b37325f0f6ef8ea2efda855e62f38bd5c17481","observation_id":"f0dc5c48-bec0-4f9a-a2cc-4da267792734","resolution":{"observed_at":"2026-08-07T05:27:36.036648Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2403.16750","last_updated":"2024-03-25T13:23:24Z","snapshot_observed_at":"2026-08-09T21:46:36.036564Z","submitted_at":"2024-03-25T13:23:24Z","title":"All Artificial, Less Intelligence: GenAI through the Lens of Formal Verification","version":1},"cited_work":{"arxiv_id":"2403.16750","doi":null,"metadata_source":"pith","pith_arxiv_id":"2403.16750","snapshot_observed_at":"2026-08-07T05:27:36.530437Z","title":"All Artificial, Less Intelligence: GenAI through the Lens of Formal Verification","venue":"cs.AI","work_id":"19cc550e-c7f1-43cb-a804-56f86169874b","year":2024},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:36.042370Z"},"links":{"cited_paper":"/paper/2403.16750","citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:2f8266edb4ea757cbec60c6e29dd9c187173452f136a5db18e8f1bd8ff5c9c1f","observation_id":"82e2afc0-e2b0-4986-a30e-1e2f9011d4e1","resolution":{"observed_at":"2026-08-07T05:27:36.537268Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-10T06:31:04.303077+00:00","source":"crossref"},{"observed_at":"2026-08-10T06:30:57.382061+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2504.01986","last_updated":"2025-05-30T14:28:59Z","snapshot_observed_at":"2026-08-07T16:25:56.057428Z","submitted_at":"2025-03-31T07:43:12Z","title":"TuRTLe: A Unified Evaluation of LLMs for RTL Generation","version":2},"cited_work":{"arxiv_id":"2504.01986","doi":null,"metadata_source":"pith","pith_arxiv_id":"2504.01986","snapshot_observed_at":"2026-08-07T05:27:36.502241Z","title":"TuRTLe: A Unified Evaluation of LLMs for RTL Generation","venue":"cs.AR","work_id":"03e891e5-96e9-4b78-8cfb-2548c2f60db9","year":2025},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":11,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:36.047661Z"},"links":{"cited_paper":"/paper/2504.01986","citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:604203fc1b74f6f734f63245e3b97c4ef3e4c76eb30ca01a04071ac784d486c7","observation_id":"b9940c38-714a-4236-8195-7e29b7fbb732","resolution":{"observed_at":"2026-08-07T05:27:36.510441Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-10T06:31:04.303077+00:00","source":"crossref"},{"observed_at":"2026-08-10T06:30:57.382061+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2406.00115","last_updated":"2024-05-31T18:06:15Z","snapshot_observed_at":"2026-07-06T18:23:31.520359Z","submitted_at":"2024-05-31T18:06:15Z","title":"Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correction","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2406.00115","snapshot_observed_at":"2026-08-07T05:27:36.054040Z","title":"Towards llm-powered verilog rtl assistant: Self-verification and self-correction,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":12,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:36.054040Z"},"links":{"cited_paper":"/paper/2406.00115","citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:532703e128750bc5a68571463ad26bd631850ebfe9c0b01feafea9b5c095fe1c","observation_id":"480b4146-1067-4756-8dac-0222d286ce71","resolution":{"observed_at":"2026-08-07T05:27:36.054040Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2411.04905","last_updated":"2025-03-20T03:28:56Z","snapshot_observed_at":"2026-08-08T14:21:42.036023Z","submitted_at":"2024-11-07T17:47:25Z","title":"OpenCoder: The Open Cookbook for Top-Tier Code Large Language Models","version":3},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2411.04905","snapshot_observed_at":"2026-08-07T05:27:36.059269Z","title":"Opencoder: The open cookbook for top-tier code large language models,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":13,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:36.059269Z"},"links":{"cited_paper":"/paper/2411.04905","citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:8ece97a5afed3394ede3088d82443726165af125902302eea4dc057953e48c64","observation_id":"cdce50b4-bde1-4bc4-a851-b49ac8bc7e76","resolution":{"observed_at":"2026-08-07T05:27:36.059269Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2409.12186","last_updated":"2024-11-12T13:24:25Z","snapshot_observed_at":"2026-07-06T02:11:23.670680Z","submitted_at":"2024-09-18T17:57:57Z","title":"Qwen2.5-Coder Technical Report","version":3},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2409.12186","snapshot_observed_at":"2026-08-07T05:27:36.064345Z","title":"Qwen2. 5-coder technical report,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:36.064345Z"},"links":{"cited_paper":"/paper/2409.12186","citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:f35aeb5cb772122723633329a1824940e2f38051aabec8af4cd82231ee8b0377","observation_id":"6a8e573e-2b64-4a4c-8232-9f0412a38426","resolution":{"observed_at":"2026-08-07T05:27:36.064345Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:27:36.926490Z","title":"Automated synthesis of hardware designs using symbolic feedback and grammar-constrained decoding in large language models,","venue":null,"work_id":"6932a397-f606-426c-a9a6-2ece598e3870","year":2024},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":15,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:36.069289Z"},"links":{"citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:ae9f8af04f2235e74004a3a94632b7ea35f480a6847d44281c1d7771f6becadc","observation_id":"99dff6dc-cb93-4a92-a504-cc7da5f9e6ee","resolution":{"observed_at":"2026-08-07T05:27:36.932675Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-10T06:31:04.303077+00:00","source":"crossref"},{"observed_at":"2026-08-10T06:30:57.382061+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2406.00515","last_updated":"2024-11-10T22:02:27Z","snapshot_observed_at":"2026-07-29T20:40:25.374189Z","submitted_at":"2024-06-01T17:48:15Z","title":"A Survey on Large Language Models for Code Generation","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2406.00515","snapshot_observed_at":"2026-08-07T05:27:36.074233Z","title":"A survey on large language models for code generation,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":16,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:36.074233Z"},"links":{"cited_paper":"/paper/2406.00515","citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:4862b902668c311f6a0cfd06db7eba08d1fda180c0c1bd6855c16b16945369cc","observation_id":"a13f2fad-4efe-404f-a1bd-d2098181a5f6","resolution":{"observed_at":"2026-08-07T05:27:36.074233Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:27:36.908951Z","title":"Swe-bench: Can language models resolve real-world github issues?","venue":null,"work_id":"a80782bc-9731-4ee6-842c-fc8d1b6bba2b","year":2024},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:36.078956Z"},"links":{"citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:376cabe95fe6de01d4ed8cc9ecd9ff3f56b18e28840a0453db9edda0ae8c8976","observation_id":"0abd343c-98e5-489f-8f15-9ec8e49526ad","resolution":{"observed_at":"2026-08-07T05:27:36.914156Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-10T06:31:04.303077+00:00","source":"crossref"},{"observed_at":"2026-08-10T06:30:57.382061+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:27:36.892681Z","title":"Hdleval benchmarking llms for multiple hdls,","venue":null,"work_id":"33727b82-4081-4c0e-9f4d-fb2caa0a7bc5","year":2024},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":18,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:36.083609Z"},"links":{"citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:4ce93196ac0da3d4878bbafb1b5d2dc7971bde30032dbf8edc1cfde92bb27531","observation_id":"efc90441-1487-4947-834d-f48e5be24243","resolution":{"observed_at":"2026-08-07T05:27:36.897910Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-10T06:31:04.303077+00:00","source":"crossref"},{"observed_at":"2026-08-10T06:30:57.382061+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:27:36.876454Z","title":"Uart communication protocol and how it works,","venue":null,"work_id":"775f2f2f-99e4-4833-afcd-691f28ed77bc","year":2022},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":19,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:36.088017Z"},"links":{"citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:6f36c1a88745d226457f339e980cbb403b8f76769dc8d190ed20b1e0d0011ce9","observation_id":"727aff90-8517-4575-9cd1-500477bfec37","resolution":{"observed_at":"2026-08-07T05:27:36.881511Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-10T06:31:04.303077+00:00","source":"crossref"},{"observed_at":"2026-08-10T06:30:57.382061+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:27:36.860925Z","title":"Interfacing of mems motion sensor with fpga using i2c protocol,","venue":null,"work_id":"9821d016-e47c-4bde-9549-18be82a0b446","year":2017},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":20,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:36.092866Z"},"links":{"citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:7b6c356ddc817ed560795ede51c314a4c625124cba3c04658fb3d6c7971c9504","observation_id":"e6661c43-60c1-4878-9e4c-8e08e5462dbb","resolution":{"observed_at":"2026-08-07T05:27:36.865817Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-10T06:31:04.303077+00:00","source":"crossref"},{"observed_at":"2026-08-10T06:30:57.382061+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:27:36.844984Z","title":"Autosilicon: Scaling up rtl design generation capability of large language models,","venue":null,"work_id":"49b6c253-83fa-43f2-a2e1-f90343962f10","year":2025},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":21,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:36.097366Z"},"links":{"citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:0e29b623e4a46e6102dcaddf926af31820f4767ca034ed878ef287d4df662d23","observation_id":"c78d5a6f-3809-4a0b-9678-d3c6db89e1bb","resolution":{"observed_at":"2026-08-07T05:27:36.850067Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-10T06:31:04.303077+00:00","source":"crossref"},{"observed_at":"2026-08-10T06:30:57.382061+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2305.06161","last_updated":"2023-12-13T14:44:10Z","snapshot_observed_at":"2026-07-06T15:25:35.930688Z","submitted_at":"2023-05-09T08:16:42Z","title":"StarCoder: may the source be with you!","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2305.06161","snapshot_observed_at":"2026-08-07T05:27:36.101730Z","title":"Starcoder: may the source be with you!","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":22,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:36.101730Z"},"links":{"cited_paper":"/paper/2305.06161","citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:99eb2c1309e8bcb14fdfea784c92e994b94a010374a20cccf958a57e19562197","observation_id":"ba35aa8f-fdf2-426a-b9d7-5bc7501dfe49","resolution":{"observed_at":"2026-08-07T05:27:36.101730Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:27:36.106823Z","title":"Verilogeval: Evaluating large language models for verilog code generation,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":23,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:36.106823Z"},"links":{"citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:ce4c2dd3f862c0cd923eb16f78494b03ea877fbae8ded7cf661cdaff968d1c4f","observation_id":"a246702b-d547-46a2-92a2-6b623bb95b4c","resolution":{"observed_at":"2026-08-07T05:27:36.106823Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2402.19173","last_updated":"2024-02-29T13:53:35Z","snapshot_observed_at":"2026-07-06T02:11:23.670680Z","submitted_at":"2024-02-29T13:53:35Z","title":"StarCoder 2 and The Stack v2: The Next Generation","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2402.19173","snapshot_observed_at":"2026-08-07T05:27:36.111466Z","title":"Starcoder 2 and the stack v2: The next generation,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":24,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:36.111466Z"},"links":{"cited_paper":"/paper/2402.19173","citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:687f5f7c255b559bc878a6baccbf6f6a353c868eb495b9fb32186b51f82c9908","observation_id":"92fa7bc8-35c0-406d-92b9-1d11ad3eed08","resolution":{"observed_at":"2026-08-07T05:27:36.111466Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2308.05345","last_updated":"2023-11-11T07:53:10Z","snapshot_observed_at":"2026-07-06T16:04:42.791957Z","submitted_at":"2023-08-10T05:24:41Z","title":"RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model","version":3},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2308.05345","snapshot_observed_at":"2026-08-07T05:27:36.116201Z","title":"Rtllm: An open-source benchmark for design rtl generation with large language model,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":25,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:36.116201Z"},"links":{"cited_paper":"/paper/2308.05345","citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:72091d7eaccd8cb23032e3d1e187e4b1cf15b6d668b65997acfe5fe4efd896c8","observation_id":"e00af0db-2ebd-456b-967f-954bb8a5dc2b","resolution":{"observed_at":"2026-08-07T05:27:36.116201Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:27:36.817927Z","title":"Rtllm: An open-source benchmark for design rtl generation with large language model,","venue":null,"work_id":"cb84aded-4b41-4a4b-88e4-c32e007ebd9e","year":2024},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":26,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:36.120883Z"},"links":{"citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:9b469ecc3281c742cdde82aafc9f03f5fa9c54d297773537c4fa74c1efcb3037","observation_id":"938291ee-6b64-4992-ace6-d302e6a2d94d","resolution":{"observed_at":"2026-08-07T05:27:36.822971Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-10T06:31:04.303077+00:00","source":"crossref"},{"observed_at":"2026-08-10T06:30:57.382061+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:27:36.801734Z","title":"Serial peripheral interface (spi),","venue":null,"work_id":"02011abc-d022-4860-875b-fe4008593376","year":2025},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":27,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:36.125783Z"},"links":{"citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:71266b701cb876c72c86b2c37ce8ede338357f57e647f546077c1159b8dda719","observation_id":"15d63152-2ca2-49fc-8014-55e5ec79bebd","resolution":{"observed_at":"2026-08-07T05:27:36.806684Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-10T06:31:04.303077+00:00","source":"crossref"},{"observed_at":"2026-08-10T06:30:57.382061+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:27:36.130808Z","title":"Gpt-4.1,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":28,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:36.130808Z"},"links":{"citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:89841688c3e255a178fcadb96f03b841634fb09848d8da76095249fc66d22379","observation_id":"5f92df7d-5544-4b77-ac76-9a1af6ebe627","resolution":{"observed_at":"2026-08-07T05:27:36.130808Z","resolver_source":null,"status":"parse_uncertain"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2303.08774","last_updated":"2024-03-04T06:01:33Z","snapshot_observed_at":"2026-08-07T07:30:12.213965Z","submitted_at":"2023-03-15T17:15:04Z","title":"GPT-4 Technical Report","version":6},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2303.08774","snapshot_observed_at":"2026-08-07T05:27:36.135599Z","title":"Gpt-4 technical report,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":29,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:36.135599Z"},"links":{"cited_paper":"/paper/2303.08774","citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:963410b2fd5d8f3fad7aed560d85e023c628747e0716de3f4e2e71f8c6bcc955","observation_id":"4b80fe08-1b9b-4033-bd8a-07b0e93d445c","resolution":{"observed_at":"2026-08-07T05:27:36.135599Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:27:36.140642Z","title":"A survey of research in large language models for electronic design automation,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":30,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:36.140642Z"},"links":{"citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:ca54f8181084f7bfe43d31aeb2cd19f1979635b9bfff598dbca00b65215e7c6b","observation_id":"4414c998-2e4e-4c46-9e2b-2bd766721ff5","resolution":{"observed_at":"2026-08-07T05:27:36.140642Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:27:36.762250Z","title":"Usart, spi, i2c, and communication protocols,","venue":null,"work_id":"b95b2ac3-d0d2-4a41-8739-2af89b10ea8f","year":2024},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":31,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:36.145806Z"},"links":{"citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:b8c7ea8763e2b9b2c969881849ce9066f4899beed945990a4770f70b285325db","observation_id":"2d967e3a-bbce-4a8a-ac51-069d61d88105","resolution":{"observed_at":"2026-08-07T05:27:36.767363Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-10T06:31:04.303077+00:00","source":"crossref"},{"observed_at":"2026-08-10T06:30:57.382061+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2408.02793","last_updated":"2024-08-05T19:19:30Z","snapshot_observed_at":"2026-08-10T01:20:53.877719Z","submitted_at":"2024-08-05T19:19:30Z","title":"Evaluating Large Language Models for Automatic Register Transfer Logic Generation via High-Level Synthesis","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2408.02793","snapshot_observed_at":"2026-08-07T05:27:36.151403Z","title":"Evaluating large language models for automatic register transfer logic generation via high-level synthesis,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":32,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:36.151403Z"},"links":{"cited_paper":"/paper/2408.02793","citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:4c07f8fefd7be179c84ef0d5a6791c1577f613d74ffe240ecf790d26b360d398","observation_id":"04278365-2610-4d17-b8bd-c3e561e715ff","resolution":{"observed_at":"2026-08-07T05:27:36.151403Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:27:36.156625Z","title":"Benchmarking large language models for auto- mated verilog rtl code generation,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":33,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:36.156625Z"},"links":{"citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:79e512c652b19f5e7a305cd2922b538e2d84c00c7e81d925c76a672081070786","observation_id":"143cba06-df52-46a9-98c9-e22a1442607f","resolution":{"observed_at":"2026-08-07T05:27:36.156625Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:27:36.162177Z","title":"Verigen: A large language model for verilog code generation,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":34,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:36.162177Z"},"links":{"citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:7c2a937ba1c0949700a0889c6ca979c23b927ff147535c35aa99c369597404ef","observation_id":"1b5f1a72-d916-46ae-889a-c82741b68563","resolution":{"observed_at":"2026-08-07T05:27:36.162177Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2406.04379","last_updated":"2024-06-06T00:06:50Z","snapshot_observed_at":"2026-08-05T01:53:28.686684Z","submitted_at":"2024-06-06T00:06:50Z","title":"VHDL-Eval: A Framework for Evaluating Large Language Models in VHDL Code Generation","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2406.04379","snapshot_observed_at":"2026-08-07T05:27:36.167362Z","title":"Vhdl-eval: A framework for evaluating large language models in vhdl code generation,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":35,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:36.167362Z"},"links":{"cited_paper":"/paper/2406.04379","citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:e9a861fb417047c64572d9b646c2f195c286f8acb4a3267c15655ddc9b8596d3","observation_id":"b3f22a93-62c7-4fd8-a916-62af175fc489","resolution":{"observed_at":"2026-08-07T05:27:36.167362Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:27:36.721982Z","title":"Understanding the i2c bus: A beginner’s guide to simplifying communication,","venue":null,"work_id":"e777cd13-4a98-4c4f-ad1e-d57bf04331d8","year":2024},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":36,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:36.173134Z"},"links":{"citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:682c6a30b4e3d82583b49a518fcbfb660901517e9c896f4f36930c2b0d011df4","observation_id":"083f52ca-2d37-470b-9301-ad9c16a37aed","resolution":{"observed_at":"2026-08-07T05:27:36.727498Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-10T06:31:04.303077+00:00","source":"crossref"},{"observed_at":"2026-08-10T06:30:57.382061+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2504.03723","last_updated":"2025-07-13T08:44:02Z","snapshot_observed_at":"2026-08-07T16:27:20.178881Z","submitted_at":"2025-03-30T15:44:22Z","title":"VFlow: Discovering Optimal Agentic Workflows for Verilog Generation","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2504.03723","snapshot_observed_at":"2026-08-07T05:27:36.178869Z","title":"Vflow: Discovering optimal agentic workflows for verilog generation,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":37,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:36.178869Z"},"links":{"cited_paper":"/paper/2504.03723","citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:6ec8994968d5941068e322a93d0d44ac4817630ccb5426c82158d47f05569998","observation_id":"a062c18c-e004-42bb-849d-172756067885","resolution":{"observed_at":"2026-08-07T05:27:36.178869Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T05:27:36.184407Z","title":"Verithoughts: Enabling automated verilog code generation us- ing reasoning and formal verification,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":38,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:36.184407Z"},"links":{"citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:f2ef5c40e2f42efe0766e0aa276795beaa1de330c3b72b91538c5a09af5d4527","observation_id":"ea8c9136-d970-41f8-99eb-74bb7764cec1","resolution":{"observed_at":"2026-08-07T05:27:36.184407Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2307.03817","last_updated":"2023-11-22T01:26:07Z","snapshot_observed_at":"2026-08-10T06:23:12.651657Z","submitted_at":"2023-07-07T20:14:22Z","title":"Exploring and Characterizing Large Language Models For Embedded System Development and Debugging","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2307.03817","snapshot_observed_at":"2026-08-07T05:27:36.031238Z","title":"Available: https://arxiv.org/abs/2307.03817","venue":null,"work_id":null,"year":null},"citing_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"reference_index":2023,"source":"pdf_text","source_observed_at":"2026-08-07T05:27:36.031238Z"},"links":{"cited_paper":"/paper/2307.03817","citing_paper":"/paper/2506.07945"},"observation_digest":"sha256:7a4e2b861f71a86a05abb64e2799f5f372614d9a2dff28db04f92c8c7a972e7a","observation_id":"006295bd-5943-4edf-964a-f56f2a0a00bd","resolution":{"observed_at":"2026-08-07T05:27:36.031238Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}}],"paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","latest_version":2,"primary_category":"cs.AR","snapshot_observed_at":"2026-08-07T22:12:34.938175Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols"},"reference_resolution":{"displayed":39,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":1,"unresolved":21,"verified_exact":2,"verified_fuzzy":15},"total_outbound_references":39},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-10T06:31:04.303077+00:00","source":"crossref"},{"observed_at":"2026-08-10T06:30:57.382061+00:00","source":"retraction_watch"}],"thesis":"As of 10 August 2026, this Paper Citation Record lists 39 of 39 outbound references and 1 inbound Pith citation observation for arXiv:2506.07945."}