{"as_of":"2026-08-22T02:44:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:15e56e23b9dbc7ef6f90dd4afcf8d2a8e9fb551536c3e28f09fd8ae2f7d6ee25","coverage":[{"denominator":17,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":17,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-07T00:40:25.355515Z","state":"measured"},{"denominator":17,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":17,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-21T06:32:19.484+00:00","state":"measured"},{"denominator":0,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"cited_works","source_observed_at":null,"state":"measured"}],"external_citation_measurements":[],"inbound":[],"links":{"evidence":"/evidence","html":"/paper/2506.12968/citation-record","integrity":"/paper/2506.12968/integrity","json":"/paper/2506.12968/citation-record.json","paper":"/paper/2506.12968"},"outbound":[{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T00:40:28.100031Z","title":"High-Performance Vision-Based Navigation on SoC FPGA for Spacecraft Proximity Operations,","venue":null,"work_id":"06362c66-c250-43cb-8e53-a03ac959e96c","year":2020},"citing_paper":{"arxiv_id":"2506.12968","last_updated":"2025-06-15T21:26:59Z","snapshot_observed_at":"2026-08-21T23:49:36.995707Z","submitted_at":"2025-06-15T21:26:59Z","title":"FPGA & VPU Co-Processing in Space Applications: Development and Testing with DSP/AI Benchmarks","version":1},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-08-07T00:40:24.235752Z"},"links":{"citing_paper":"/paper/2506.12968"},"observation_digest":"sha256:3a43dc08f2981d686db9ffced29451e8ac8590a9b2b4fca3aaf2579bd817de29","observation_id":"6b318732-1224-4eb6-a44b-876f77eb8391","resolution":{"observed_at":"2026-08-07T00:40:28.228674Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T00:40:27.697153Z","title":"Development and Testing on the European Space-Grade BRA VE FPGAs: Evaluation of NG-Large Using High-Performance DSP Benchmarks,","venue":null,"work_id":"9a7221a2-e2ea-4665-b556-a032aae27019","year":2021},"citing_paper":{"arxiv_id":"2506.12968","last_updated":"2025-06-15T21:26:59Z","snapshot_observed_at":"2026-08-21T23:49:36.995707Z","submitted_at":"2025-06-15T21:26:59Z","title":"FPGA & VPU Co-Processing in Space Applications: Development and Testing with DSP/AI Benchmarks","version":1},"reference_index":2,"source":"pdf_text","source_observed_at":"2026-08-07T00:40:24.306024Z"},"links":{"citing_paper":"/paper/2506.12968"},"observation_digest":"sha256:07c9b74a3bec110279b18461b316fc926b80e2629f068f3c865b179bf2804bf1","observation_id":"6f445a9a-c01d-4ae7-9602-c6af2474d9c3","resolution":{"observed_at":"2026-08-07T00:40:27.859125Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T00:40:27.416888Z","title":"Improving Performance-Power-Programmability in Space Avionics with Edge Devices: VBN on Myriad2 SoC,","venue":null,"work_id":"b44b6f6e-2b58-463c-a5fb-2b7168d5a027","year":2021},"citing_paper":{"arxiv_id":"2506.12968","last_updated":"2025-06-15T21:26:59Z","snapshot_observed_at":"2026-08-21T23:49:36.995707Z","submitted_at":"2025-06-15T21:26:59Z","title":"FPGA & VPU Co-Processing in Space Applications: Development and Testing with DSP/AI Benchmarks","version":1},"reference_index":3,"source":"pdf_text","source_observed_at":"2026-08-07T00:40:24.356673Z"},"links":{"citing_paper":"/paper/2506.12968"},"observation_digest":"sha256:fec1ac1e397046c2cd437430e61fb4664619ba75732afb21c436ed858a9460b3","observation_id":"e215acf9-781d-4755-8d90-779b23034541","resolution":{"observed_at":"2026-08-07T00:40:27.529608Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T00:40:27.202464Z","title":"Onboard Processing with Hybrid and Reconfigurable Computing on Small Satellites,","venue":null,"work_id":"babe5279-074a-4e4d-a61f-ac932aec942b","year":2018},"citing_paper":{"arxiv_id":"2506.12968","last_updated":"2025-06-15T21:26:59Z","snapshot_observed_at":"2026-08-21T23:49:36.995707Z","submitted_at":"2025-06-15T21:26:59Z","title":"FPGA & VPU Co-Processing in Space Applications: Development and Testing with DSP/AI Benchmarks","version":1},"reference_index":4,"source":"pdf_text","source_observed_at":"2026-08-07T00:40:24.432669Z"},"links":{"citing_paper":"/paper/2506.12968"},"observation_digest":"sha256:e7f4e699265c6e12cf78f77b3fa17df1a7df8901af195df7c9a7dabe7ecf06c5","observation_id":"2e898c99-3644-4190-ad63-18f04954398d","resolution":{"observed_at":"2026-08-07T00:40:27.308042Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T00:40:26.986539Z","title":"System-Level Architecture for Mixed Crit- icality Applications on MPSoC: A Space Application,","venue":null,"work_id":"320c987b-b881-4cb4-87cd-284c0a6d125b","year":2017},"citing_paper":{"arxiv_id":"2506.12968","last_updated":"2025-06-15T21:26:59Z","snapshot_observed_at":"2026-08-21T23:49:36.995707Z","submitted_at":"2025-06-15T21:26:59Z","title":"FPGA & VPU Co-Processing in Space Applications: Development and Testing with DSP/AI Benchmarks","version":1},"reference_index":5,"source":"pdf_text","source_observed_at":"2026-08-07T00:40:24.473275Z"},"links":{"citing_paper":"/paper/2506.12968"},"observation_digest":"sha256:0f11f3f6acf88829776940f5ea082e51b1b987c18d01c8ea88ba4fad1c51bb96","observation_id":"895f92c3-2283-486c-96ce-c2f369139959","resolution":{"observed_at":"2026-08-07T00:40:27.088727Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T00:40:26.867999Z","title":"Towards an Integrated GPU Accelerated SoC as a Flight Computer for Small Satellites,","venue":null,"work_id":"88cf137f-213b-454b-b8c6-955bb15fff5b","year":2019},"citing_paper":{"arxiv_id":"2506.12968","last_updated":"2025-06-15T21:26:59Z","snapshot_observed_at":"2026-08-21T23:49:36.995707Z","submitted_at":"2025-06-15T21:26:59Z","title":"FPGA & VPU Co-Processing in Space Applications: Development and Testing with DSP/AI Benchmarks","version":1},"reference_index":6,"source":"pdf_text","source_observed_at":"2026-08-07T00:40:24.574320Z"},"links":{"citing_paper":"/paper/2506.12968"},"observation_digest":"sha256:3adc1df2ff74168aaa285e5713d24995edafc14f16e63328c9af687777eff608","observation_id":"ed85b417-098c-4b9f-9269-d3c89256e8f2","resolution":{"observed_at":"2026-08-07T00:40:26.940591Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T00:40:26.732960Z","title":"Enabling Radiation Tolerant Heterogeneous GPU-based Onboard Data Processing in Space,","venue":null,"work_id":"80216c14-fd36-4424-a3c2-b3f217c2ffd7","year":2020},"citing_paper":{"arxiv_id":"2506.12968","last_updated":"2025-06-15T21:26:59Z","snapshot_observed_at":"2026-08-21T23:49:36.995707Z","submitted_at":"2025-06-15T21:26:59Z","title":"FPGA & VPU Co-Processing in Space Applications: Development and Testing with DSP/AI Benchmarks","version":1},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-08-07T00:40:24.663885Z"},"links":{"citing_paper":"/paper/2506.12968"},"observation_digest":"sha256:391d2feedbc5958b1d1e6da76431b0e5b43a6825567dd60315e70d9e3028e664","observation_id":"09a3b916-a34a-4c23-bd30-3139df1daf23","resolution":{"observed_at":"2026-08-07T00:40:26.790355Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T00:40:26.608657Z","title":"Run-Time Reconfigurable MPSoC- Based On-Board Processor for Vision-Based Space Navigation,","venue":null,"work_id":"4ce3c477-ca3f-49c5-ba7c-132957d08d67","year":2020},"citing_paper":{"arxiv_id":"2506.12968","last_updated":"2025-06-15T21:26:59Z","snapshot_observed_at":"2026-08-21T23:49:36.995707Z","submitted_at":"2025-06-15T21:26:59Z","title":"FPGA & VPU Co-Processing in Space Applications: Development and Testing with DSP/AI Benchmarks","version":1},"reference_index":8,"source":"pdf_text","source_observed_at":"2026-08-07T00:40:24.739918Z"},"links":{"citing_paper":"/paper/2506.12968"},"observation_digest":"sha256:9cbcdb817dec5b18bb8846bd310245d2759f3cf529d2df84894c2520bacfedcd","observation_id":"c0e60fc3-dc3d-4699-9797-c36dc8944c4b","resolution":{"observed_at":"2026-08-07T00:40:26.660718Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T00:40:26.455969Z","title":"Always-on Vision Processing Unit for Mobile Applications,","venue":null,"work_id":"c38436da-45a4-40ee-9da4-ce9ab4eb1f70","year":2015},"citing_paper":{"arxiv_id":"2506.12968","last_updated":"2025-06-15T21:26:59Z","snapshot_observed_at":"2026-08-21T23:49:36.995707Z","submitted_at":"2025-06-15T21:26:59Z","title":"FPGA & VPU Co-Processing in Space Applications: Development and Testing with DSP/AI Benchmarks","version":1},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-08-07T00:40:24.852773Z"},"links":{"citing_paper":"/paper/2506.12968"},"observation_digest":"sha256:d4eaacc529ea4d97a4a493ad70a1aa4e3fdd639ba70764a59ff0b110986cf625","observation_id":"13aaecbf-0d0d-4c5c-bbde-7379090d03a8","resolution":{"observed_at":"2026-08-07T00:40:26.519178Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T00:40:26.254281Z","title":"GAP-8: A RISC-V SoC for AI at the Edge of the IoT,","venue":null,"work_id":"8f7e323c-9d7a-4b65-8229-360f97a3620b","year":2018},"citing_paper":{"arxiv_id":"2506.12968","last_updated":"2025-06-15T21:26:59Z","snapshot_observed_at":"2026-08-21T23:49:36.995707Z","submitted_at":"2025-06-15T21:26:59Z","title":"FPGA & VPU Co-Processing in Space Applications: Development and Testing with DSP/AI Benchmarks","version":1},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-08-07T00:40:24.920081Z"},"links":{"citing_paper":"/paper/2506.12968"},"observation_digest":"sha256:cc28c51faec95bff31503b5aa72bfc5d7063df17bf0dd9ce4824edb90a0833f6","observation_id":"3e35602b-5c6e-4ddd-b646-57724acf3427","resolution":{"observed_at":"2026-08-07T00:40:26.354250Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T00:40:26.145235Z","title":"High-Performance Compute Board – A Fault-Tolerant Module for On-Board Vision Processing,","venue":null,"work_id":"3a10da58-361b-4163-88f1-47d1b6693559","year":2021},"citing_paper":{"arxiv_id":"2506.12968","last_updated":"2025-06-15T21:26:59Z","snapshot_observed_at":"2026-08-21T23:49:36.995707Z","submitted_at":"2025-06-15T21:26:59Z","title":"FPGA & VPU Co-Processing in Space Applications: Development and Testing with DSP/AI Benchmarks","version":1},"reference_index":11,"source":"pdf_text","source_observed_at":"2026-08-07T00:40:24.998009Z"},"links":{"citing_paper":"/paper/2506.12968"},"observation_digest":"sha256:6fcfbd9e56870547cefd212a3d4826d058be1f96d77ecb853788374e39a53e1d","observation_id":"17905f13-b75a-4cc9-8294-e51208ce139c","resolution":{"observed_at":"2026-08-07T00:40:26.194984Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T00:40:26.016587Z","title":"[Online]","venue":null,"work_id":"8936fe71-8e47-4c2b-b55b-39c513de42b5","year":2021},"citing_paper":{"arxiv_id":"2506.12968","last_updated":"2025-06-15T21:26:59Z","snapshot_observed_at":"2026-08-21T23:49:36.995707Z","submitted_at":"2025-06-15T21:26:59Z","title":"FPGA & VPU Co-Processing in Space Applications: Development and Testing with DSP/AI Benchmarks","version":1},"reference_index":12,"source":"pdf_text","source_observed_at":"2026-08-07T00:40:25.050806Z"},"links":{"citing_paper":"/paper/2506.12968"},"observation_digest":"sha256:2ab57c8d9c70eee1b9c6d09ba0580533d5c679456478389f4f6ac32d116c0389","observation_id":"cd316342-12e3-445a-b64d-0fc90218a527","resolution":{"observed_at":"2026-08-07T00:40:26.068460Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T00:40:25.881948Z","title":"[Online]","venue":null,"work_id":"c647ce46-ef4d-4f90-b801-53ed4f87ef0a","year":2021},"citing_paper":{"arxiv_id":"2506.12968","last_updated":"2025-06-15T21:26:59Z","snapshot_observed_at":"2026-08-21T23:49:36.995707Z","submitted_at":"2025-06-15T21:26:59Z","title":"FPGA & VPU Co-Processing in Space Applications: Development and Testing with DSP/AI Benchmarks","version":1},"reference_index":13,"source":"pdf_text","source_observed_at":"2026-08-07T00:40:25.121004Z"},"links":{"citing_paper":"/paper/2506.12968"},"observation_digest":"sha256:471eeb85f51d370e1e77303356746196c30a3c14b2c3145f83a87532a1a2f9ca","observation_id":"9d3ec1b5-e49b-4203-ad54-75c43b42c2ef","resolution":{"observed_at":"2026-08-07T00:40:25.928815Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T00:40:25.743695Z","title":"[Online]","venue":null,"work_id":"3e0e6e8f-d892-4464-9e06-d39a93dbd756","year":2021},"citing_paper":{"arxiv_id":"2506.12968","last_updated":"2025-06-15T21:26:59Z","snapshot_observed_at":"2026-08-21T23:49:36.995707Z","submitted_at":"2025-06-15T21:26:59Z","title":"FPGA & VPU Co-Processing in Space Applications: Development and Testing with DSP/AI Benchmarks","version":1},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-08-07T00:40:25.188024Z"},"links":{"citing_paper":"/paper/2506.12968"},"observation_digest":"sha256:3607aad14dcc5e8a1c2c7490fc82854ed4368f2d6f01cf59d890984f4f644cc6","observation_id":"8a16904d-f3e7-4897-8d02-b3b0f450ddf1","resolution":{"observed_at":"2026-08-07T00:40:25.815027Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T00:40:25.662229Z","title":"March 2021)","venue":null,"work_id":"5d4af04e-e845-40b1-92cd-07e6607b069d","year":2018},"citing_paper":{"arxiv_id":"2506.12968","last_updated":"2025-06-15T21:26:59Z","snapshot_observed_at":"2026-08-21T23:49:36.995707Z","submitted_at":"2025-06-15T21:26:59Z","title":"FPGA & VPU Co-Processing in Space Applications: Development and Testing with DSP/AI Benchmarks","version":1},"reference_index":15,"source":"pdf_text","source_observed_at":"2026-08-07T00:40:25.225551Z"},"links":{"citing_paper":"/paper/2506.12968"},"observation_digest":"sha256:3d28bf214895619f6651123dbc226d3f371456143d3838bc4bc101717aead33a","observation_id":"47b57718-558b-4d65-a48a-97cc5d2394b3","resolution":{"observed_at":"2026-08-07T00:40:25.697287Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T00:40:25.560649Z","title":"High- Performance COTS FPGA SoC for Parallel Hyperspectral Image Com- pression with CCSDS-123.0-B-1,","venue":null,"work_id":"3f3a4632-1cc2-4f9e-9003-91104bcf0e00","year":2020},"citing_paper":{"arxiv_id":"2506.12968","last_updated":"2025-06-15T21:26:59Z","snapshot_observed_at":"2026-08-21T23:49:36.995707Z","submitted_at":"2025-06-15T21:26:59Z","title":"FPGA & VPU Co-Processing in Space Applications: Development and Testing with DSP/AI Benchmarks","version":1},"reference_index":16,"source":"pdf_text","source_observed_at":"2026-08-07T00:40:25.290591Z"},"links":{"citing_paper":"/paper/2506.12968"},"observation_digest":"sha256:d509a172a188adc9e0a80ce24b4ac83975072ee1766e6e72789557b38583bfde","observation_id":"69390928-8635-434f-b3c3-503aea68b03a","resolution":{"observed_at":"2026-08-07T00:40:25.601579Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T00:40:25.451001Z","title":"Combining Arithmetic Approximation Techniques for Improved CNN Circuit Design,","venue":null,"work_id":"1e3827f9-c1b8-4bd9-be6c-60d3b9e5995a","year":2020},"citing_paper":{"arxiv_id":"2506.12968","last_updated":"2025-06-15T21:26:59Z","snapshot_observed_at":"2026-08-21T23:49:36.995707Z","submitted_at":"2025-06-15T21:26:59Z","title":"FPGA & VPU Co-Processing in Space Applications: Development and Testing with DSP/AI Benchmarks","version":1},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-08-07T00:40:25.355515Z"},"links":{"citing_paper":"/paper/2506.12968"},"observation_digest":"sha256:b85492a47d37ff9c795471d6ac18d361efaf48e3a769be0f80fbe647b0a592f1","observation_id":"44723424-ab59-497c-b246-616dc25f70e3","resolution":{"observed_at":"2026-08-07T00:40:25.506968Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"state":"measured"}}],"paper":{"arxiv_id":"2506.12968","last_updated":"2025-06-15T21:26:59Z","latest_version":1,"primary_category":"cs.AR","snapshot_observed_at":"2026-08-21T23:49:36.995707Z","submitted_at":"2025-06-15T21:26:59Z","title":"FPGA & VPU Co-Processing in Space Applications: Development and Testing with DSP/AI Benchmarks"},"reference_resolution":{"displayed":17,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":0,"verified_exact":0,"verified_fuzzy":17},"total_outbound_references":17},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-21T06:32:19.484+00:00","source":"crossref"},{"observed_at":"2026-08-21T06:32:16.066871+00:00","source":"retraction_watch"}],"thesis":"As of 22 August 2026, this Paper Citation Record lists 17 of 17 outbound references and 0 inbound Pith citation observations for arXiv:2506.12968."}