{"as_of":"2026-08-20T23:38:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:7c9e74036f5ffde8211c2122c9a17943e6f21348a3a8e97103ddf1aa322b79ac","coverage":[{"denominator":23,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":23,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-07T04:52:57.712752Z","state":"measured"},{"denominator":24,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":24,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-20T06:33:59.587034+00:00","state":"measured"},{"denominator":1,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":1,"source":"paper_references, paper_reference_links","source_observed_at":"2026-05-08T08:19:42.493657Z","state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"arxiv_reference","source_observed_at":"2026-05-11T20:41:11.936700Z","state":"measured"}],"external_citation_measurements":[],"inbound":[{"citation":{"cited_paper":{"arxiv_id":"2506.13983","last_updated":"2025-06-11T06:43:24Z","snapshot_observed_at":"2026-08-19T23:33:05.092724Z","submitted_at":"2025-06-11T06:43:24Z","title":"SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine","version":1},"cited_work":{"arxiv_id":"2506.13983","doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":"2506.13983","snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"SANGAM: SystemVerilog as- sertion generation via Monte Carlo tree self-refine","venue":null,"work_id":"74da1641-1c68-4990-8f96-5603fdd79bb6","year":2025},"citing_paper":{"arxiv_id":"2604.23100","last_updated":"2026-04-25T01:46:33Z","snapshot_observed_at":"2026-08-15T12:34:43.977560Z","submitted_at":"2026-04-25T01:46:33Z","title":"From Language to Logic: Bridging LLMs & Formal Representations for RTL Assertion Generation","version":1},"reference_index":28,"source":"pdf_text","source_observed_at":"2026-05-08T08:19:42.493657Z"},"links":{"cited_paper":"/paper/2506.13983","citing_paper":"/paper/2604.23100"},"observation_digest":"sha256:326907a762d01aacb19ae11c50fd26db47b556ffe21dabd15ac2bf6b77ee7313","observation_id":"d29a0d0f-92b0-42fb-9a9c-8e46e0e34b70","resolution":{"observed_at":"2026-05-11T20:41:11.951183Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-20T06:33:59.587034+00:00","source":"crossref"},{"observed_at":"2026-08-20T06:33:54.927442+00:00","source":"retraction_watch"}],"state":"measured"}}],"links":{"evidence":"/evidence","html":"/paper/2506.13983/citation-record","integrity":"/paper/2506.13983/integrity","json":"/paper/2506.13983/citation-record.json","paper":"/paper/2506.13983"},"outbound":[{"citation":{"cited_paper":{"arxiv_id":"2306.14027","last_updated":"2024-07-09T21:08:06Z","snapshot_observed_at":"2026-08-20T08:45:16.306897Z","submitted_at":"2023-06-24T17:44:36Z","title":"(Security) Assertions by Large Language Models","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2306.14027","snapshot_observed_at":"2026-08-07T04:52:57.629981Z","title":"Llm-assisted generation of hardware assertions,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2506.13983","last_updated":"2025-06-11T06:43:24Z","snapshot_observed_at":"2026-08-19T23:33:05.092724Z","submitted_at":"2025-06-11T06:43:24Z","title":"SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine","version":1},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-08-07T04:52:57.629981Z"},"links":{"cited_paper":"/paper/2306.14027","citing_paper":"/paper/2506.13983"},"observation_digest":"sha256:0067f68953a93c837d5a3a430115c38022b66811f29885dc08963a43aeac1021","observation_id":"ce441583-6141-4dbe-9ab1-1c4486ef0478","resolution":{"observed_at":"2026-08-07T04:52:57.629981Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:52:58.035232Z","title":"Chiraag: Chatgpt informed rapid and automated assertion generation,","venue":null,"work_id":"bea3515e-9010-4168-b87f-75a8ae809fe2","year":2024},"citing_paper":{"arxiv_id":"2506.13983","last_updated":"2025-06-11T06:43:24Z","snapshot_observed_at":"2026-08-19T23:33:05.092724Z","submitted_at":"2025-06-11T06:43:24Z","title":"SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine","version":1},"reference_index":2,"source":"pdf_text","source_observed_at":"2026-08-07T04:52:57.634754Z"},"links":{"citing_paper":"/paper/2506.13983"},"observation_digest":"sha256:27c0131f0873c3a5e9c7ef92d855770668a02d50b840856abf061e46b94b9746","observation_id":"b9071a4d-b049-42fe-b3eb-29ddeaf9d143","resolution":{"observed_at":"2026-08-07T04:52:58.038757Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-20T06:33:59.587034+00:00","source":"crossref"},{"observed_at":"2026-08-20T06:33:54.927442+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:52:57.642311Z","title":"Assertllm: Generating and evaluating hardware verification assertions from design specifications via multi-llms,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2506.13983","last_updated":"2025-06-11T06:43:24Z","snapshot_observed_at":"2026-08-19T23:33:05.092724Z","submitted_at":"2025-06-11T06:43:24Z","title":"SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine","version":1},"reference_index":4,"source":"pdf_text","source_observed_at":"2026-08-07T04:52:57.642311Z"},"links":{"citing_paper":"/paper/2506.13983"},"observation_digest":"sha256:f9a53148e26ef63e0ea51ba3b728a2937d4a0bf525f2adcf908cc95fb7d4e877","observation_id":"77577d9b-7591-4308-91fb-f3e3c930d38f","resolution":{"observed_at":"2026-08-07T04:52:57.642311Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:52:58.025022Z","title":"Global Large Language Model (LLM) Research Re- port 2024-2030,","venue":null,"work_id":"42fc7e58-1715-4def-968c-8784a69e3456","year":2024},"citing_paper":{"arxiv_id":"2506.13983","last_updated":"2025-06-11T06:43:24Z","snapshot_observed_at":"2026-08-19T23:33:05.092724Z","submitted_at":"2025-06-11T06:43:24Z","title":"SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine","version":1},"reference_index":5,"source":"pdf_text","source_observed_at":"2026-08-07T04:52:57.646554Z"},"links":{"citing_paper":"/paper/2506.13983"},"observation_digest":"sha256:ffa0c74e70650de8a5f6ed1f6d7598e5ae66e7e6ed40012b9df5f98f1d712cd4","observation_id":"6d078b8e-5c07-4baa-9042-a68f70ee2813","resolution":{"observed_at":"2026-08-07T04:52:58.028681Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-20T06:33:59.587034+00:00","source":"crossref"},{"observed_at":"2026-08-20T06:33:54.927442+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2408.06810","last_updated":"2024-08-13T10:59:30Z","snapshot_observed_at":"2026-08-18T09:27:58.211379Z","submitted_at":"2024-08-13T10:59:30Z","title":"HLSPilot: LLM-based High-Level Synthesis","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2408.06810","snapshot_observed_at":"2026-08-07T04:52:57.650143Z","title":"Hlspilot: Llm-based high-level synthesis,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2506.13983","last_updated":"2025-06-11T06:43:24Z","snapshot_observed_at":"2026-08-19T23:33:05.092724Z","submitted_at":"2025-06-11T06:43:24Z","title":"SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine","version":1},"reference_index":6,"source":"pdf_text","source_observed_at":"2026-08-07T04:52:57.650143Z"},"links":{"cited_paper":"/paper/2408.06810","citing_paper":"/paper/2506.13983"},"observation_digest":"sha256:5495e4fdcb895a9259385761ab35146baec2bc1a0c97ef05bfbb9037df7a15d4","observation_id":"54150c34-5968-4937-8c3e-1da2ca504a86","resolution":{"observed_at":"2026-08-07T04:52:57.650143Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:52:58.014109Z","title":"Lhs: Llm assisted efficient high-level synthesis of deep learning tasks,","venue":null,"work_id":"caf3c4f7-5b86-429c-99c8-1cfbac585c91","year":2025},"citing_paper":{"arxiv_id":"2506.13983","last_updated":"2025-06-11T06:43:24Z","snapshot_observed_at":"2026-08-19T23:33:05.092724Z","submitted_at":"2025-06-11T06:43:24Z","title":"SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine","version":1},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-08-07T04:52:57.654420Z"},"links":{"citing_paper":"/paper/2506.13983"},"observation_digest":"sha256:8a25c8c9b17f9f1b52e8a13119379470a00aae58d56f559afd016b605dcc0f28","observation_id":"59542042-1985-43dd-9604-ea3eec6a8ef5","resolution":{"observed_at":"2026-08-07T04:52:58.017929Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-20T06:33:59.587034+00:00","source":"crossref"},{"observed_at":"2026-08-20T06:33:54.927442+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:52:58.003500Z","title":"Large language model (llm) for standard cell layout design optimization,","venue":null,"work_id":"d4e666ff-7923-47c1-857e-421fecec5fab","year":2024},"citing_paper":{"arxiv_id":"2506.13983","last_updated":"2025-06-11T06:43:24Z","snapshot_observed_at":"2026-08-19T23:33:05.092724Z","submitted_at":"2025-06-11T06:43:24Z","title":"SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine","version":1},"reference_index":8,"source":"pdf_text","source_observed_at":"2026-08-07T04:52:57.657705Z"},"links":{"citing_paper":"/paper/2506.13983"},"observation_digest":"sha256:767a0e2626c65da7a43bd41711e6fac835369be6864b7e765f0e36c80a2cfe53","observation_id":"51162e04-6414-402a-84e9-1e7226e0f0f9","resolution":{"observed_at":"2026-08-07T04:52:58.007375Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-20T06:33:59.587034+00:00","source":"crossref"},{"observed_at":"2026-08-20T06:33:54.927442+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:52:57.992941Z","title":"Automatically improving llm-based verilog generation using eda tool feedback,","venue":null,"work_id":"ec0c27d5-e280-4d11-a4fa-47c98d6141ea","year":2025},"citing_paper":{"arxiv_id":"2506.13983","last_updated":"2025-06-11T06:43:24Z","snapshot_observed_at":"2026-08-19T23:33:05.092724Z","submitted_at":"2025-06-11T06:43:24Z","title":"SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine","version":1},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-08-07T04:52:57.661001Z"},"links":{"citing_paper":"/paper/2506.13983"},"observation_digest":"sha256:02c99d18cc6d6859403641542f3730d4cbf9e0dce65c3149483886d49e2a13cd","observation_id":"68271aab-22e7-469f-80ed-f362bd926c11","resolution":{"observed_at":"2026-08-07T04:52:57.996730Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-20T06:33:59.587034+00:00","source":"crossref"},{"observed_at":"2026-08-20T06:33:54.927442+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:52:57.982198Z","title":"Vhdl-eval: A framework for evaluating large language models in vhdl code generation,","venue":null,"work_id":"b6593306-1a63-4859-be99-fcac93568d1d","year":2024},"citing_paper":{"arxiv_id":"2506.13983","last_updated":"2025-06-11T06:43:24Z","snapshot_observed_at":"2026-08-19T23:33:05.092724Z","submitted_at":"2025-06-11T06:43:24Z","title":"SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine","version":1},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-08-07T04:52:57.663985Z"},"links":{"citing_paper":"/paper/2506.13983"},"observation_digest":"sha256:f2162c44aba46e2c44e723170a445cbdbf4051ddad2839b1e063d91d951feed4","observation_id":"4fa89efe-2162-4925-86ef-0c4dc7bd4f20","resolution":{"observed_at":"2026-08-07T04:52:57.985839Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-20T06:33:59.587034+00:00","source":"crossref"},{"observed_at":"2026-08-20T06:33:54.927442+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:52:57.971776Z","title":"Layoutcopilot: An llm-powered multi-agent collaborative framework for interactive analog layout design,","venue":null,"work_id":"e5ce6581-c0fe-4378-9705-8021e488f34e","year":2025},"citing_paper":{"arxiv_id":"2506.13983","last_updated":"2025-06-11T06:43:24Z","snapshot_observed_at":"2026-08-19T23:33:05.092724Z","submitted_at":"2025-06-11T06:43:24Z","title":"SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine","version":1},"reference_index":11,"source":"pdf_text","source_observed_at":"2026-08-07T04:52:57.667325Z"},"links":{"citing_paper":"/paper/2506.13983"},"observation_digest":"sha256:07d34ab11a24cafa4b42d42993d994a043100a43c74559cb37aa70af4bdc4ded","observation_id":"31c089ac-14d0-4cd9-b5f0-84b7a6b562e7","resolution":{"observed_at":"2026-08-07T04:52:57.975488Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-20T06:33:59.587034+00:00","source":"crossref"},{"observed_at":"2026-08-20T06:33:54.927442+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:52:57.961313Z","title":"Assertllm: Generating hardware verification assertions from design specifications via multi-llms,","venue":null,"work_id":"0a5289b4-9760-4768-a0dd-92ef7b13c123","year":2024},"citing_paper":{"arxiv_id":"2506.13983","last_updated":"2025-06-11T06:43:24Z","snapshot_observed_at":"2026-08-19T23:33:05.092724Z","submitted_at":"2025-06-11T06:43:24Z","title":"SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine","version":1},"reference_index":12,"source":"pdf_text","source_observed_at":"2026-08-07T04:52:57.670753Z"},"links":{"citing_paper":"/paper/2506.13983"},"observation_digest":"sha256:bb9a6f0d77cf0beb864409ad43ace4834272301594eefec19fb4f8bd8e47c74c","observation_id":"98236062-81e9-428b-88b9-e00c09568a03","resolution":{"observed_at":"2026-08-07T04:52:57.965034Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-20T06:33:59.587034+00:00","source":"crossref"},{"observed_at":"2026-08-20T06:33:54.927442+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:52:57.949741Z","title":"(security) assertions by large language models,","venue":null,"work_id":"eabe75ae-3bf9-41a7-acb6-291f50867b85","year":2024},"citing_paper":{"arxiv_id":"2506.13983","last_updated":"2025-06-11T06:43:24Z","snapshot_observed_at":"2026-08-19T23:33:05.092724Z","submitted_at":"2025-06-11T06:43:24Z","title":"SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine","version":1},"reference_index":13,"source":"pdf_text","source_observed_at":"2026-08-07T04:52:57.673845Z"},"links":{"citing_paper":"/paper/2506.13983"},"observation_digest":"sha256:2a3b306b61818ea23df94a1b0fccafdf4bc2b6cb63c9d512bb1e729e31661cee","observation_id":"51033cee-27e0-4886-853b-9053c48dd691","resolution":{"observed_at":"2026-08-07T04:52:57.954512Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-20T06:33:59.587034+00:00","source":"crossref"},{"observed_at":"2026-08-20T06:33:54.927442+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:52:57.677273Z","title":"A survey of monte carlo tree search methods,","venue":null,"work_id":null,"year":2012},"citing_paper":{"arxiv_id":"2506.13983","last_updated":"2025-06-11T06:43:24Z","snapshot_observed_at":"2026-08-19T23:33:05.092724Z","submitted_at":"2025-06-11T06:43:24Z","title":"SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine","version":1},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-08-07T04:52:57.677273Z"},"links":{"citing_paper":"/paper/2506.13983"},"observation_digest":"sha256:af3df6c27478befbe1e6ca8f9247bc9195f621e6081361e0f0bf63bfba9cb48a","observation_id":"05db9ea7-4a4f-445a-a1d8-d8b05f097bee","resolution":{"observed_at":"2026-08-07T04:52:57.677273Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2406.07394","last_updated":"2024-06-13T07:19:06Z","snapshot_observed_at":"2026-08-19T23:32:49.413897Z","submitted_at":"2024-06-11T16:01:07Z","title":"Accessing GPT-4 level Mathematical Olympiad Solutions via Monte Carlo Tree Self-refine with LLaMa-3 8B","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2406.07394","snapshot_observed_at":"2026-08-07T04:52:57.680654Z","title":"Accessing gpt-4 level mathematical olympiad solutions via monte carlo tree self-refine with llama-3 8b,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2506.13983","last_updated":"2025-06-11T06:43:24Z","snapshot_observed_at":"2026-08-19T23:33:05.092724Z","submitted_at":"2025-06-11T06:43:24Z","title":"SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine","version":1},"reference_index":15,"source":"pdf_text","source_observed_at":"2026-08-07T04:52:57.680654Z"},"links":{"cited_paper":"/paper/2406.07394","citing_paper":"/paper/2506.13983"},"observation_digest":"sha256:bece897335b88ace0e354794a7eec27cb0e7dbea4e9b154abc1f208d600c9e96","observation_id":"09eabde7-cfde-42d2-ae9c-2ad25a992f67","resolution":{"observed_at":"2026-08-07T04:52:57.680654Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2406.06592","last_updated":"2024-12-11T22:59:10Z","snapshot_observed_at":"2026-07-06T02:11:23.670680Z","submitted_at":"2024-06-05T19:25:40Z","title":"Improve Mathematical Reasoning in Language Models by Automated Process Supervision","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2406.06592","snapshot_observed_at":"2026-08-07T04:52:57.684133Z","title":"Improve mathematical reasoning in lan- guage models by automated process supervision,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2506.13983","last_updated":"2025-06-11T06:43:24Z","snapshot_observed_at":"2026-08-19T23:33:05.092724Z","submitted_at":"2025-06-11T06:43:24Z","title":"SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine","version":1},"reference_index":16,"source":"pdf_text","source_observed_at":"2026-08-07T04:52:57.684133Z"},"links":{"cited_paper":"/paper/2406.06592","citing_paper":"/paper/2506.13983"},"observation_digest":"sha256:493b2103c2daf247f30586fcad8b5672b9ea6f1bdf3db4c7430e65a04bcac52d","observation_id":"d74b9f8c-62b4-439c-a77b-d87c812b9306","resolution":{"observed_at":"2026-08-07T04:52:57.684133Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2410.01707","last_updated":"2024-12-25T13:32:54Z","snapshot_observed_at":"2026-08-16T13:13:17.454194Z","submitted_at":"2024-10-02T16:15:31Z","title":"Interpretable Contrastive Monte Carlo Tree Search Reasoning","version":3},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2410.01707","snapshot_observed_at":"2026-08-07T04:52:57.687795Z","title":"Interpretable contrastive monte carlo tree search reasoning,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2506.13983","last_updated":"2025-06-11T06:43:24Z","snapshot_observed_at":"2026-08-19T23:33:05.092724Z","submitted_at":"2025-06-11T06:43:24Z","title":"SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine","version":1},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-08-07T04:52:57.687795Z"},"links":{"cited_paper":"/paper/2410.01707","citing_paper":"/paper/2506.13983"},"observation_digest":"sha256:cd158f35daa2f657b5a6c6a17e40864a31ba0731cbe00d39253ce5d5ed715f46","observation_id":"4ae882a5-8e08-47e1-b47e-874f811024c9","resolution":{"observed_at":"2026-08-07T04:52:57.687795Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2412.16720","last_updated":"2026-04-30T02:46:40Z","snapshot_observed_at":"2026-08-19T11:46:55.171293Z","submitted_at":"2024-12-21T18:04:31Z","title":"OpenAI o1 System Card","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2412.16720","snapshot_observed_at":"2026-08-07T04:52:57.691583Z","title":"Deepseek-r1: Incentivizing reasoning capability in llms via reinforcement learning,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2506.13983","last_updated":"2025-06-11T06:43:24Z","snapshot_observed_at":"2026-08-19T23:33:05.092724Z","submitted_at":"2025-06-11T06:43:24Z","title":"SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine","version":1},"reference_index":18,"source":"pdf_text","source_observed_at":"2026-08-07T04:52:57.691583Z"},"links":{"cited_paper":"/paper/2412.16720","citing_paper":"/paper/2506.13983"},"observation_digest":"sha256:4ec2baddb457e7d2bd4a7e815564a2f0c7e54f1395b006cf232c6f6da8ee1689","observation_id":"87ef17b4-d171-4b0c-ab1a-20fed0e5b303","resolution":{"observed_at":"2026-08-07T04:52:57.691583Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:52:57.932884Z","title":"JasperGold,","venue":null,"work_id":"79d8f825-10c9-43ae-a3bd-82353635bdfe","year":2025},"citing_paper":{"arxiv_id":"2506.13983","last_updated":"2025-06-11T06:43:24Z","snapshot_observed_at":"2026-08-19T23:33:05.092724Z","submitted_at":"2025-06-11T06:43:24Z","title":"SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine","version":1},"reference_index":19,"source":"pdf_text","source_observed_at":"2026-08-07T04:52:57.695265Z"},"links":{"citing_paper":"/paper/2506.13983"},"observation_digest":"sha256:ff6e001600af3d54cd8f9cbc0a4d792d8b47e123a16a6b1717469204bc384299","observation_id":"32e1f071-e775-47e7-a347-42c0170c4e96","resolution":{"observed_at":"2026-08-07T04:52:57.936727Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-20T06:33:59.587034+00:00","source":"crossref"},{"observed_at":"2026-08-20T06:33:54.927442+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:52:57.920966Z","title":"Dasgupta,A Roadmap for Formal Property Verification","venue":null,"work_id":"fca2bc3e-5f94-45bf-bbfb-6a8c7eeccc4d","year":2006},"citing_paper":{"arxiv_id":"2506.13983","last_updated":"2025-06-11T06:43:24Z","snapshot_observed_at":"2026-08-19T23:33:05.092724Z","submitted_at":"2025-06-11T06:43:24Z","title":"SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine","version":1},"reference_index":20,"source":"pdf_text","source_observed_at":"2026-08-07T04:52:57.698673Z"},"links":{"citing_paper":"/paper/2506.13983"},"observation_digest":"sha256:85d0f769eef63942397e02ae51a442a73155975abad1a92a39d9a0cc9bc5858d","observation_id":"16945369-f932-42e5-aaf6-10a6debb436e","resolution":{"observed_at":"2026-08-07T04:52:57.925028Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-20T06:33:59.587034+00:00","source":"crossref"},{"observed_at":"2026-08-20T06:33:54.927442+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:52:57.908978Z","title":null,"venue":null,"work_id":"f81573a5-89f4-4b3a-a07e-225fcf796f80","year":2013},"citing_paper":{"arxiv_id":"2506.13983","last_updated":"2025-06-11T06:43:24Z","snapshot_observed_at":"2026-08-19T23:33:05.092724Z","submitted_at":"2025-06-11T06:43:24Z","title":"SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine","version":1},"reference_index":21,"source":"pdf_text","source_observed_at":"2026-08-07T04:52:57.702170Z"},"links":{"citing_paper":"/paper/2506.13983"},"observation_digest":"sha256:3f5d979ed9a1bb952e813217c442eb0b4ffb2c4b483fd4286cab272661c55c36","observation_id":"485d6166-81a4-4446-abdf-6cb2a4f6adc6","resolution":{"observed_at":"2026-08-07T04:52:57.912327Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-20T06:33:59.587034+00:00","source":"crossref"},{"observed_at":"2026-08-20T06:33:54.927442+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:52:57.897381Z","title":"Vijayaraghavan and M","venue":null,"work_id":"0966e6b8-c29d-4387-8429-701d6fd3ac4d","year":2005},"citing_paper":{"arxiv_id":"2506.13983","last_updated":"2025-06-11T06:43:24Z","snapshot_observed_at":"2026-08-19T23:33:05.092724Z","submitted_at":"2025-06-11T06:43:24Z","title":"SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine","version":1},"reference_index":22,"source":"pdf_text","source_observed_at":"2026-08-07T04:52:57.705532Z"},"links":{"citing_paper":"/paper/2506.13983"},"observation_digest":"sha256:9c140de5a9f7d8000640dde8ad0e4c3d4ffc235337b7cc587528d8a7936a3571","observation_id":"dacdfe94-c6e1-4a63-a6c3-e86403f75f63","resolution":{"observed_at":"2026-08-07T04:52:57.900865Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-20T06:33:59.587034+00:00","source":"crossref"},{"observed_at":"2026-08-20T06:33:54.927442+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:52:57.885505Z","title":"Assertllm dataset: Generating hardware ver- ification assertions from design specifications via multi-llms,","venue":null,"work_id":"69db7e2b-6460-48f7-9879-d2e220ccbf5d","year":2024},"citing_paper":{"arxiv_id":"2506.13983","last_updated":"2025-06-11T06:43:24Z","snapshot_observed_at":"2026-08-19T23:33:05.092724Z","submitted_at":"2025-06-11T06:43:24Z","title":"SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine","version":1},"reference_index":23,"source":"pdf_text","source_observed_at":"2026-08-07T04:52:57.709141Z"},"links":{"citing_paper":"/paper/2506.13983"},"observation_digest":"sha256:13153ebaa07d21d7dd0e7e4d59bf0e89b875a227ee96149b9d1ec4a4ba6d066e","observation_id":"4598133f-bb9e-4cca-81a6-0b06d84292ec","resolution":{"observed_at":"2026-08-07T04:52:57.889453Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-20T06:33:59.587034+00:00","source":"crossref"},{"observed_at":"2026-08-20T06:33:54.927442+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-07T04:52:57.872013Z","title":"• Be very strict, ensureCORRECTNESS,CONSISTENCY, andCOMPLETENESSof the SV As","venue":null,"work_id":"d4b536bd-ced4-4152-9baf-f9ccf4a55bfb","year":null},"citing_paper":{"arxiv_id":"2506.13983","last_updated":"2025-06-11T06:43:24Z","snapshot_observed_at":"2026-08-19T23:33:05.092724Z","submitted_at":"2025-06-11T06:43:24Z","title":"SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine","version":1},"reference_index":100,"source":"pdf_text","source_observed_at":"2026-08-07T04:52:57.712752Z"},"links":{"citing_paper":"/paper/2506.13983"},"observation_digest":"sha256:77439b079cc21dbfc2546d0f319a2c384a9e50a92177b55eb9b24d57844f1c7b","observation_id":"a05812bf-c086-4443-9b2e-1b74d73e3c92","resolution":{"observed_at":"2026-08-07T04:52:57.878173Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-20T06:33:59.587034+00:00","source":"crossref"},{"observed_at":"2026-08-20T06:33:54.927442+00:00","source":"retraction_watch"}],"state":"measured"}}],"paper":{"arxiv_id":"2506.13983","last_updated":"2025-06-11T06:43:24Z","latest_version":1,"primary_category":"cs.AI","snapshot_observed_at":"2026-08-19T23:33:05.092724Z","submitted_at":"2025-06-11T06:43:24Z","title":"SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine"},"reference_resolution":{"displayed":23,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":9,"verified_exact":0,"verified_fuzzy":14},"total_outbound_references":23},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-20T06:33:59.587034+00:00","source":"crossref"},{"observed_at":"2026-08-20T06:33:54.927442+00:00","source":"retraction_watch"}],"thesis":"As of 20 August 2026, this Paper Citation Record lists 23 of 23 outbound references and 1 inbound Pith citation observation for arXiv:2506.13983."}