{"as_of":"2026-08-14T20:19:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:735871deb5d436a55e5b3925f3f7a1786a493321b1265f5bd758ee27c1508aba","coverage":[{"denominator":300,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":100,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-05T15:29:59.294780Z","state":"measured"},{"denominator":100,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":100,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-14T06:32:32.682623+00:00","state":"measured"},{"denominator":0,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"cited_works","source_observed_at":null,"state":"measured"}],"external_citation_measurements":[],"inbound":[],"links":{"evidence":"/evidence","html":"/paper/2508.19868/citation-record","integrity":"/paper/2508.19868/integrity","json":"/paper/2508.19868/citation-record.json","paper":"/paper/2508.19868"},"outbound":[{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:58.963912Z","title":"Understanding and Improving the Latency of DRAM-Based Memory Systems,","venue":null,"work_id":null,"year":2017},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:58.963912Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:e69f311bcdd0a9901d17fdfc13b8f5cd336caaa0947ec4723e61077ee0bf78ce","observation_id":"c41ec0cf-8274-4def-b546-63426b5ecb5b","resolution":{"observed_at":"2026-08-05T15:29:58.963912Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:58.968046Z","title":"A Signed Binary mMultiplication Technique,","venue":null,"work_id":null,"year":1951},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":2,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:58.968046Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:7a60775096d5456cbb643ff4ac516ab47d5fe447857b5e3665d3903858b58718","observation_id":"32536225-8d8f-46f5-b487-24814daa3d65","resolution":{"observed_at":"2026-08-05T15:29:58.968046Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:58.972003Z","title":"Multiplication of Many-Digital Numbers by Automatic Computers,","venue":null,"work_id":null,"year":1962},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":3,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:58.972003Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:00cc6ecd88b4c002cf2e353f50e8960cda11876b40d8f0eb1dbb1721d212fcdc","observation_id":"76a73807-c8e2-481b-a5c8-6b6f46ceed24","resolution":{"observed_at":"2026-08-05T15:29:58.972003Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:58.975548Z","title":"Phoenix Rebirth: Scalable MapReduce on a Large-Scale Shared-Memory System,","venue":null,"work_id":null,"year":2009},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":4,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:58.975548Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:0e12e97296792bdf40e10bb4eb7cf43fb4c1de136473b30849975489626baec9","observation_id":"6e0f81d4-024c-4ea1-9fed-fdc164f2cadb","resolution":{"observed_at":"2026-08-05T15:29:58.975548Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:58.979687Z","title":"SPEC CPU2017 Benchmarks,","venue":null,"work_id":null,"year":null},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":5,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:58.979687Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:0c4af9fafc625f4986379a3a6afb30a282e7ac89cd7a398594b81940a877825b","observation_id":"3238a8a0-7e18-463f-bb3d-68b79738ea0e","resolution":{"observed_at":"2026-08-05T15:29:58.979687Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:58.983267Z","title":"Benchmarking a New Paradigm: Experimental Analysis and Characterization of a Real Processing-in-Memory System,","venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":6,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:58.983267Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:23af3f96508ed84fcbcd110c731554d4d365918b57c683219a8c1da0a9c1518e","observation_id":"7355716f-15ed-4dc4-acc5-22d955162a06","resolution":{"observed_at":"2026-08-05T15:29:58.983267Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:58.986600Z","title":"Memory Scaling: A Systems Architecture Perspective,","venue":null,"work_id":null,"year":2013},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:58.986600Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:9ccc93238f79ffbe20be1a50ce8f9b3cb3464e5725f0d2d1896449ad7904a9e5","observation_id":"ade6d82d-4a1a-4761-a082-27ad54d75451","resolution":{"observed_at":"2026-08-05T15:29:58.986600Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:58.989736Z","title":"Research Problems and Opportunities in Memory Systems,","venue":null,"work_id":null,"year":2014},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":8,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:58.989736Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:a650200cc4aa7146741f93260ca7dad47d59d57f576d76625593757bdae3bb35","observation_id":"207c3d7f-d988-487b-90ab-70fa60bf28dd","resolution":{"observed_at":"2026-08-05T15:29:58.989736Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:58.992773Z","title":"The Tail at Scale,","venue":null,"work_id":null,"year":2013},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:58.992773Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:4ebcbdffeef8bbfa70bd7c1fb4ddd3da380508dabf6ce685fbef280c467446b1","observation_id":"a120547e-962f-4ebb-9e35-dfe5b9c04f19","resolution":{"observed_at":"2026-08-05T15:29:58.992773Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:58.995848Z","title":"Profiling a Warehouse-Scale Computer,","venue":null,"work_id":null,"year":2015},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:58.995848Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:e61fa8feaed727dcaad798a24b585053ef07728dcadf25e04aaa8271c585f01c","observation_id":"f7846e13-378e-423f-ad80-c1fef9643539","resolution":{"observed_at":"2026-08-05T15:29:58.995848Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:58.998832Z","title":"Clearing the Clouds: A Study of Emerging Scale-Out Workloads on Modern Hardware,","venue":null,"work_id":null,"year":2012},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":11,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:58.998832Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:6aad7ed07d39ae35a3ee79928cd4339dc6d8982ed435ba14c03cde68ebc5198d","observation_id":"84190047-c879-4da3-8fbb-80fa3000165f","resolution":{"observed_at":"2026-08-05T15:29:58.998832Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.001913Z","title":"BigDataBench: A Big Data Bench- mark Suite from Internet Services,","venue":null,"work_id":null,"year":2014},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":12,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.001913Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:d45f026eafbde41bda253a47263750d4e8c7883b32a3e960d37a9a956836dc76","observation_id":"7129d64f-c813-4c38-b8e4-f4f06806a554","resolution":{"observed_at":"2026-08-05T15:29:59.001913Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.004901Z","title":"Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks,","venue":null,"work_id":null,"year":2018},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":13,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.004901Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:638b9e1fb414eeadc037798fd98cf58fd210b21597cfdd3e624f92d6b0ca089c","observation_id":"9064e286-3869-4c2f-b97b-90bc626948fa","resolution":{"observed_at":"2026-08-05T15:29:59.004901Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.007887Z","title":"Google Neural Network Models for Edge Devices: Analyzing and Mitigating Machine Learning Inference Bottlenecks,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.007887Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:f4189e380f8fe128c93dfeb6505f6cbc114d888d5a0be69f63452ff86b4fb82d","observation_id":"35fdca43-ea2e-401f-b423-8a524695a6fc","resolution":{"observed_at":"2026-08-05T15:29:59.007887Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2109.14320","last_updated":"2021-09-29T10:16:53Z","snapshot_observed_at":"2026-08-13T18:03:00.682959Z","submitted_at":"2021-09-29T10:16:53Z","title":"Google Neural Network Models for Edge Devices: Analyzing and Mitigating Machine Learning Inference Bottlenecks","version":1},"cited_work":{"arxiv_id":"2109.14320","doi":null,"metadata_source":"pith","pith_arxiv_id":"2109.14320","snapshot_observed_at":"2026-08-05T15:30:00.237414Z","title":"Google Neural Network Models for Edge Devices: Analyzing and Mitigating Machine Learning Inference Bottlenecks","venue":"cs.AR","work_id":"ccf8dc9f-7929-4e5b-bbd6-bcdb9d6ae9f5","year":2021},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":15,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.010918Z"},"links":{"cited_paper":"/paper/2109.14320","citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:9a9110597f65b29dab4890d2fb6508986c1bbacc7a766f2ddf184aa6890e1ee2","observation_id":"f23c1ddf-e495-4ada-a3fe-c2c33b645ebf","resolution":{"observed_at":"2026-08-05T15:30:00.242131Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-14T06:32:32.682623+00:00","source":"crossref"},{"observed_at":"2026-08-14T06:32:18.44784+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.014192Z","title":"En- abling Practical Processing in and Near Memory for Data-Intensive Computing,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":16,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.014192Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:9b2902457289c2277babb6496210ce04f4072ac0583cfafe38da270163230510","observation_id":"60876764-e267-4cd0-80de-76456ee72593","resolution":{"observed_at":"2026-08-05T15:29:59.014192Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.017459Z","title":"Pro- cessing Data Where It Makes Sense: Enabling In-Memory Computation,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.017459Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:6d18135e2e5526bb566883c860fa8ac98ef82731eee89a1b945c3e5af5b307db","observation_id":"7b0cf148-a05f-4370-80c4-0f1ba49a9dc4","resolution":{"observed_at":"2026-08-05T15:29:59.017459Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.020874Z","title":"Intelligent Architectures for Intelligent Machines,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":18,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.020874Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:a53bb94700e3310d99cc42e83c16bd5e6d2ad8eddabe818106ef7561ad31e213","observation_id":"04544bdf-fe71-406c-8679-b07e951aec76","resolution":{"observed_at":"2026-08-05T15:29:59.020874Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.023803Z","title":"Processing-in-Memory: A Workload-Driven Perspective,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":19,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.023803Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:04e2d4f06157efe4a607b312773db0f9c6623b5bdcfde6e69e5ad354b01567a4","observation_id":"7c49a28f-8017-4a2d-8b0e-12afb2bfeae6","resolution":{"observed_at":"2026-08-05T15:29:59.023803Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.027739Z","title":"Accelerating Genome Analysis: A Primer on an Ongoing Journey,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":20,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.027739Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:037b3fe42dd910cf554cc2c0dde16bed6aeb9cc270c0709e7486dc734bdc5a8a","observation_id":"77956a76-b1e4-4a42-ae0d-b2904ecf22f6","resolution":{"observed_at":"2026-08-05T15:29:59.027739Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.030709Z","title":"GenASM: A High-Performance, Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysis,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":21,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.030709Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:580ff6f98027c59aab65778e282a5e5467868d638b0f54a4e2a18e02ea6242c5","observation_id":"a7e70934-8116-40be-9ec4-390f470b63a4","resolution":{"observed_at":"2026-08-05T15:29:59.030709Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.033949Z","title":"EDEN: Enabling Energy-Efficient, High- Performance Deep Neural Network Inference Using Approximate DRAM,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":22,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.033949Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:eeaa49b332cf465b4f303cb96b470121285945736eeb22c92fa72863f237dfcf","observation_id":"4919a74e-f524-441f-bfea-bee32b0d8a6b","resolution":{"observed_at":"2026-08-05T15:29:59.033949Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.037148Z","title":"SMASH: Co-Designing Software Compression and Hardware- Accelerated Indexing for Efficient Sparse Matrix Operations,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":23,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.037148Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:138acee750f56d278615ac1ce74b6ac05f5ea1df8a9a47ed8c83418e55315172","observation_id":"9d93c2ec-201c-4cb7-b858-b012590834bb","resolution":{"observed_at":"2026-08-05T15:29:59.037148Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.040195Z","title":"DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":24,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.040195Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:5f77049496a6692fc3709d7cb78308ce34cd4466ac996d56d7de83a505dd1a1f","observation_id":"618b2ec4-f484-4f5e-9882-ba620f41deea","resolution":{"observed_at":"2026-08-05T15:29:59.040195Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2105.03725","last_updated":"2023-04-06T14:33:03Z","snapshot_observed_at":"2026-07-06T11:07:31.660804Z","submitted_at":"2021-05-08T16:02:53Z","title":"DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks","version":6},"cited_work":{"arxiv_id":"2105.03725","doi":null,"metadata_source":"pith","pith_arxiv_id":"2105.03725","snapshot_observed_at":"2026-08-05T15:30:00.222947Z","title":"DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks","venue":"cs.AR","work_id":"cec3ea81-abfb-4998-b491-71cf28aa0c4c","year":2021},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":25,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.043119Z"},"links":{"cited_paper":"/paper/2105.03725","citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:09e25a88b29830804898cb37359c4170c00560512e6bb33f4bf2ed5cba318a2a","observation_id":"efac6bb4-1468-4727-b5f2-e8047d6b4dca","resolution":{"observed_at":"2026-08-05T15:30:00.226663Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-14T06:32:32.682623+00:00","source":"crossref"},{"observed_at":"2026-08-14T06:32:18.44784+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.046358Z","title":"DAMOV: A New Methodology and Benchmark Suite for Evalu- ating Data Movement Bottlenecks,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":26,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.046358Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:90103cbced564b072f1ee891935b0bf55b1a5d0eea27c3c90622d60ee7e58ea4","observation_id":"8bf1c620-6e84-4b32-9f5e-ece8a0b3e63d","resolution":{"observed_at":"2026-08-05T15:29:59.046358Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.049239Z","title":"Processing Data Where It Makes Sense: Enabling In-Memory Computation,","venue":null,"work_id":null,"year":2017},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":27,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.049239Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:43f7332bf923ddd16222e4a4fa343c52099d9d90d1b973aa4a7c080fb09c0d87","observation_id":"abdacf17-11fc-4560-b267-3e6e3be3ee01","resolution":{"observed_at":"2026-08-05T15:29:59.049239Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.052493Z","title":"Processing Data Where It Makes Sense in Modern Computing Systems: Enabling In-Memory Computation,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":28,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.052493Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:4df6235b5997ae9dd700c479a895a62355a369d66a49636cadec318166311ce6","observation_id":"4aad9e52-f7b6-4edb-8c0e-0bf14d3b62e8","resolution":{"observed_at":"2026-08-05T15:29:59.052493Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.055852Z","title":"Processing Data Where It Makes Sense in Modern Computing Systems: Enabling In-Memory Computation,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":29,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.055852Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:2d6a113eeda12fb905af2d37495d5e5a52ac6f5f9acede23c34fa7c40854498c","observation_id":"008f1ab9-e391-43e3-94f2-c702e3cd37df","resolution":{"observed_at":"2026-08-05T15:29:59.055852Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.058846Z","title":"Processing Data Where It Makes Sense in Modern Computing Systems: Enabling In-Memory Computation,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":30,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.058846Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:13e082701513ea692d855a3ee8976393b1202db0304ddb6fbba7d0b295cde202","observation_id":"f1a1a9b7-d71a-4afb-91bf-3dec34ec09a7","resolution":{"observed_at":"2026-08-05T15:29:59.058846Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.062030Z","title":"Processing Data Where It Makes Sense in Modern Computing Systems: Enabling In-Memory Computation,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":31,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.062030Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:d21166142ee8ac7534a01ce0848f751b32133e177c322dc979961297c0e05850","observation_id":"3c80cfde-4715-4ff5-827b-602e448cf0fb","resolution":{"observed_at":"2026-08-05T15:29:59.062030Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.065357Z","title":"Processing Data Where It Makes Sense in Modern Computing Systems: Enabling In-Memory Computation,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":32,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.065357Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:2a2e54c96b436a4fe4aade98f5684e3d9dd9e549866a73fb3910e328d946706c","observation_id":"f44b4d68-e385-4242-a8cc-c06da60aebcb","resolution":{"observed_at":"2026-08-05T15:29:59.065357Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.068359Z","title":"Evaluating the Memory System Behavior of Smartphone Workloads,","venue":null,"work_id":null,"year":2014},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":33,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.068359Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:c46605471bb1077742421ef6cbd18be7217f002e2aa5358054d7a73f6e1a8515","observation_id":"b54ffbe5-49e8-4f5f-858e-9b576150c3c5","resolution":{"observed_at":"2026-08-05T15:29:59.068359Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.071322Z","title":"Memory Hierarchy for Web Search,","venue":null,"work_id":null,"year":2018},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":34,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.071322Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:745d683b1e5cb44080965d28753ba926c28950894f5691045ff282039b39a1f2","observation_id":"5987596f-7ef2-4244-b698-435f28365309","resolution":{"observed_at":"2026-08-05T15:29:59.071322Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.074579Z","title":"Understanding Big Data Analytics Workloads on Modern Processors,","venue":null,"work_id":null,"year":2016},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":35,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.074579Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:efbfb1d16b65027e8fee58f1f7a18e7a927ccabe9996701504b95427ce5eec68","observation_id":"a93bf4e3-7742-4257-887a-fdb35ccea581","resolution":{"observed_at":"2026-08-05T15:29:59.074579Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.077728Z","title":"Optimizing database architecture for the new bottleneck: Memory access,","venue":null,"work_id":null,"year":2000},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":36,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.077728Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:7d7601cc16cbb00e1ee577b0d328308085e63d4c28a30f238b70a4a5f85cec67","observation_id":"5011f3f0-4f93-492d-bfb4-4f3224f94a5d","resolution":{"observed_at":"2026-08-05T15:29:59.077728Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.080901Z","title":"AI and Memory Wall,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":37,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.080901Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:5cae89d8fedb7972ecb3dadec276a404623e591054d9c785533d061cba7191a5","observation_id":"16362fad-e3ff-4a58-802e-7f0b8512e13c","resolution":{"observed_at":"2026-08-05T15:29:59.080901Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.084279Z","title":"Quantifying Per- formance Bottlenecks of Stencil Computations Using the Execution-Cache-Memory Model,","venue":null,"work_id":null,"year":2015},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":38,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.084279Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:c5bc2e0f852c7da9d987bd7978ddea7ce152298e8d9d0bf2098a8d8df73cdd77","observation_id":"6ad9c0c1-d106-43cd-80d7-830d924543ee","resolution":{"observed_at":"2026-08-05T15:29:59.084279Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.087215Z","title":"Memory System Characterization of Deep Learning Workloads,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":39,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.087215Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:bac29a589f47bd5a782f83704bf4ede5954d3f97b23b530b53b9a06f99e9deaa","observation_id":"81135c82-dcf2-4092-870e-5f7eb1d97a8f","resolution":{"observed_at":"2026-08-05T15:29:59.087215Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.095360Z","title":"The Declining Effectiveness of Dynamic Caching for General-Purpose Microprocessors,","venue":null,"work_id":null,"year":1995},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":40,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.095360Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:9c220d47606854cdd87f5000541baeae5fbed0f96eb937647ad54b195d7ee8f9","observation_id":"6f43e637-047b-480c-a3cf-02dc9a104c40","resolution":{"observed_at":"2026-08-05T15:29:59.095360Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.098637Z","title":"The Ar- chitectural Implications of Facebook’s DNN-based Personalized Recommendation,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":41,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.098637Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:eb9b50185f410e897b489b77437082fd952681563e936b613ef4ea55c248ef4e","observation_id":"24ed4f5e-e7a4-4edc-9301-840f4726c65e","resolution":{"observed_at":"2026-08-05T15:29:59.098637Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.101817Z","title":"SoftSKU: Optimizing Server Architectures for Microservice Diversity @Scale,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":42,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.101817Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:c50bdf30c21f4a2ed5eb81599cb066c29be65de9a746a27d49c56f8a90eb6d47","observation_id":"6b757561-d62e-4bdb-8b9e-55944b7c0628","resolution":{"observed_at":"2026-08-05T15:29:59.101817Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.104941Z","title":"Understanding Data Storage and Ingestion for Large-Scale Deep Recommendation Model Training: Indus- trial Product,","venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":43,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.104941Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:3331872b41d50560143a59ba50c1c936080ce21e32e8985b044c1c53ad895298","observation_id":"4c851807-8b8f-4de9-93cc-5e4672d45165","resolution":{"observed_at":"2026-08-05T15:29:59.104941Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.108334Z","title":"{INSIDER}: Designing{In-Storage} Com- puting System for Emerging{High-Performance} Drive,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":44,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.108334Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:26b4a6e7a55808bd84382ea595c6e269f7ff5613623a3c1d3cd8869b32f5e755","observation_id":"0346ed8c-dbd7-4de6-8585-97cb7c00865b","resolution":{"observed_at":"2026-08-05T15:29:59.108334Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.111391Z","title":"The Architectural Implications of Cloud Microser- vices,","venue":null,"work_id":null,"year":2018},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":45,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.111391Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:ccde79968784b22c7c08909833b3c4bc18d5425af49e78f1ee01798edc93ea29","observation_id":"c1f4ed8a-ad3e-401b-80c9-c46b90c18776","resolution":{"observed_at":"2026-08-05T15:29:59.111391Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.114430Z","title":"Accelerometer: Understanding Accelera- tion Opportunities for Data Center Overheads at Hyperscale,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":46,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.114430Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:b51b03d39e751f6f21aecb41ad5c39bfebbefd3eb58663167a6ce84088fefeeb","observation_id":"7fd3a6c6-fdce-42ea-9afa-07df9da53676","resolution":{"observed_at":"2026-08-05T15:29:59.114430Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.117512Z","title":"RAMBDA: RDMA-Driven Acceleration Framework for Memory-Intensive 𝜇s-Scale Datacenter Applications,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":47,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.117512Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:b6aaa43553c875404374030d607d09f2fd4cb0115b44f278e03c627fb42454d0","observation_id":"fcc40678-3f5f-4cc5-8f6e-a691ffd3601a","resolution":{"observed_at":"2026-08-05T15:29:59.117512Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.120999Z","title":"Amdahl’s Law for Tail Latency,","venue":null,"work_id":null,"year":2018},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":48,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.120999Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:2c41eaf3b06da16c0dccd8a21a83aa7de2ffb44dc90839068eb13e3e144222cb","observation_id":"f57e3857-26a4-4a44-ac8a-6e0a89b88dd2","resolution":{"observed_at":"2026-08-05T15:29:59.120999Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.123947Z","title":"Cross-Stack Workload Characterization of Deep Recommendation Systems,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":49,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.123947Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:2c290dec3bcd4c390697185b92422a3fd7bddc91e283b0c6ae1a4d602a378063","observation_id":"92406ea7-d233-41de-b64e-5c475f4d6114","resolution":{"observed_at":"2026-08-05T15:29:59.123947Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.127032Z","title":"vbench: Benchmarking Video Transcoding in the Cloud,","venue":null,"work_id":null,"year":2018},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":50,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.127032Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:919fd1795b65e2735b88454879e1f8f0d4320de29069d4aa6bcd8c2579242f5c","observation_id":"9f9e22c3-d5e1-4d49-9751-a64d1b039fc6","resolution":{"observed_at":"2026-08-05T15:29:59.127032Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.130278Z","title":"Characterizing Job Microarchitectural Profiles at Scale: Dataset and Analysis,","venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":51,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.130278Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:2b5720e7230f76bfa495daa8d4bb0d73d94af37204b3ed8f6bbed70263783842","observation_id":"21ce411f-bde7-4750-93ef-b9d2d84874cb","resolution":{"observed_at":"2026-08-05T15:29:59.130278Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.134246Z","title":"Missing the Forest for the Trees: End-to-End AI Application Performance in Edge Data Centers,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":52,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.134246Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:a83b66331c18f9fafdf92d600e22261f6f258794e4dfaad68b5ea9344dd7f764","observation_id":"caa6e74a-0de2-4870-b610-c1a612cd7284","resolution":{"observed_at":"2026-08-05T15:29:59.134246Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.137440Z","title":"Reflections on the Memory Wall,","venue":null,"work_id":null,"year":2004},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":53,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.137440Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:f4c81f4234d2848bead509cab342b68916e77a83e0b19391efcd690a0478b5c6","observation_id":"6115434a-e262-47a5-9737-5dda577ee32c","resolution":{"observed_at":"2026-08-05T15:29:59.137440Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.140708Z","title":"Accelerating Depen- dent Cache Misses with an Enhanced Memory Controller,","venue":null,"work_id":null,"year":2016},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":54,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.140708Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:9eeb8ee12dc1c05471454c64f1acc977bc618998e22d138a4e62cced5c079cb9","observation_id":"113c3c38-7aca-4305-a26b-18200e415abf","resolution":{"observed_at":"2026-08-05T15:29:59.140708Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.143862Z","title":"Continuous Runahead: Transparent Hardware Acceleration for Memory Intensive Workloads,","venue":null,"work_id":null,"year":2016},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":55,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.143862Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:138665d01c45ec735c9c1035e576c1fea8fe4689a997649bfcae208c4e1db9ab","observation_id":"db748a2b-6431-4415-b330-07e4e180b131","resolution":{"observed_at":"2026-08-05T15:29:59.143862Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.147541Z","title":"A Scal- able Processing-in-Memory Accelerator for Parallel Graph Processing,","venue":null,"work_id":null,"year":2015},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":56,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.147541Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:3dd05e03134e4e16547c972c12877b65d26063e845b40f48406a1a244560bee3","observation_id":"2b46a74c-ba6a-494b-b1a3-a95d777e1204","resolution":{"observed_at":"2026-08-05T15:29:59.147541Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.150662Z","title":"PIM-Enabled Instruc- tions: A Low-Overhead, Locality-Aware Processing-in-Memory Architecture,","venue":null,"work_id":null,"year":2015},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":57,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.150662Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:c8cdfb9fda032c13ee059903fee32a8640b50237b735332c4f9d63534a7a80fb","observation_id":"f7a9d49d-5c94-4252-9bd4-08965599d71c","resolution":{"observed_at":"2026-08-05T15:29:59.150662Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.153947Z","title":"GPUs and the Future of Parallel Computing,","venue":null,"work_id":null,"year":2011},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":58,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.153947Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:ca894b64245b57235c6149b8da551b2811d10c2a720cd040402ad2ef5c472cf6","observation_id":"4901d8d9-4dc1-484d-b31c-da19f738b6b1","resolution":{"observed_at":"2026-08-05T15:29:59.153947Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.157746Z","title":"Slave Memories and Dynamic Storage Allocation,","venue":null,"work_id":null,"year":1965},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":59,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.157746Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:05cbd11929aa632b2ab72676025cf6247e0731fa303754a024cbcb055cd86280","observation_id":"b282ed5f-6041-4f0e-9b51-29dd335c8d8a","resolution":{"observed_at":"2026-08-05T15:29:59.157746Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.161127Z","title":null,"venue":null,"work_id":null,"year":1990},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":60,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.161127Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:87c1702c93651c1c2884908cbb33a337e4d33fdbfaa1721e6c46ce726bd830c9","observation_id":"c37e15d8-1fc8-4c25-aac7-448019dc2e90","resolution":{"observed_at":"2026-08-05T15:29:59.161127Z","resolver_source":null,"status":"parse_uncertain"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.164173Z","title":"A Case for Direct-Mapped Caches,","venue":null,"work_id":null,"year":1988},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":61,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.164173Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:f17c028ee443e22bd17ded2de9d8ab57f7d0ec8c619ad082ab32963d0c81c416","observation_id":"cbc97843-7eae-4b1f-a435-43afe61d2a84","resolution":{"observed_at":"2026-08-05T15:29:59.164173Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.168076Z","title":"High-Bandwidth Data Memory Systems for Su- perscalar Processors,","venue":null,"work_id":null,"year":1991},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":62,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.168076Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:a99536158ace51c2a32cddbfc437379b589b5a57d2ca18360c6024a5ab6eb32c","observation_id":"d00038a1-3ece-415e-9264-ebb3ebb33880","resolution":{"observed_at":"2026-08-05T15:29:59.168076Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.171234Z","title":"The Microarchitecture of the Intel Pentium 4 Processor on 90nm Technology,","venue":null,"work_id":null,"year":2004},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":63,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.171234Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:4cc133bed223e6e38bef2157c5953ac40432d5b49fd32d049bd9251b6c6978fd","observation_id":"c121ca5e-5fb9-45bb-8fb1-6325cc92b476","resolution":{"observed_at":"2026-08-05T15:29:59.171234Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.174284Z","title":"Tuning the Pentium Pro Microarchitecture,","venue":null,"work_id":null,"year":1996},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":64,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.174284Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:1cb70155e0b27cc1cb9a59ff9e9b970031353a73da4a74312eeaf1f2682a6b22","observation_id":"f9c1e345-e53a-4522-b67d-73794bd04157","resolution":{"observed_at":"2026-08-05T15:29:59.174284Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.177515Z","title":"POWER7: IBM’s Next-Generation Server Processor,","venue":null,"work_id":null,"year":2010},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":65,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.177515Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:75f71e2c26aac345d02f16734ead83e3dede45e9272ae7fa6404ad2e4f413d2f","observation_id":"e0091359-6dc3-4646-9559-23d88cab83fa","resolution":{"observed_at":"2026-08-05T15:29:59.177515Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.180540Z","title":"IBM POWER7 Multicore Server Processor,","venue":null,"work_id":null,"year":2011},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":66,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.180540Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:193724b11605b21297319e00d62351ed1d9e93881ccb3757e7adff582475ba3d","observation_id":"24226d9b-3111-42d9-b231-777461f59433","resolution":{"observed_at":"2026-08-05T15:29:59.180540Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.183904Z","title":"IBM POWER8 Processor Core Microarchitecture,","venue":null,"work_id":null,"year":2015},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":67,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.183904Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:cef6a793e26dd108949c24274583d1bf2893d6778443f99fb2eede892e9bcb17","observation_id":"0f7a9d27-22cf-4d4b-b2a6-045dad70d4ad","resolution":{"observed_at":"2026-08-05T15:29:59.183904Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.187232Z","title":"Developing the AMD-K5 Architecture,","venue":null,"work_id":null,"year":1996},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":68,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.187232Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:da4c1570a68f2857152d4de7fe8aa9c9f9a1ab4e1d6a97457d731a567e5078bb","observation_id":"99e91428-ccec-48cb-82c9-29dffe4faea8","resolution":{"observed_at":"2026-08-05T15:29:59.187232Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.190278Z","title":"Content-Sensitive Data Prefetching,","venue":null,"work_id":null,"year":2002},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":69,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.190278Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:4139c8f65ec7ab149abded7f6fccc0bddf5f2be15f1580e674502f2ff872cf95","observation_id":"f3d1f51c-0681-4988-a231-e56f92c6164a","resolution":{"observed_at":"2026-08-05T15:29:59.190278Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.193492Z","title":"A Hardware-Based Cache Pollution Filtering Mechanism for Aggressive Prefetches,","venue":null,"work_id":null,"year":2003},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":70,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.193492Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:c0d9363376ba743704aa0af8bff9ce6606a8d5bcd58f5ce4aa756b6b573a4a31","observation_id":"352afa88-2f4b-413f-8ff9-746d4e1684bb","resolution":{"observed_at":"2026-08-05T15:29:59.193492Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.197185Z","title":"Effective Stream-Based and Execution-Based Data Prefetching,","venue":null,"work_id":null,"year":2004},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":71,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.197185Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:c5df64e888fc5ff7ce01f534c9687b4e3a81972becaf803bd402a253b9d16041","observation_id":"6891adfa-d6a8-460d-9bd0-f5db7bb771bf","resolution":{"observed_at":"2026-08-05T15:29:59.197185Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.201020Z","title":"AC/DC: An Adaptive Data Cache Prefetcher,","venue":null,"work_id":null,"year":2004},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":72,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.201020Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:fd39f6bd6dbd050aeef86dc11a71a4b63798576764ec9de9c1e22dd219ccf37b","observation_id":"f542ee19-44f9-45ff-8a1a-05236891dc96","resolution":{"observed_at":"2026-08-05T15:29:59.201020Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.204792Z","title":"Memory Prefetching Using Adaptive Stream Detection,","venue":null,"work_id":null,"year":2006},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":73,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.204792Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:239fe44c29ed144001634f445574042e807cc2ce0b58576ec761efbf3aad9d64","observation_id":"2e754ac4-3088-4c80-aac3-e77753961aa8","resolution":{"observed_at":"2026-08-05T15:29:59.204792Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.207897Z","title":"Pythia: A Customizable Hardware Prefetching Framework using Online Reinforcement Learning,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":74,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.207897Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:a938536586d536ed3a763ec1913f3ac415faf58c40ceb2a22c7a1e5fb4727c13","observation_id":"d197c86a-5945-41cb-a7f3-2bcd55e17dc4","resolution":{"observed_at":"2026-08-05T15:29:59.207897Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.211111Z","title":"Access Map Pattern Matching for Data Cache Prefetch,","venue":null,"work_id":null,"year":2009},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":75,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.211111Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:872046fc5db76e45f396fc117902c7046f286a06827cd09566dacea88c99586b","observation_id":"1964c81e-b20a-49c3-a181-62543f26a030","resolution":{"observed_at":"2026-08-05T15:29:59.211111Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.214492Z","title":"Stride Directed Prefetching in Scalar Processors,","venue":null,"work_id":null,"year":1992},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":76,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.214492Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:7a3fd01f9b41db85d86d4c4a5803d21823265ce61530af721ded47f393ed47db","observation_id":"f03f87f3-98e8-46fe-af73-261c0a3313e4","resolution":{"observed_at":"2026-08-05T15:29:59.214492Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.217837Z","title":"Effective Hardware-Based Data Prefetching for High-Performance Processors,","venue":null,"work_id":null,"year":1995},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":77,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.217837Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:86705e343774bc29449953ad75719ea417397337ba9dac19d31a4c11d4a21d8c","observation_id":"2afd11d2-4ff2-4180-905a-1f2c24159c1f","resolution":{"observed_at":"2026-08-05T15:29:59.217837Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.220935Z","title":"Domino Temporal Data Prefetcher,","venue":null,"work_id":null,"year":2018},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":78,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.220935Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:b8e7c66353754b07c679076f5768adfd0f7a4acbe920f783b7d64c1bdc277514","observation_id":"64da2296-5d3c-4610-b6a6-09ce9d0492ce","resolution":{"observed_at":"2026-08-05T15:29:59.220935Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.224481Z","title":"DSPatch: Dual Spatial Pattern Prefetcher,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":79,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.224481Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:db45d082951972a313bd8174e7fcdbc9978a3adb570f6aba28cc02f49a7df1ab","observation_id":"145cfdcb-8e89-4df7-913d-92d5993ad994","resolution":{"observed_at":"2026-08-05T15:29:59.224481Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.227967Z","title":"Speculative Execution via Address Prediction and Data Prefetching,","venue":null,"work_id":null,"year":1997},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":80,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.227967Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:882d4ab6d04d4036c02cddeae457aa217ada0dfdc7aaa0e8313c08f37ffdd9fb","observation_id":"29a98539-023a-42c5-9f31-c4903d25b3ec","resolution":{"observed_at":"2026-08-05T15:29:59.227967Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.231157Z","title":"Coordinated Control of Multiple Prefetchers in Multi-Core Systems,","venue":null,"work_id":null,"year":2009},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":81,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.231157Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:d33f49b97e5277634fa48eea2b44fa7eeac5359c9f01becb3e2df860dcc7b6d1","observation_id":"b17184f2-cda1-4b48-a50c-299124bd4c3b","resolution":{"observed_at":"2026-08-05T15:29:59.231157Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.234158Z","title":"A Study of Integrated Prefetch- ing and Caching Strategies,","venue":null,"work_id":null,"year":1995},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":82,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.234158Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:cc4075559109cad89a347000374baaa913d819c51f77c18a9b740c9f16ffef75","observation_id":"594b5731-86b3-4d74-a1c0-17d4ff9f5d2f","resolution":{"observed_at":"2026-08-05T15:29:59.234158Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.237475Z","title":"Generalized Correlation-Based Hardware Prefetching,","venue":null,"work_id":null,"year":1995},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":83,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.237475Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:ae19a34e86fa9a873b487e257ad215efa341cb5b4fdffe90524b28ff686aabac","observation_id":"fddd0bd5-2288-4b57-b58d-665330ba61b6","resolution":{"observed_at":"2026-08-05T15:29:59.237475Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.240841Z","title":"Effective Jump-Pointer Prefetching for Linked Data Structures,","venue":null,"work_id":null,"year":1999},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":84,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.240841Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:3aa8d46d5688267158106a47f72eb911cf70fde9fee70f4350f30ff5b227e542","observation_id":"d3f8e512-5f34-4ece-97bc-5bfa16f8a00c","resolution":{"observed_at":"2026-08-05T15:29:59.240841Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.243971Z","title":"Data Prefetching by Dependence Graph Precomputation,","venue":null,"work_id":null,"year":2001},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":85,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.243971Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:f8c46b94081f558622d313ccf6ca817e44302b40c7fc515ce57936a17cfae9d0","observation_id":"d45a98ed-3a5d-4334-a489-50aa0afed889","resolution":{"observed_at":"2026-08-05T15:29:59.243971Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.247576Z","title":"Graph Prefetching Using Data Structure Knowledge,","venue":null,"work_id":null,"year":2016},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":86,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.247576Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:9b232ce4ef14405324bc3972ad923fe2151ee61d33358a26c85b09d2ab0a4013","observation_id":"9f8bfa1e-ae72-4b3c-a154-5df4166c227a","resolution":{"observed_at":"2026-08-05T15:29:59.247576Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.250726Z","title":"Gretch: A Hardware Prefetcher for Graph Analytics,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":87,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.250726Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:e3012f7e65dddcf809c0bd3481e1a5a3da5676ee3d954010efdb81888fa97719","observation_id":"9489716e-7f31-4088-a0b9-7be95a0e19cc","resolution":{"observed_at":"2026-08-05T15:29:59.250726Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.254055Z","title":"PrefEdge: SSD Prefetcher for Large-Scale Graph Traversal,","venue":null,"work_id":null,"year":2014},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":88,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.254055Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:4fb1f14d0424be3d7b2cc510e87ae2d0aa243cffb798bfe16d644febe0d1a705","observation_id":"6858e350-a61f-4ed3-b2c1-15be4deabe8f","resolution":{"observed_at":"2026-08-05T15:29:59.254055Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.257516Z","title":"Correlation-Based Hardware Prefetching,","venue":null,"work_id":null,"year":1995},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":89,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.257516Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:95d9fe35375e733d5af6e3ad5b39cd31a528ddafb23cb2e92afdf42d5123df2f","observation_id":"70726310-9eb7-496e-bcce-9e932a847c31","resolution":{"observed_at":"2026-08-05T15:29:59.257516Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.260557Z","title":"A Stateless, Content-Directed Data Prefetching Mechanism,","venue":null,"work_id":null,"year":2002},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":90,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.260557Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:7165481efa71bfb07619d390d1abfae3446d6b1e9ec63d9741038ccfa6ccaeb8","observation_id":"538c5793-c785-4406-b568-d407fa79f6fe","resolution":{"observed_at":"2026-08-05T15:29:59.260557Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.263620Z","title":"Prefetching Using Markov Predictors,","venue":null,"work_id":null,"year":1997},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":91,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.263620Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:3756fc9f71c3831b562db10a5e58889c80c76b5badb66ae81f10a0144abfdd13","observation_id":"0472d199-2363-4457-bfb3-a1339cb253ed","resolution":{"observed_at":"2026-08-05T15:29:59.263620Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.267205Z","title":"Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers,","venue":null,"work_id":null,"year":2007},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":92,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.267205Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:db708f7b7a2b01581f9c7882bcf052ab7c8e6bc3ec62f41d13900b0be1657767","observation_id":"1582022c-807e-4bf7-bd15-a15121f59220","resolution":{"observed_at":"2026-08-05T15:29:59.267205Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.270748Z","title":"Techniques for Bandwidth-Efficient Prefetching of Linked Data Structures in Hybrid Prefetching Systems,","venue":null,"work_id":null,"year":2009},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":93,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.270748Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:85613eb4018ea9d1553fc3f9e5aba94327b6b331a13e0e600588035e750c8987","observation_id":"e28030b7-1b27-40ef-8ab3-8bd1180b780e","resolution":{"observed_at":"2026-08-05T15:29:59.270748Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.273992Z","title":"Speculative Precomputation: Long-Range Prefetching of Delinquent Loads,","venue":null,"work_id":null,"year":2001},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":94,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.273992Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:d8dcffa7cb3127af7bc4ac92e89f48940e6299534a42d44c0b4eadf33ab97c8f","observation_id":"d3fc38b2-90b3-4580-82ae-02b0665866e1","resolution":{"observed_at":"2026-08-05T15:29:59.273992Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.277870Z","title":"LTRF: Enabling High-Capacity Register Files for GPUs via Hardware/Software Cooperative Register Prefetching,","venue":null,"work_id":null,"year":2018},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":95,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.277870Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:31ebb8db6fd6623db694832cf598cce2f88b21ee63b378198c4a4b5f528c7247","observation_id":"0db0d2a0-38a2-44dc-bcc5-f236d4b54787","resolution":{"observed_at":"2026-08-05T15:29:59.277870Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.280905Z","title":"Dependence Based Prefetching for Linked Data Structures,","venue":null,"work_id":null,"year":1998},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":96,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.280905Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:0943e14c35d7aa83025461cf12643e3878a4618ff0fbaf6146e35b6aa1ec5827","observation_id":"d6f70716-1cba-41a2-989b-8f088f1decc9","resolution":{"observed_at":"2026-08-05T15:29:59.280905Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.283981Z","title":"SPAID: Software Prefetching in Pointer- and Call-Intensive Environments,","venue":null,"work_id":null,"year":1995},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":97,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.283981Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:2f73900538c37db9ff1221428e7c3fae50ee02598e4a9c6e0949ed25f780f325","observation_id":"68deafce-d6a4-42a7-9b29-64c4dc7e5043","resolution":{"observed_at":"2026-08-05T15:29:59.283981Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.287780Z","title":"A Prefetching Technique for Irregular Accesses to Linked Data Structures,","venue":null,"work_id":null,"year":2000},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":98,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.287780Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:629493a3bb98e8ee651029a980899ccd2c59f074203c25e8331577463028c191","observation_id":"9ec7fcdd-5214-41a6-ba33-e123aed4ade7","resolution":{"observed_at":"2026-08-05T15:29:59.287780Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.290940Z","title":"Pointer Cache Assisted Prefetching,","venue":null,"work_id":null,"year":2002},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":99,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.290940Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:f532b4cd27757ed88794064a68cbe1bf72b8ce6e087e09dbc0741928e45d7648","observation_id":"8ed7d639-613f-430d-b904-f936944c3932","resolution":{"observed_at":"2026-08-05T15:29:59.290940Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:29:59.294780Z","title":"TCP: Tag Correlating Prefetchers,","venue":null,"work_id":null,"year":2003},"citing_paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures","version":1},"reference_index":100,"source":"pdf_text","source_observed_at":"2026-08-05T15:29:59.294780Z"},"links":{"citing_paper":"/paper/2508.19868"},"observation_digest":"sha256:c50fedfdf67f8728fc79c2bd7e0306559acda2a87635fedb2df6bbdeb3b2b362","observation_id":"24f40ce0-df6d-4101-8df4-a033b9cc9949","resolution":{"observed_at":"2026-08-05T15:29:59.294780Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}}],"paper":{"arxiv_id":"2508.19868","last_updated":"2025-08-27T13:30:54Z","latest_version":1,"primary_category":"cs.AR","snapshot_observed_at":"2026-08-13T18:00:51.267223Z","submitted_at":"2025-08-27T13:30:54Z","title":"New Tools, Programming Models, and System Support for Processing-in-Memory Architectures"},"reference_resolution":{"displayed":100,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":1,"unresolved":97,"verified_exact":2,"verified_fuzzy":0},"total_outbound_references":300},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-14T06:32:32.682623+00:00","source":"crossref"},{"observed_at":"2026-08-14T06:32:18.44784+00:00","source":"retraction_watch"}],"thesis":"As of 14 August 2026, this Paper Citation Record lists 100 of 300 outbound references and 0 inbound Pith citation observations for arXiv:2508.19868."}