{"as_of":"2026-08-16T16:32:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:781165f369fbe5910d02931d79a45c1a906c1b3d019d5ca3c8daa94b82b0b3be","coverage":[{"denominator":50,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":50,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-05T05:50:29.947770Z","state":"measured"},{"denominator":51,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":51,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-16T06:30:59.297886+00:00","state":"measured"},{"denominator":1,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":1,"source":"paper_references, paper_reference_links","source_observed_at":"2026-05-21T06:51:24.566343Z","state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"arxiv_reference","source_observed_at":"2026-05-21T06:54:01.144171Z","state":"measured"}],"external_citation_measurements":[],"inbound":[{"citation":{"cited_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"cited_work":{"arxiv_id":"2509.04905","doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":"2509.04905","snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","venue":null,"work_id":"5aa39762-65ef-4ac6-b7d9-40bf389f525f","year":2025},"citing_paper":{"arxiv_id":"2605.20456","last_updated":"2026-05-19T20:10:13Z","snapshot_observed_at":"2026-08-12T15:15:54.345070Z","submitted_at":"2026-05-19T20:10:13Z","title":"Agentic Agile-V: From Vibe Coding to Verified Engineering in Software and Hardware Development","version":1},"reference_index":34,"source":"pdf_text","source_observed_at":"2026-05-21T06:51:24.566343Z"},"links":{"cited_paper":"/paper/2509.04905","citing_paper":"/paper/2605.20456"},"observation_digest":"sha256:58f44918f50bd533e638654a99f5b496ed851c516b06a67b82d71ef7dfbe45f2","observation_id":"9fbda0b2-cd40-44c6-9c73-e11200c60634","resolution":{"observed_at":"2026-05-21T06:54:01.145807Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}}],"links":{"evidence":"/evidence","html":"/paper/2509.04905/citation-record","integrity":"/paper/2509.04905/integrity","json":"/paper/2509.04905/citation-record.json","paper":"/paper/2509.04905"},"outbound":[{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:30.750281Z","title":"Global semiconductor sales in- crease 19.1% in 2024; double-digit growth projected in 2025,","venue":null,"work_id":"cdcfd125-1938-4dc8-bf78-dffddda26fa6","year":2024},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.337750Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:c1a897e25c5fedf5f012f95514fe775cb29cbf3ec6e09b3cfa1d72678ef5b09b","observation_id":"7fd77270-fab5-48aa-8dbc-006449bf2dff","resolution":{"observed_at":"2026-08-05T05:50:30.753804Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:30.739098Z","title":"The semiconductor decade: A trillion-dollar industry,","venue":null,"work_id":"8a4ef232-99d0-4742-8b17-e4396c474032","year":2022},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":2,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.392268Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:9b3885fca11279fce55511c70d7c1cbf84427a1d7441b051f6f2d041ab8ae746","observation_id":"26dcffd5-7f75-4906-95d7-52982660182d","resolution":{"observed_at":"2026-08-05T05:50:30.742599Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:30.727579Z","title":"Electronic design automation (eda) global market report 2025,","venue":null,"work_id":"13702c59-fc11-4ea6-a71e-bf3371c1292b","year":2025},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":3,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.500110Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:e85a5fbcbb0738ac453f0fb5e1851bb9248e32e1d4303d4770d3232b1e68161a","observation_id":"928c24d9-890f-4d51-ba7e-8d40c30c8ae0","resolution":{"observed_at":"2026-08-05T05:50:30.731121Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:30.716274Z","title":"Machine learning for electronic design automation: A survey,","venue":null,"work_id":"29d10798-b8f9-462b-9aa0-40ff500069eb","year":2021},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":4,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.577773Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:204a52a413adeaaaead9ad0364ba3eeabf70ccbeacc7de43a74de4f1812c7dc5","observation_id":"a6553b11-c539-430c-bf52-a438fd66629c","resolution":{"observed_at":"2026-08-05T05:50:30.719747Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:30.704206Z","title":"A survey of research in large language models for electronic design automation,","venue":null,"work_id":"beefa3cd-b06f-4394-a0b8-e871dd2adf25","year":2025},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":5,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.653786Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:9f6bc74f5aed553908346783dfac346b3e70d28fff648ff1531855da2369f769","observation_id":"3fc23f03-6e02-4ca6-8801-c0f75c067e7e","resolution":{"observed_at":"2026-08-05T05:50:30.708484Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:30.692725Z","title":"Chatcpu: An agile cpu design and verification platform with llm,","venue":null,"work_id":"88b58733-1a3f-414c-9f70-0c82d182dd76","year":2024},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":6,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.735875Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:ba0be9939c17d7c8cd7589c3c79e2257c5dd2c70d506617f63792537828fe685","observation_id":"da7fea96-c237-48ef-82bc-2d9ac082f58e","resolution":{"observed_at":"2026-08-05T05:50:30.696305Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:30.680872Z","title":"Llm-based processor verification: A case study for neuromorphic processor,","venue":null,"work_id":"d6aafacc-328d-4593-8cff-ed07cdda674d","year":2024},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.792632Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:12127336c88634d6a310dbb4be65fdb4dfe55fcc37cbbd7ff73e7968a28245de","observation_id":"cc294d16-cd06-47f2-a00e-7a048ef9531c","resolution":{"observed_at":"2026-08-05T05:50:30.684573Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:30.669535Z","title":"Llm-guided formal verification coupled with mutation testing,","venue":null,"work_id":"781ee323-24d4-4843-98c9-8ac4d8fd77fd","year":2024},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":8,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.796727Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:baceac81eb99c2497e87d0f316f54b6da976fd0ddf5a51f9bd4c69ce9b2d11b7","observation_id":"d52c5a49-458b-4b17-b10e-5fbfe1170a4d","resolution":{"observed_at":"2026-08-05T05:50:30.673002Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:30.658120Z","title":"Rtl- coder: Fully open-source and efficient llm-assisted rtl code generation technique,","venue":null,"work_id":"342592f3-0790-46d6-b0b9-b8ad392837ed","year":2024},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.800594Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:731ffff4085e5739027bc1fab0387b47cb8e3f5a7073bd4e11d825306dd5de32","observation_id":"72ce8098-054a-4324-974e-d324f7cead4e","resolution":{"observed_at":"2026-08-05T05:50:30.661612Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:30.646629Z","title":"Verilogcoder: Autonomous Verilog coding agents with graph-based planning and abstract syntax tree (ast)- based waveform tracing tool,","venue":null,"work_id":"45b6faa3-aa96-48d7-8c08-72641e576394","year":2025},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.804515Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:0e8ad9db43c6dc37f4fb38e94c0d86dae55b8f98c4e3d83c10f017009cbfacf2","observation_id":"6b93d49b-adaf-4a91-81ed-922edaef86d0","resolution":{"observed_at":"2026-08-05T05:50:30.650302Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:30.634969Z","title":"Large circuit models: opportunities and challenges,","venue":null,"work_id":"31370b4e-9c98-4027-b18b-747cab454fa5","year":2024},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":11,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.808457Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:85149aa87616c16ba241f3b78805a574099e21f073f8ece3a15dc2a41eca61ca","observation_id":"c09b8900-6a99-488e-9aba-27fc46f472ab","resolution":{"observed_at":"2026-08-05T05:50:30.638556Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:29.811928Z","title":"Chipgpt: How far are we from natural language hardware design,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":12,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.811928Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:d50edfda40c1cd776977365685a700fe2d40397e92ddb5df34b3cf069c8552c9","observation_id":"f5166c0a-5020-4d7a-9c3d-14c73dde9273","resolution":{"observed_at":"2026-08-05T05:50:29.811928Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:30.622929Z","title":"Revisiting verilogeval: A year of improvements in large-language models for hardware code generation,","venue":null,"work_id":"380b675d-1e78-4f6a-9750-387a16a90b28","year":2025},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":13,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.815686Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:ac37986b988f29506dfecf0727b7c2e4fb7c641e8fda66e798a4c925b67591e5","observation_id":"a0f3621e-d127-43e4-adeb-fa0e1edcec1a","resolution":{"observed_at":"2026-08-05T05:50:30.626507Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2506.14074","last_updated":"2025-06-17T00:11:13Z","snapshot_observed_at":"2026-08-15T19:52:10.016891Z","submitted_at":"2025-06-17T00:11:13Z","title":"Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2506.14074","snapshot_observed_at":"2026-08-05T05:50:29.819033Z","title":"Comprehensive Verilog design problems: A next-generation benchmark dataset for evaluating large language models and agents on rtl design and verification,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.819033Z"},"links":{"cited_paper":"/paper/2506.14074","citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:9d0d429267982d56e76e96f1f4028a8115e3a98020f09ec47f97ebd12ae81fd7","observation_id":"4fefa38d-41cd-4acc-9549-bf39075cadd6","resolution":{"observed_at":"2026-08-05T05:50:29.819033Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:30.610696Z","title":"Betterv: Controlled verilog generation with discriminative guidance,","venue":null,"work_id":"6684a28e-6afa-4017-b3bc-0d09c1214755","year":2024},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":15,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.822735Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:d639ea1c595d47b7fd451f4bd41fca93f7e4cee03be9c2a478a04f011dd87e7c","observation_id":"94643c6e-396b-4892-93b0-51838d862ae3","resolution":{"observed_at":"2026-08-05T05:50:30.614473Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:30.599200Z","title":"Deeprtl: Bridging verilog understanding and generation with a unified representation model,","venue":null,"work_id":"daf38b2c-4a29-4e8d-8914-c057fe60b960","year":2025},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":16,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.826682Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:2870e0fda69fdcb00ed5190a44c4e3613b3eb9f9f602ab762dde6a9b27a26177","observation_id":"df8e1062-732a-497f-8858-0b5feff5b34a","resolution":{"observed_at":"2026-08-05T05:50:30.602901Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:30.588017Z","title":"Deeprtl2: A versatile model for rtl-related tasks,","venue":null,"work_id":"5d443ee7-71df-46da-bb44-c37dfbcc6159","year":2025},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.830166Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:906ba8151e4ea9a708076de68d74c3f300d9d47825508a2667707a31e683967a","observation_id":"878372e9-9a00-4549-8975-1b85d1f2e024","resolution":{"observed_at":"2026-08-05T05:50:30.591501Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2405.16072","last_updated":"2024-09-23T14:38:16Z","snapshot_observed_at":"2026-08-16T13:49:32.812665Z","submitted_at":"2024-05-25T05:45:55Z","title":"SynthAI: A Multi Agent Generative AI Framework for Automated Modular HLS Design Generation","version":4},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2405.16072","snapshot_observed_at":"2026-08-05T05:50:29.833591Z","title":"Synthai: A multi agent gen- erative ai framework for automated modular hls design generation,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":18,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.833591Z"},"links":{"cited_paper":"/paper/2405.16072","citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:92266b092d6410181ca057b49e5ce3ae6491e9b92b9001cd8b89dc9a8db25b85","observation_id":"32838db4-89fc-44d5-a738-2bdf99f2f5bb","resolution":{"observed_at":"2026-08-05T05:50:29.833591Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:30.575685Z","title":"Assertllm: Generating hardware verification assertions from design specifications via multi-llms,","venue":null,"work_id":"1799f0be-d69d-4c19-9e03-5e622482849e","year":2025},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":19,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.837210Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:04fc19e79d6d7042d33b8a70747fc814eebb30fdef8ab5de7dd522cca4219ed6","observation_id":"843aeaa3-db56-4441-8ade-b17d343631a9","resolution":{"observed_at":"2026-08-05T05:50:30.579569Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:30.563568Z","title":"Assertionbench: A benchmark to evaluate large-language models for assertion generation,","venue":null,"work_id":"cbc638cb-6306-4dbd-b14b-afec43dd0563","year":2025},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":20,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.840608Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:3c2bd2626f7ae5e79a645166ad3c7c73e6a14d0c0b50cdb24867db506d194d64","observation_id":"81fcaf07-9373-470d-839d-82daccfe3440","resolution":{"observed_at":"2026-08-05T05:50:30.567397Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:30.550265Z","title":"Rtlfixer: Automatically fixing rtl syntax errors with large language model,","venue":null,"work_id":"002f697d-e2c7-47b3-ad56-55148e890aaa","year":2024},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":21,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.844298Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:3775aff1b21369cf7e95cb704e59e1ff9a1fd0863cc327560511a967efbd2619","observation_id":"e553c74f-68a3-41ef-8660-8b94468e158c","resolution":{"observed_at":"2026-08-05T05:50:30.554297Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-08-16T14:47:02.577158Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-05T05:50:29.847849Z","title":"Chipnemo: Domain-adapted llms for chip design,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":22,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.847849Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:208da7902d018c52f9430b56474ca606d025a040e640715a86e1b5f7be70b79b","observation_id":"c732ae9d-b738-4392-908c-b06fd4192373","resolution":{"observed_at":"2026-08-05T05:50:29.847849Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:30.537538Z","title":"Customized retrieval augmented generation and benchmarking for eda tool documentation qa,","venue":null,"work_id":"7a624e64-125e-43dc-b07d-631caeb4a365","year":2024},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":23,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.851714Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:37295616842c8a0f6f076fb5e0ab1e30c88831c6882576959fc49738359faed4","observation_id":"c551e8e4-73a1-431d-8f41-79664b5b503c","resolution":{"observed_at":"2026-08-05T05:50:30.541541Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:30.523924Z","title":"Drc-coder: Automated drc checker code generation using llm autonomous agent,","venue":null,"work_id":"b4284789-9942-496b-b96c-0cb38b9ec7d4","year":2025},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":24,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.855215Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:5e61fdf4afa7428c2e4223b53d68909cc4a743cd2b81ed9bab3439ed670a804d","observation_id":"1e3fb026-3f97-4767-b0ce-9c236a3d5c93","resolution":{"observed_at":"2026-08-05T05:50:30.528394Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:30.511176Z","title":"Rtlrewriter: Methodologies for large models aided rtl code optimization,","venue":null,"work_id":"63d72fa1-b4e8-457f-9edc-2e8438ba4a85","year":2024},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":25,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.858609Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:c6b66c5860c4c1546a00e10aa2603e6a28030bb75d57ce24981da64a52dacf34","observation_id":"aee644d1-4d37-4bc2-a351-bd2672758ff7","resolution":{"observed_at":"2026-08-05T05:50:30.515132Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:30.499492Z","title":"Deepgate: Learning neural representations of logic gates,","venue":null,"work_id":"3460789b-b1c2-43e9-85bc-0f3ed9f49acb","year":2022},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":26,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.861933Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:ab5970176b2c7ae613466e46065baa09f1c15bbd95c5955f923958c68251e183","observation_id":"5a50e2d6-6a2d-4b62-86f1-1e62bb874444","resolution":{"observed_at":"2026-08-05T05:50:30.503066Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:30.485913Z","title":"Maskplace: Fast chip placement via reinforced visual representation learning,","venue":null,"work_id":"299e3db3-8148-4ba0-a5ba-70d3964250d5","year":2022},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":27,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.865386Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:b030b3a0ba02d4dfe2d588a56a4ee61d690292da62d27269e878451350ca8360","observation_id":"09efadab-49e2-4f08-b6fe-5aeaf7de115d","resolution":{"observed_at":"2026-08-05T05:50:30.489739Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:30.472342Z","title":"Deepgate3: Towards scalable circuit representation learning,","venue":null,"work_id":"1e1dc434-0e93-4f52-9c04-1f1dcf68714c","year":2024},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":28,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.868691Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:a069174265a3320661bad669cf7e30bca0a86cd1dfc1b3316a5a6fc0217fa9f2","observation_id":"34e5885f-17bc-49d8-97a0-495a43b2fa5a","resolution":{"observed_at":"2026-08-05T05:50:30.476144Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:30.459735Z","title":"Deepcell: Self-supervised multiview fusion for circuit representation learning,","venue":null,"work_id":"37767f7e-15cf-4e1e-b40f-5da86019eb4b","year":2025},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":29,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.872347Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:2f32ab7bcc0f43e2912405836b0a08f99b1c3ffe23e0abaa1c42efcc19f53acc","observation_id":"8631836d-890a-4349-9a1a-9040b5e37517","resolution":{"observed_at":"2026-08-05T05:50:30.463790Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:30.447516Z","title":"Circuitfusion: Multimodal circuit representation learning for agile chip design,","venue":null,"work_id":"df078f56-2601-4497-a6f5-1a8791149fe4","year":2025},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":30,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.875722Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:2b35fe640c912e174b9a27d250b796913b62d8f98356c47024ad0180a1e0ee6c","observation_id":"f246af36-f983-47f3-9aee-7c32eafa3b76","resolution":{"observed_at":"2026-08-05T05:50:30.451303Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2311.04887","last_updated":"2024-06-04T19:12:48Z","snapshot_observed_at":"2026-08-16T14:44:51.915570Z","submitted_at":"2023-11-08T18:46:39Z","title":"AutoChip: Automating HDL Generation Using LLM Feedback","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.04887","snapshot_observed_at":"2026-08-05T05:50:29.879093Z","title":"Autochip: Automating hdl generation using llm feedback,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":31,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.879093Z"},"links":{"cited_paper":"/paper/2311.04887","citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:b5b75508453eae978a9a9925e4e9c4959fd5d1bfe276ddedce17dc01e14f5b3a","observation_id":"940ad1a5-aa06-439e-861b-192380c0f889","resolution":{"observed_at":"2026-08-05T05:50:29.879093Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:30.435425Z","title":"Autobench: Automatic testbench generation and evaluation using LLMs for HDL design,","venue":null,"work_id":"2bba6b8a-ab29-4579-8749-8dc687df2ca7","year":2024},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":32,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.882881Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:733a4e7475ac07d926789ebbdd956422c0703a2bfdfe8629861be1eb6fc76de3","observation_id":"4cb5c1a9-d943-4722-be97-8b0f37983dbf","resolution":{"observed_at":"2026-08-05T05:50:30.439109Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:30.423664Z","title":"Uvllm: An automated universal rtl verification framework using llms,","venue":null,"work_id":"ba9f50e2-e758-4755-afc8-80bb33dba1ac","year":2025},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":33,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.886575Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:2f5fab8f4d33e211d65cb38ee8b1132c283c5a88c7932e6ec43e890ae3891326","observation_id":"2c778a2c-e9b4-43d5-9118-1e1957dbc488","resolution":{"observed_at":"2026-08-05T05:50:30.427306Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:30.411496Z","title":"Llms for hardware verification: Frameworks, techniques, and future directions,","venue":null,"work_id":"e4f5fc34-7146-4b71-945f-34852ebb26cc","year":2024},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":34,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.890126Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:968083904592ff1985dc93909d131cfa125b7fc667fb0eb0aeddf19f58a4902d","observation_id":"3098f8b9-262f-4e46-b733-7f556890a0b9","resolution":{"observed_at":"2026-08-05T05:50:30.415528Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:30.399663Z","title":"Prompt. verify. repeat. llms in the hardware verification cycle,","venue":null,"work_id":"5803a609-7e2a-49bc-83dc-2e5e9a8431c2","year":2025},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":35,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.893537Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:247a949e22ec1f825b01bc1a9eb518a2643ecb859b5d3d7f7fcbe9422b3876f6","observation_id":"3b2f21e8-979b-4df9-ac80-72b19c842614","resolution":{"observed_at":"2026-08-05T05:50:30.403344Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2506.15066","last_updated":"2026-06-29T07:25:06Z","snapshot_observed_at":"2026-08-15T23:36:47.538890Z","submitted_at":"2025-06-18T02:15:02Z","title":"ChatModel: Automating Reference Model Design and Verification with LLMs","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2506.15066","snapshot_observed_at":"2026-08-05T05:50:29.896944Z","title":"Chat- model: Automating reference model design and verification with llms,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":36,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.896944Z"},"links":{"cited_paper":"/paper/2506.15066","citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:a6101bf770b20718eb6a9312ca89e201dc0d278c4e8a6d4a5716f34c582e821a","observation_id":"68ada99a-d079-4f5f-8b4a-80a850cec4e5","resolution":{"observed_at":"2026-08-05T05:50:29.896944Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:30.387896Z","title":"Meic: Re-thinking rtl debug automation using llms,","venue":null,"work_id":"2bd2da50-64d9-4020-8563-0b50c0bb8ba2","year":2024},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":37,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.900897Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:ea00fedcd6bbf8c62393d06a2d5cdc000dff13e46461b3a94a193e6331c21792","observation_id":"3c381054-0bc8-4905-a46b-5873b0afab9a","resolution":{"observed_at":"2026-08-05T05:50:30.391522Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2504.19099","last_updated":"2025-04-27T04:09:48Z","snapshot_observed_at":"2026-08-16T05:59:09.647372Z","submitted_at":"2025-04-27T04:09:48Z","title":"VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correction","version":1},"cited_work":{"arxiv_id":"2504.19099","doi":null,"metadata_source":"pith","pith_arxiv_id":"2504.19099","snapshot_observed_at":"2026-08-05T05:50:30.043766Z","title":"VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correction","venue":"cs.SE","work_id":"b42cfa28-c3f4-48af-a37b-20f106316757","year":2025},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":38,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.904392Z"},"links":{"cited_paper":"/paper/2504.19099","citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:8aadc8001e59f8ead9302c3e360827db43d5554f6a47e8a4c9067bc8da91907f","observation_id":"be6ce78f-e184-4b37-b94d-94f4063a2c1d","resolution":{"observed_at":"2026-08-05T05:50:30.148024Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2508.01191","last_updated":"2026-05-08T20:20:58Z","snapshot_observed_at":"2026-07-06T22:06:38.785781Z","submitted_at":"2025-08-02T04:37:28Z","title":"Is Chain-of-Thought Reasoning of LLMs a Mirage? A Data Distribution Lens","version":6},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2508.01191","snapshot_observed_at":"2026-08-05T05:50:29.908555Z","title":"Is chain-of-thought reasoning of LLMs a mirage? a data distribution lens,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":39,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.908555Z"},"links":{"cited_paper":"/paper/2508.01191","citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:e4d159c4489292fb4edd1a6ab31251f40a3865c6dd4faa80ac9b02a62e07a82a","observation_id":"fcf90e96-9f77-4510-b137-53b4ac61dc1c","resolution":{"observed_at":"2026-08-05T05:50:29.908555Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:30.375792Z","title":"Improving llm-powered eda assistants with raft,","venue":null,"work_id":"d96c598f-c905-4ec1-aaab-736658ffbcf9","year":2025},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":40,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.912291Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:b961c1d02642dc4d42a3a5e720b40ebdf632d3805e3975972227f12f8e4c595f","observation_id":"7533358a-8a4e-415a-b4c7-c214ea7cf193","resolution":{"observed_at":"2026-08-05T05:50:30.379366Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2505.09610","last_updated":"2025-05-14T17:58:40Z","snapshot_observed_at":"2026-08-16T01:26:44.298423Z","submitted_at":"2025-05-14T17:58:40Z","title":"Customizing a Large Language Model for VHDL Design of High-Performance Microprocessors","version":1},"cited_work":{"arxiv_id":"2505.09610","doi":null,"metadata_source":"pith","pith_arxiv_id":"2505.09610","snapshot_observed_at":"2026-08-05T05:50:30.008585Z","title":"Customizing a Large Language Model for VHDL Design of High-Performance Microprocessors","venue":"cs.AR","work_id":"335ccee2-617d-4a40-8d44-aad23de1f332","year":2025},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":41,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.915922Z"},"links":{"cited_paper":"/paper/2505.09610","citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:c00a6299388f8fd5d7c2c4dd2ec09b7494823d71dfe1f7673cff43c426099b07","observation_id":"df1baf80-5600-41ea-871f-9338f38236e2","resolution":{"observed_at":"2026-08-05T05:50:30.015038Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:30.364057Z","title":"Accurate predictions on small data with a tabular foundation model,","venue":null,"work_id":"6b03e72a-24bc-4eb4-8138-873112a38547","year":2025},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":42,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.919497Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:6495bacd5df1bde6b7555b220b74b5f9e8cbf2045f72490d1a6250068d486eb5","observation_id":"776b5908-72d9-40b0-a4ba-957165aa8ac0","resolution":{"observed_at":"2026-08-05T05:50:30.367616Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:30.351454Z","title":"Transformers can do arithmetic with the right em- beddings,","venue":null,"work_id":"be239e44-d506-41da-8c21-fe4257bbf8fb","year":2024},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":43,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.922979Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:ed379d0be9eabe5f04afc942ed2c5ca0d51f2ab3f4b399e7bba26c0b7331c013","observation_id":"5fb13fea-8ee8-40a3-926d-bfbb9c81b274","resolution":{"observed_at":"2026-08-05T05:50:30.355605Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2506.06941","last_updated":"2025-11-20T00:19:24Z","snapshot_observed_at":"2026-08-09T21:19:24.140229Z","submitted_at":"2025-06-07T22:42:29Z","title":"The Illusion of Thinking: Understanding the Strengths and Limitations of Reasoning Models via the Lens of Problem Complexity","version":3},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2506.06941","snapshot_observed_at":"2026-08-05T05:50:29.926202Z","title":"The illusion of thinking: Understanding the strengths and limitations of reasoning models via the lens of problem complexity,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":44,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.926202Z"},"links":{"cited_paper":"/paper/2506.06941","citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:342b55cb8369e6419bb9186c46796e67a6996df963802595d6bfe5d6f0c3b41e","observation_id":"bbe6fbef-3632-4184-aec0-93c95c66c9c0","resolution":{"observed_at":"2026-08-05T05:50:29.926202Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:30.338511Z","title":"Measuring the impact of early-2025 AI on experienced open-source developer productivity,","venue":null,"work_id":"d19e55db-522d-4ff0-85e7-9ca978773a05","year":2025},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":45,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.930036Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:da9584a84a8a457637a9821385abbf68703384ee70a8fd4bdc9fbe5950b0c8a9","observation_id":"9156f28c-27aa-43a7-a539-2336b1ddfd99","resolution":{"observed_at":"2026-08-05T05:50:30.342349Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:30.326514Z","title":"Correctbench: Automatic testbench generation with functional self- correction using LLMs for HDL design,","venue":null,"work_id":"0a5f0820-3a6a-499c-afee-86c7dcaee311","year":2025},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":46,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.933515Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:e8677a9eeb67c16cd6e649ed9c62229010777844bbf1c6246917f05a3ffc74b0","observation_id":"03180307-f73c-4d60-9ff9-e426a1c915cf","resolution":{"observed_at":"2026-08-05T05:50:30.330234Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:30.313450Z","title":"Genben: A generative benchmark for LLM-aided design,","venue":null,"work_id":"d615aadd-3b9f-4f1e-8685-2f7e532152e1","year":2025},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":47,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.936897Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:0cd074ca2a87eb6c8fafd86997ac6f59edb49c5bbfc40dd74c06b6bedd6eb23f","observation_id":"9cbde998-b836-43d1-b146-ee5aa4cffb23","resolution":{"observed_at":"2026-08-05T05:50:30.317623Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2507.04276","last_updated":"2025-07-06T07:32:01Z","snapshot_observed_at":"2026-08-14T02:16:34.157458Z","submitted_at":"2025-07-06T07:32:01Z","title":"FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2507.04276","snapshot_observed_at":"2026-08-05T05:50:29.940447Z","title":"Fixme: Towards end-to-end bench- marking of llm-aided design verification,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":48,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.940447Z"},"links":{"cited_paper":"/paper/2507.04276","citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:2bdb757aa9e5ae12172b3ee897592dd66e0c6a957fb677c128915289aa92cf61","observation_id":"906a3cae-8dbb-43c1-9f09-55e02d796b6d","resolution":{"observed_at":"2026-08-05T05:50:29.940447Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:30.301085Z","title":"Deepcircuitx: A comprehensive repository-level dataset for rtl code understanding, generation, and ppa analysis,","venue":null,"work_id":"ec359bb1-c392-45cd-873e-0c2555f08bdf","year":2025},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":49,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.944157Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:bca997f6c327899d0ea26a90602cca090e55837247fd7e90f184cbd5ef92a0de","observation_id":"935d7aca-44df-4213-82fb-a32c07c45627","resolution":{"observed_at":"2026-08-05T05:50:30.304955Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T05:50:30.288739Z","title":"Forgeeda: A comprehensive multimodal dataset for advancing eda,","venue":null,"work_id":"f7d0aaf2-317b-4ff0-a681-161cf08a2e76","year":2025},"citing_paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design","version":1},"reference_index":50,"source":"pdf_text","source_observed_at":"2026-08-05T05:50:29.947770Z"},"links":{"citing_paper":"/paper/2509.04905"},"observation_digest":"sha256:0bb8e20c8aa3aea9bdff8fa0822fba3afbacbb3ba97bab80edee74f10897a28f","observation_id":"2f59ac46-8e54-4768-bc53-87921a52c46a","resolution":{"observed_at":"2026-08-05T05:50:30.292586Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"state":"measured"}}],"paper":{"arxiv_id":"2509.04905","last_updated":"2025-09-05T08:23:16Z","latest_version":1,"primary_category":"cs.LG","snapshot_observed_at":"2026-08-10T07:17:26.305197Z","submitted_at":"2025-09-05T08:23:16Z","title":"Revolution or Hype? Seeking the Limits of Large Models in Hardware Design"},"reference_resolution":{"displayed":50,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":9,"verified_exact":2,"verified_fuzzy":39},"total_outbound_references":50},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-16T06:30:59.297886+00:00","source":"crossref"},{"observed_at":"2026-08-16T06:30:54.164669+00:00","source":"retraction_watch"}],"thesis":"As of 16 August 2026, this Paper Citation Record lists 50 of 50 outbound references and 1 inbound Pith citation observation for arXiv:2509.04905."}