{"as_of":"2026-08-15T10:59:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:b3d52ea127747520f95411b3e479d3acf9657d2bbf18cb9d4813775762130bcb","coverage":[{"denominator":19,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":19,"source":"paper_references, paper_reference_links","source_observed_at":"2026-05-18T14:07:18.826032Z","state":"measured"},{"denominator":19,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":19,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-15T06:32:42.880941+00:00","state":"measured"},{"denominator":0,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"cited_works","source_observed_at":null,"state":"measured"}],"external_citation_measurements":[],"inbound":[],"links":{"evidence":"/evidence","html":"/paper/2509.18355/citation-record","integrity":"/paper/2509.18355/integrity","json":"/paper/2509.18355/citation-record.json","paper":"/paper/2509.18355"},"outbound":[{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"2019.291895","doi":"10.1109/jproc.2019.2918951","metadata_source":"arxiv_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"Edge Intelligence: Paving the Way for a New Era of AI","venue":"Proceedings of the IEEE","work_id":"3082b97d-d3dc-481d-9e40-511a8117786a","year":2019},"citing_paper":{"arxiv_id":"2509.18355","last_updated":"2026-04-07T17:04:22Z","snapshot_observed_at":"2026-08-07T01:18:14.379202Z","submitted_at":"2025-09-22T19:31:58Z","title":"Chiplet-Based RISC-V SoC with Modular AI Acceleration","version":5},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-05-18T14:07:18.826032Z"},"links":{"citing_paper":"/paper/2509.18355"},"observation_digest":"sha256:699d4bcab515d3edf2fca8a6000c89becf7cda63f3877895e3e9a07522550d32","observation_id":"d452d6be-656a-4315-a817-305c5d010849","resolution":{"observed_at":"2026-05-18T14:11:27.176126Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-15T06:32:42.880941+00:00","source":"crossref"},{"observed_at":"2026-08-15T06:32:39.529945+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"MobileNetV2: Inverted residuals and linear bottlenecks","venue":null,"work_id":"786216a1-b392-479d-aea7-892468a3dbc2","year":2018},"citing_paper":{"arxiv_id":"2509.18355","last_updated":"2026-04-07T17:04:22Z","snapshot_observed_at":"2026-08-07T01:18:14.379202Z","submitted_at":"2025-09-22T19:31:58Z","title":"Chiplet-Based RISC-V SoC with Modular AI Acceleration","version":5},"reference_index":2,"source":"pdf_text","source_observed_at":"2026-05-18T14:07:18.826032Z"},"links":{"citing_paper":"/paper/2509.18355"},"observation_digest":"sha256:a5dd7239d46d8b3ec5958662c0c3f6786cdc0b4c855b6e5e4c5ef78f0037e51a","observation_id":"6c14f73b-3deb-424d-97da-c0e8257a58d0","resolution":{"observed_at":"2026-05-18T14:12:40.458803Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-15T06:32:42.880941+00:00","source":"crossref"},{"observed_at":"2026-08-15T06:32:39.529945+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Deep residual learning for image recognition","venue":null,"work_id":"ff280535-8c3e-4871-a24d-1358ee9847a0","year":2016},"citing_paper":{"arxiv_id":"2509.18355","last_updated":"2026-04-07T17:04:22Z","snapshot_observed_at":"2026-08-07T01:18:14.379202Z","submitted_at":"2025-09-22T19:31:58Z","title":"Chiplet-Based RISC-V SoC with Modular AI Acceleration","version":5},"reference_index":3,"source":"pdf_text","source_observed_at":"2026-05-18T14:07:18.826032Z"},"links":{"citing_paper":"/paper/2509.18355"},"observation_digest":"sha256:11d2fe560153dcc2048f1ebb7042d33ab0bcc52a806b15d70e5882569667e5ca","observation_id":"1aff1da8-5c1d-4036-9d67-4ae4439e7fe2","resolution":{"observed_at":"2026-05-18T14:12:40.455722Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-15T06:32:42.880941+00:00","source":"crossref"},{"observed_at":"2026-08-15T06:32:39.529945+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Modeling statistical dopant fluctuations in MOS transistors","venue":null,"work_id":"0067dd0b-06c9-4b03-b910-5440eced8cad","year":1960},"citing_paper":{"arxiv_id":"2509.18355","last_updated":"2026-04-07T17:04:22Z","snapshot_observed_at":"2026-08-07T01:18:14.379202Z","submitted_at":"2025-09-22T19:31:58Z","title":"Chiplet-Based RISC-V SoC with Modular AI Acceleration","version":5},"reference_index":4,"source":"pdf_text","source_observed_at":"2026-05-18T14:07:18.826032Z"},"links":{"citing_paper":"/paper/2509.18355"},"observation_digest":"sha256:e6cf7d40199fa9e71b6e83e968d4c36dc651926557f06863f39d724ea2b02cbe","observation_id":"1312076f-7ee9-4cc2-9087-f5d02a0e60c8","resolution":{"observed_at":"2026-05-18T14:12:40.467541Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-15T06:32:42.880941+00:00","source":"crossref"},{"observed_at":"2026-08-15T06:32:39.529945+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"The use and evaluation of yield models in integrated circuit manufacturing","venue":null,"work_id":"bcd39b82-ae1b-41cd-b8a6-35df63688ef4","year":1990},"citing_paper":{"arxiv_id":"2509.18355","last_updated":"2026-04-07T17:04:22Z","snapshot_observed_at":"2026-08-07T01:18:14.379202Z","submitted_at":"2025-09-22T19:31:58Z","title":"Chiplet-Based RISC-V SoC with Modular AI Acceleration","version":5},"reference_index":5,"source":"pdf_text","source_observed_at":"2026-05-18T14:07:18.826032Z"},"links":{"citing_paper":"/paper/2509.18355"},"observation_digest":"sha256:1b2bd20550c4e63f65860b101d6dc37474814f578bc6823ddfe8df2ca780ae8a","observation_id":"f78cd475-f364-41fd-aa1d-c4558d5a935f","resolution":{"observed_at":"2026-05-18T14:12:40.464680Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-15T06:32:42.880941+00:00","source":"crossref"},{"observed_at":"2026-08-15T06:32:39.529945+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"TAP-2.5D: A thermally-aware chiplet placement framework for 2.5D systems","venue":null,"work_id":"6bb3db14-449a-4ed9-ab2c-6ba2eb79a329","year":2021},"citing_paper":{"arxiv_id":"2509.18355","last_updated":"2026-04-07T17:04:22Z","snapshot_observed_at":"2026-08-07T01:18:14.379202Z","submitted_at":"2025-09-22T19:31:58Z","title":"Chiplet-Based RISC-V SoC with Modular AI Acceleration","version":5},"reference_index":6,"source":"pdf_text","source_observed_at":"2026-05-18T14:07:18.826032Z"},"links":{"citing_paper":"/paper/2509.18355"},"observation_digest":"sha256:98cc08d97cc20efeae8248b2e39b32d4fcec8dc66b593b1a98a309ffe2f1239c","observation_id":"22321e8a-e5c7-4968-ad63-b2f7f00ffffb","resolution":{"observed_at":"2026-05-18T14:12:40.461729Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-15T06:32:42.880941+00:00","source":"crossref"},{"observed_at":"2026-08-15T06:32:39.529945+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"High-performance, power-efficient three-dimensional chiplet systems","venue":null,"work_id":"9cc77eb5-e7f1-44ce-8817-c738c26603b7","year":2024},"citing_paper":{"arxiv_id":"2509.18355","last_updated":"2026-04-07T17:04:22Z","snapshot_observed_at":"2026-08-07T01:18:14.379202Z","submitted_at":"2025-09-22T19:31:58Z","title":"Chiplet-Based RISC-V SoC with Modular AI Acceleration","version":5},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-05-18T14:07:18.826032Z"},"links":{"citing_paper":"/paper/2509.18355"},"observation_digest":"sha256:bf0bb9a0fac9476ec4b774147de9895e846e6e239b1a0243f427430b802eb12b","observation_id":"0bfc9c88-d608-4fec-82c3-505c0a2537a6","resolution":{"observed_at":"2026-05-18T14:12:40.427434Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-15T06:32:42.880941+00:00","source":"crossref"},{"observed_at":"2026-08-15T06:32:39.529945+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"A 17–95.6 TOPS/W deep learning inference accelerator with per-vector scaled 4-bit quantization in 5 nm","venue":null,"work_id":"79f66b77-a6d1-47b7-aef8-2a1e0bb896ba","year":2023},"citing_paper":{"arxiv_id":"2509.18355","last_updated":"2026-04-07T17:04:22Z","snapshot_observed_at":"2026-08-07T01:18:14.379202Z","submitted_at":"2025-09-22T19:31:58Z","title":"Chiplet-Based RISC-V SoC with Modular AI Acceleration","version":5},"reference_index":8,"source":"pdf_text","source_observed_at":"2026-05-18T14:07:18.826032Z"},"links":{"citing_paper":"/paper/2509.18355"},"observation_digest":"sha256:e0c4b63660de728abd8daa88b61fa0f2f1d614f8267fbbd764051ebdce4e3e9b","observation_id":"a3b6d085-e785-48d9-8a59-8fdb3e952b1c","resolution":{"observed_at":"2026-05-18T14:12:40.452468Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-15T06:32:42.880941+00:00","source":"crossref"},{"observed_at":"2026-08-15T06:32:39.529945+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"High Bandwidth Memory (HBM3) DRAM Standard JESD238","venue":null,"work_id":"2308aa66-b06b-4e56-9a71-3bbac3860685","year":2022},"citing_paper":{"arxiv_id":"2509.18355","last_updated":"2026-04-07T17:04:22Z","snapshot_observed_at":"2026-08-07T01:18:14.379202Z","submitted_at":"2025-09-22T19:31:58Z","title":"Chiplet-Based RISC-V SoC with Modular AI Acceleration","version":5},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-05-18T14:07:18.826032Z"},"links":{"citing_paper":"/paper/2509.18355"},"observation_digest":"sha256:656a08fc9e533e16e51ab495ef52ffea218a10a20716a6016e9875382027e4c0","observation_id":"a7a809e8-05aa-469b-b2c7-d6f3200ec44c","resolution":{"observed_at":"2026-05-18T14:12:40.449222Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-15T06:32:42.880941+00:00","source":"crossref"},{"observed_at":"2026-08-15T06:32:39.529945+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"HBM3 stacking and integration challenges","venue":null,"work_id":"21b59ecc-4d46-457e-af30-e660518b27c9","year":2023},"citing_paper":{"arxiv_id":"2509.18355","last_updated":"2026-04-07T17:04:22Z","snapshot_observed_at":"2026-08-07T01:18:14.379202Z","submitted_at":"2025-09-22T19:31:58Z","title":"Chiplet-Based RISC-V SoC with Modular AI Acceleration","version":5},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-05-18T14:07:18.826032Z"},"links":{"citing_paper":"/paper/2509.18355"},"observation_digest":"sha256:08e5901168acbe775d8d653c28e3dfc47eeea304b4202c9dd6fea5aac1ba2039","observation_id":"d187649c-328e-4753-8508-7d7f50fc1f09","resolution":{"observed_at":"2026-05-18T14:12:40.445768Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-15T06:32:42.880941+00:00","source":"crossref"},{"observed_at":"2026-08-15T06:32:39.529945+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Fine-grained DVFS using on-chip regulators","venue":null,"work_id":"1fcf65e0-2ee8-4b33-8c24-8af0300d894c","year":2011},"citing_paper":{"arxiv_id":"2509.18355","last_updated":"2026-04-07T17:04:22Z","snapshot_observed_at":"2026-08-07T01:18:14.379202Z","submitted_at":"2025-09-22T19:31:58Z","title":"Chiplet-Based RISC-V SoC with Modular AI Acceleration","version":5},"reference_index":11,"source":"pdf_text","source_observed_at":"2026-05-18T14:07:18.826032Z"},"links":{"citing_paper":"/paper/2509.18355"},"observation_digest":"sha256:e612d15ae43ed7b47bfe40ccb78d99c7d2f86403fd17be0cc4c167242fb312cb","observation_id":"f2ebc85d-16d6-4574-bfbd-9e363e53536a","resolution":{"observed_at":"2026-05-18T14:12:40.430209Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-15T06:32:42.880941+00:00","source":"crossref"},{"observed_at":"2026-08-15T06:32:39.529945+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Adaptive DVFS and thread packing under power caps","venue":null,"work_id":"1c733ff2-4d35-444d-954f-508982cc4e24","year":2011},"citing_paper":{"arxiv_id":"2509.18355","last_updated":"2026-04-07T17:04:22Z","snapshot_observed_at":"2026-08-07T01:18:14.379202Z","submitted_at":"2025-09-22T19:31:58Z","title":"Chiplet-Based RISC-V SoC with Modular AI Acceleration","version":5},"reference_index":12,"source":"pdf_text","source_observed_at":"2026-05-18T14:07:18.826032Z"},"links":{"citing_paper":"/paper/2509.18355"},"observation_digest":"sha256:de63aad9f4469d99cb8fa182fd56ddf9016bcb033b33d64465741ff3e329f909","observation_id":"9832bf27-7eed-47fd-b185-7584efffa71d","resolution":{"observed_at":"2026-05-18T14:12:40.442841Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-15T06:32:42.880941+00:00","source":"crossref"},{"observed_at":"2026-08-15T06:32:39.529945+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"2.5D root of trust: Secure system-level integration of untrusted chiplets","venue":null,"work_id":"d0dba6f2-0759-431e-b1dc-bdb9484c3444","year":2020},"citing_paper":{"arxiv_id":"2509.18355","last_updated":"2026-04-07T17:04:22Z","snapshot_observed_at":"2026-08-07T01:18:14.379202Z","submitted_at":"2025-09-22T19:31:58Z","title":"Chiplet-Based RISC-V SoC with Modular AI Acceleration","version":5},"reference_index":13,"source":"pdf_text","source_observed_at":"2026-05-18T14:07:18.826032Z"},"links":{"citing_paper":"/paper/2509.18355"},"observation_digest":"sha256:905035157e0e37a57633d6e955e68310b6b8830b273290843a324dc1b962a803","observation_id":"9507ec59-96b3-4e13-be7d-17166719ba35","resolution":{"observed_at":"2026-05-18T14:12:40.439759Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-15T06:32:42.880941+00:00","source":"crossref"},{"observed_at":"2026-08-15T06:32:39.529945+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Temperature-aware microarchitecture: Modeling and implementation","venue":null,"work_id":"a978e65f-8eec-484e-a5db-691b906aa3b5","year":2003},"citing_paper":{"arxiv_id":"2509.18355","last_updated":"2026-04-07T17:04:22Z","snapshot_observed_at":"2026-08-07T01:18:14.379202Z","submitted_at":"2025-09-22T19:31:58Z","title":"Chiplet-Based RISC-V SoC with Modular AI Acceleration","version":5},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-05-18T14:07:18.826032Z"},"links":{"citing_paper":"/paper/2509.18355"},"observation_digest":"sha256:c547651045d15d9d43a2616037c283311ad7a3afdb5bca5a735569d865c6769d","observation_id":"159d71e7-86d3-4c68-9ad6-872f74eebf3c","resolution":{"observed_at":"2026-05-18T14:12:40.433081Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-15T06:32:42.880941+00:00","source":"crossref"},{"observed_at":"2026-08-15T06:32:39.529945+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Thermal management for 3D-stacked systems via unified DVFS and load power management","venue":null,"work_id":"a242fd49-46c9-4adb-bb87-6063ea9f8626","year":2023},"citing_paper":{"arxiv_id":"2509.18355","last_updated":"2026-04-07T17:04:22Z","snapshot_observed_at":"2026-08-07T01:18:14.379202Z","submitted_at":"2025-09-22T19:31:58Z","title":"Chiplet-Based RISC-V SoC with Modular AI Acceleration","version":5},"reference_index":15,"source":"pdf_text","source_observed_at":"2026-05-18T14:07:18.826032Z"},"links":{"citing_paper":"/paper/2509.18355"},"observation_digest":"sha256:c1b108c3049e5faad2973d08760b81bdce36ffe84b1cef28f050f25b1f3eab35","observation_id":"9fd787e4-f958-4ffd-816e-1cb883f601bb","resolution":{"observed_at":"2026-05-18T14:12:40.436623Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-15T06:32:42.880941+00:00","source":"crossref"},{"observed_at":"2026-08-15T06:32:39.529945+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"2008.465863","doi":"10.1109/hpca.2008.4658633","metadata_source":"arxiv_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"System level analysis of fast, per-core DVFS using on-chip switching regulators","venue":"Proceedings - International Symposium on High-Performance Computer Architecture/Proceedings","work_id":"a1b404b8-16f7-4482-94a1-f77acade7e06","year":2008},"citing_paper":{"arxiv_id":"2509.18355","last_updated":"2026-04-07T17:04:22Z","snapshot_observed_at":"2026-08-07T01:18:14.379202Z","submitted_at":"2025-09-22T19:31:58Z","title":"Chiplet-Based RISC-V SoC with Modular AI Acceleration","version":5},"reference_index":16,"source":"pdf_text","source_observed_at":"2026-05-18T14:07:18.826032Z"},"links":{"citing_paper":"/paper/2509.18355"},"observation_digest":"sha256:3c14c2e28c8039973e06f41a1d1bbce4e47bedb23a4623cc1e6e1d82cd14071d","observation_id":"758492a7-f56b-415c-b207-a2363ba3ff2e","resolution":{"observed_at":"2026-05-18T14:11:27.188148Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-15T06:32:42.880941+00:00","source":"crossref"},{"observed_at":"2026-08-15T06:32:39.529945+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"2998.195299","doi":"10.1145/1952998.1952999","metadata_source":"arxiv_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"Fine-Grained DVFS Using On-Chip Regulators","venue":"ACM Transactions on Architecture and Code Optimization","work_id":"6b01319a-8864-428b-adb4-28085a1cf1fe","year":2011},"citing_paper":{"arxiv_id":"2509.18355","last_updated":"2026-04-07T17:04:22Z","snapshot_observed_at":"2026-08-07T01:18:14.379202Z","submitted_at":"2025-09-22T19:31:58Z","title":"Chiplet-Based RISC-V SoC with Modular AI Acceleration","version":5},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-05-18T14:07:18.826032Z"},"links":{"citing_paper":"/paper/2509.18355"},"observation_digest":"sha256:e52bfe9edb3ad0813990a1678d61f196b5800d1bbe85a8b2e12ac5f12a7fa5c9","observation_id":"e8780685-aa93-4a5c-a781-309bda748a27","resolution":{"observed_at":"2026-05-18T14:11:27.180535Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-15T06:32:42.880941+00:00","source":"crossref"},{"observed_at":"2026-08-15T06:32:39.529945+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"2024.345153","doi":"10.1109/mm.2024.3451532","metadata_source":"arxiv_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"UCIe: Standard for an Open Chiplet Ecosystem","venue":"IEEE Micro","work_id":"2d1530b3-0fa3-4a9d-b8fe-618c5304caa6","year":2024},"citing_paper":{"arxiv_id":"2509.18355","last_updated":"2026-04-07T17:04:22Z","snapshot_observed_at":"2026-08-07T01:18:14.379202Z","submitted_at":"2025-09-22T19:31:58Z","title":"Chiplet-Based RISC-V SoC with Modular AI Acceleration","version":5},"reference_index":18,"source":"pdf_text","source_observed_at":"2026-05-18T14:07:18.826032Z"},"links":{"citing_paper":"/paper/2509.18355"},"observation_digest":"sha256:97dfe4928d2e67f1a2fa8f984508e9d9eb83c75199f719949eeff04214b00f86","observation_id":"04ef1c6f-8271-4d5c-8350-67ecf6ce3dad","resolution":{"observed_at":"2026-05-18T14:11:27.184658Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-15T06:32:42.880941+00:00","source":"crossref"},{"observed_at":"2026-08-15T06:32:39.529945+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2508.13033","last_updated":"2025-08-18T15:51:48Z","snapshot_observed_at":"2026-08-14T09:42:48.256520Z","submitted_at":"2025-08-18T15:51:48Z","title":"AuthenTree: A Scalable MPC-Based Distributed Trust Architecture for Chiplet-based Heterogeneous Systems","version":1},"cited_work":{"arxiv_id":"2508.13033","doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":"2508.13033","snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"AuthenTree: A Scalable MPC-Based Distributed Trust Architecture for Chiplet-Based Heterogeneous Systems","venue":null,"work_id":"59db43fa-ae65-4f03-8de7-4a380480f48b","year":2025},"citing_paper":{"arxiv_id":"2509.18355","last_updated":"2026-04-07T17:04:22Z","snapshot_observed_at":"2026-08-07T01:18:14.379202Z","submitted_at":"2025-09-22T19:31:58Z","title":"Chiplet-Based RISC-V SoC with Modular AI Acceleration","version":5},"reference_index":19,"source":"pdf_text","source_observed_at":"2026-05-18T14:07:18.826032Z"},"links":{"cited_paper":"/paper/2508.13033","citing_paper":"/paper/2509.18355"},"observation_digest":"sha256:663683b089f0898078b1812cc6df9d1897039f75a1dd62fa0fbca285f1711ba6","observation_id":"11e835b0-3ad1-404a-9492-636a8faabcc9","resolution":{"observed_at":"2026-05-18T14:11:27.671253Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-15T06:32:42.880941+00:00","source":"crossref"},{"observed_at":"2026-08-15T06:32:39.529945+00:00","source":"retraction_watch"}],"state":"measured"}}],"paper":{"arxiv_id":"2509.18355","last_updated":"2026-04-07T17:04:22Z","latest_version":5,"primary_category":"cs.AR","snapshot_observed_at":"2026-08-07T01:18:14.379202Z","submitted_at":"2025-09-22T19:31:58Z","title":"Chiplet-Based RISC-V SoC with Modular AI Acceleration"},"reference_resolution":{"displayed":19,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":0,"verified_exact":5,"verified_fuzzy":14},"total_outbound_references":19},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-15T06:32:42.880941+00:00","source":"crossref"},{"observed_at":"2026-08-15T06:32:39.529945+00:00","source":"retraction_watch"}],"thesis":"As of 15 August 2026, this Paper Citation Record lists 19 of 19 outbound references and 0 inbound Pith citation observations for arXiv:2509.18355."}