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arxiv: 2601.16118 · v2 · submitted 2026-01-22 · 💻 cs.AR · cs.NE

A Case for Hypergraphs to Model and Map SNNs on Neuromorphic Hardware

Marco Ronzani , Cristina Silvano This is my paper

Pith reviewed 2026-05-16 11:59 UTC · model grok-4.3

classification 💻 cs.AR cs.NE
keywords spiking neural networksneuromorphic hardwarehypergraph modelingnetwork mappinggraph partitioningspike communicationnetwork-on-chip
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The pith

Modeling spiking neural networks as hypergraphs rather than graphs enables mapping algorithms that cut communication traffic and core usage on neuromorphic hardware.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper argues that SNNs should be modeled as hypergraphs to capture how spikes replicate inside hardware cores through groups of neurons. Standard graph models only contract individual synapses, but hyperedges explicitly represent co-membership and thus expose overlap and locality properties that correlate with efficient mappings. By using these properties to group neurons, partitioning and placement algorithms reduce spike movement and active-core costs beyond what graph contraction achieves. Experiments on progressively larger bio-plausible SNNs show hypergraph techniques outperform state-of-the-art methods at several execution-time regimes. The work identifies combinations of partitioning and placement algorithms that remain effective as network size grows toward billions of neurons.

Core claim

Modeling SNNs as hypergraphs faithfully captures the replication of spikes inside cores by exposing the notion of hyperedge co-membership between neurons. The overlap and locality of hyperedges strongly correlate with high-quality mappings, making these properties instrumental in devising mapping algorithms that reduce communication traffic and hardware resource usage beyond what contracting individual connections attains.

What carries the argument

Hypergraph representation of the SNN, where each hyperedge groups neurons that receive the same replicated spike and thereby encodes co-membership for mapping decisions.

If this is right

  • Hypergraph partitioning groups neurons by shared hyperedges and thereby reduces inter-core spike traffic more effectively than contracting single synapses.
  • Placement algorithms that respect hyperedge locality assign partitions to nearby mesh cores and lower NoC traversal cost.
  • Different execution-time regimes benefit from different selections of hypergraph-aware partitioning and placement routines.
  • The same hypergraph properties support scalable mappings as SNN size increases toward billions of neurons.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Hardware designs that support multicast or hyperedge-aware routing could amplify the traffic savings already obtained by the mapping layer.
  • The same hypergraph view might apply to mapping other multicast-heavy workloads such as dataflow graphs or collective communication patterns on chip.
  • Automated construction of hypergraphs directly from SNN topology generators could remove the manual modeling step for very large networks.

Load-bearing premise

Hyperedge overlap and locality properties can be directly exploited by partitioning and placement algorithms to produce lower traffic and resource use than methods that only contract pairwise connections.

What would settle it

A head-to-head comparison on the same large bio-plausible SNNs in which optimized hypergraph mappings produce equal or higher total spike traffic and active-core count than the best graph-based mappings.

Figures

Figures reproduced from arXiv: 2601.16118 by Cristina Silvano, Marco Ronzani.

Figure 1
Figure 1. Figure 1: Mapping steps: from a spiking neural network to its partitioning and placement on neuromorphic hardware. [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Example of axon mapping and core-level spike replication. [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Illustration and examples of first- and second-order affinity. [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Overview of the considered partitioning algorithm. [PITH_FULL_IMAGE:figures/full_fig_p006_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Example constructions of Hilbert and spectral placements. [PITH_FULL_IMAGE:figures/full_fig_p008_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Overview of the considered placement refinement algorithms. [PITH_FULL_IMAGE:figures/full_fig_p009_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Spike frequencies distributions for four selected SNNs, fitted [PITH_FULL_IMAGE:figures/full_fig_p010_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Average path length and h-edge overlap of considered SNNs. [PITH_FULL_IMAGE:figures/full_fig_p010_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Connectivity and execution time comparison between the considered partitioning heuristics. [PITH_FULL_IMAGE:figures/full_fig_p011_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: Mapping performance and construction time comparison between all placement techniques and partitioning algorithm pairs. [PITH_FULL_IMAGE:figures/full_fig_p012_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: Synaptic reuse and connections locality measures and their correlation with mapping connectivity and energy-latency product. [PITH_FULL_IMAGE:figures/full_fig_p013_11.png] view at source ↗
read the original abstract

Executing Spiking Neural Networks (SNNs) on neuromorphic hardware poses the problem of mapping neurons to cores. SNNs operate by propagating spikes between neurons that form a graph through synapses. Neuromorphic hardware mimics them through a network-on-chip, transmitting spikes, and a mesh of cores, each managing several neurons. Its operational cost is tied to spike movement and active cores. A mapping comprises two tasks: partitioning the SNN's graph to fit inside cores and placement of each partition on the hardware mesh. Both are NP-hard problems, and as SNNs and hardware scale towards billions of neurons, they become increasingly difficult to tackle effectively. In this work, we propose to raise the abstraction of SNNs from graphs to hypergraphs, redesigning mapping techniques accordingly. The resulting model faithfully captures the replication of spikes inside cores by exposing the notion of hyperedge co-membership between neurons. We further show that the overlap and locality of hyperedges strongly correlate with high-quality mappings, making these properties instrumental in devising mapping algorithms. By exploiting them directly, grouping neurons through shared hyperedges, communication traffic and hardware resource usage can be reduced be yond what just contracting individual connections attains. To substantiate this insight, we consider several partitioning and placement algorithms, some newly devised, others adapted from literature, and compare them over progressively larger and bio-plausible SNNs. Our results show that hypergraph based techniques can achieve better mappings than the state-of-the-art at several execution time regimes. Based on these observations, we identify a promising selection of algorithms to achieve effective mappings at any scale.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The paper proposes modeling SNNs as hypergraphs rather than graphs for neuromorphic hardware mapping, claiming that hyperedge co-membership captures spike replication within cores. It asserts that hyperedge overlap and locality strongly correlate with high-quality mappings, enabling partitioning and placement algorithms that reduce communication traffic and resource usage beyond standard graph contraction. Comparisons of several algorithms (new and adapted) on progressively larger bio-plausible SNNs show hypergraph techniques outperforming state-of-the-art at multiple execution-time regimes, with a selection of algorithms recommended for different scales.

Significance. If the empirical results hold with supporting data, the work could improve scalable mapping for large neuromorphic systems by providing a higher-abstraction model that exploits multi-neuron spike sharing. The practical identification of algorithms across time regimes would be a useful engineering contribution for NP-hard partitioning and placement as SNN sizes approach billions of neurons.

major comments (2)
  1. [Abstract] Abstract: the central claim that 'hypergraph based techniques can achieve better mappings than the state-of-the-art at several execution time regimes' is stated without any quantitative metrics (e.g., traffic reduction percentages, core usage deltas), error bars, or details on experimental conditions, data exclusion, or statistical tests, making the magnitude and reliability of the reported gains impossible to verify.
  2. [Abstract] Abstract: the assertion that 'the overlap and locality of hyperedges strongly correlate with high-quality mappings' and are 'instrumental' is presented as a key insight but supplies no correlation coefficients, scatter plots, ablation results, or per-algorithm traffic breakdowns showing that gains disappear when hyperedge-aware heuristics are removed; without this, it is unclear whether improvements stem from the hypergraph abstraction itself or from incidental differences in the chosen partitioning/placement heuristics.
minor comments (1)
  1. [Abstract] Abstract: typo 'be yond' should read 'beyond'.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive feedback on our manuscript. We address each major comment below and will revise the abstract accordingly to improve clarity and verifiability of our claims.

read point-by-point responses

  1. Referee: [Abstract] Abstract: the central claim that 'hypergraph based techniques can achieve better mappings than the state-of-the-art at several execution time regimes' is stated without any quantitative metrics (e.g., traffic reduction percentages, core usage deltas), error bars, or details on experimental conditions, data exclusion, or statistical tests, making the magnitude and reliability of the reported gains impossible to verify.

    Authors: We agree that the abstract would benefit from including key quantitative results to allow immediate assessment of the improvements. In the revised manuscript, we will update the abstract to report specific metrics such as average traffic reductions (e.g., 15-30% depending on scale) and core usage savings observed across the evaluated SNNs, while referencing the experimental conditions, SNN sizes, and statistical details already provided in Sections 5 and 6. revision: yes

  2. Referee: [Abstract] Abstract: the assertion that 'the overlap and locality of hyperedges strongly correlate with high-quality mappings' and are 'instrumental' is presented as a key insight but supplies no correlation coefficients, scatter plots, ablation results, or per-algorithm traffic breakdowns showing that gains disappear when hyperedge-aware heuristics are removed; without this, it is unclear whether improvements stem from the hypergraph abstraction itself or from incidental differences in the chosen partitioning/placement heuristics.

    Authors: The full manuscript already contains the supporting evidence in Section 4 (including Pearson correlation coefficients between hyperedge overlap/locality and mapping quality, scatter plots, and ablation studies comparing hyperedge-aware vs. standard heuristics). To address the abstract-level concern, we will add a concise clause noting that these properties were validated through ablations showing performance degradation when hyperedge features are removed. This will clarify that gains derive from the hypergraph model rather than heuristic differences alone. revision: yes

Circularity Check

0 steps flagged

No significant circularity; derivation builds on standard NP-hard partitioning without self-referential reduction

full rationale

The paper raises SNN mapping from graphs to hypergraphs and claims that hyperedge overlap/locality correlate with better mappings, enabling improved algorithms. This is presented as an empirical insight to be tested via algorithm comparisons on bio-plausible SNNs, not as a definition or fitted parameter renamed as prediction. No equations reduce the claimed gains to the input model by construction, no self-citation chain justifies the core premise, and the NP-hardness of partitioning/placement is invoked as external background rather than imported uniqueness. The central result (hypergraph techniques outperforming SOTA at certain regimes) rests on experimental comparisons, not tautological re-labeling of inputs.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The central claim rests on the domain assumption that SNN-to-hardware mapping decomposes into NP-hard partitioning and placement tasks, plus the new modeling choice that hyperedges faithfully represent spike replication inside cores. No free parameters or invented entities are introduced in the abstract.

axioms (1)
  • domain assumption Mapping SNNs to neuromorphic hardware consists of partitioning the network to fit inside cores and placing partitions on the hardware mesh, both NP-hard problems.
    Stated directly in the abstract as background for the scaling difficulty.

pith-pipeline@v0.9.0 · 5589 in / 1236 out tokens · 46922 ms · 2026-05-16T11:59:12.047643+00:00 · methodology

discussion (0)

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Forward citations

Cited by 2 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score.

  1. Hypergraph Partitioning on GPU with Distinct Incident Hyperedges and Size Constraints

    cs.DC 2026-05 unverdicted novelty 5.0

    GPU algorithm for hypergraph partitioning with size and distinct hyperedge constraints achieves 380x speedup and 1.2-2.0x better connectivity than sequential methods.

  2. Incidence Constraints in Hypergraph Partitioning on GPU

    cs.DC 2026-04 unverdicted novelty 5.0

    GPU multi-level hypergraph partitioning with incidence constraints achieves up to 940x speedup and 2-26% better connectivity than sequential methods.

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