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arxiv: 2605.20717 · v1 · pith:22CQ5NIEnew · submitted 2026-05-20 · 💻 cs.NE · cs.AR· cs.CV· eess.IV

E-ReCON: An Energy- and Resource-Efficient Precision-Configurable Sparse nvCIM Macro for Conventional and Spiking Neural Edge Inference

Ankit Kumar Tenwar , Mukul Lokhande , Santosh Kumar Vishvakarma This is my paper

Pith reviewed 2026-05-21 02:34 UTC · model grok-4.3

classification 💻 cs.NE cs.ARcs.CVeess.IV
keywords compute-in-memoryReRAMneural network inferencespiking neural networksenergy efficiencyedge AIsparse computationnon-volatile memory
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The pith

A 3T1R ReRAM bitcell with interleaved adder tree powers a sparse nvCIM macro reaching 419 TOPS/W for CNN and SNN edge inference.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper presents E-ReCON, a 16 Kb digital compute-in-memory macro built around a compact 3T1R ReRAM bitcell that performs reliable AND-based in-memory multiplication for both conventional CNNs and spiking neural networks. To cut accumulation overhead, the design introduces an interleaved 10T/28T adder tree that lowers transistor count by 37 percent and power by 28 percent versus a standard ripple-carry adder. Fabricated in 65 nm CMOS at 1.2 V, the macro records a minimum latency of 0.48 ns, throughput between 2.31 and 3.1 TOPS, and peak energy efficiency of 419 TOPS/W, while delivering 30-40 percent gains in latency and efficiency over earlier ADC-based ReRAM-CIM circuits. On standard benchmarks the macro maintains high accuracy even after 40 percent pruning and across multiple SNN weight and activation precisions.

Core claim

The 3T1R ReRAM bitcell enables direct in-memory AND multiplication that works for both dense CNN and sparse SNN workloads; paired with the interleaved adder tree, this yields a precision-configurable nvCIM macro whose measured performance reaches 0.48 ns minimum latency, 2.31-3.1 TOPS throughput, and 419 TOPS/W energy efficiency while preserving accuracy under full PVT and ReRAM variability.

What carries the argument

The 3T1R ReRAM bitcell that performs AND-based in-memory multiplication, together with the interleaved 10T/28T adder tree that reduces transistor count and power consumption.

If this is right

  • 40 percent weight pruning reduces MAC operations and cycle count while retaining nearly 99.8 percent of baseline accuracy.
  • The same bitcell supports 2A2W spike-weight multiplication for SNNs with accuracy close to floating-point baselines on CIFAR-10, CIFAR-100 and ImageNet-1K.
  • Reported latency and energy improvements of 30-40 percent versus prior ADC-based ReRAM-CIM designs translate directly into faster, lower-power edge inference.
  • The macro scales to IoT, biomedical sensing and neuromorphic workloads that require both CNN and SNN support in a single hardware block.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Lower energy per inference could extend operating time for battery-powered sensors or wearables that run continuous edge classification.
  • The precision-configurable feature may allow dynamic trade-offs between accuracy and power on the same chip when network conditions change.
  • Similar bitcell and adder-tree techniques could be ported to other emerging non-volatile memories to test whether the efficiency gains generalize beyond ReRAM.

Load-bearing premise

The 3T1R ReRAM bitcell continues to produce correct multiplication results under full process, voltage, temperature variations and ReRAM device variability.

What would settle it

A silicon measurement in which accuracy on LeNet-5, VGG-8 or ResNet-18 falls more than a few percent below the reported figures when the macro is operated across the full PVT corner set with real ReRAM variability.

Figures

Figures reproduced from arXiv: 2605.20717 by Ankit Kumar Tenwar, Mukul Lokhande, Santosh Kumar Vishvakarma.

Figure 1
Figure 1. Figure 1: (a) Schematic of the proposed CIM-enabled 3T1R [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Transient simulation waveforms of the proposed 3T1R [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Process, voltage, temperature, and ReRAM variability [PITH_FULL_IMAGE:figures/full_fig_p002_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: (a) Proposed energy- and resource-efficient ReRAM-based DCIM macro, (b) accumulation flow of the interleaved adder [PITH_FULL_IMAGE:figures/full_fig_p003_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Distribution of peripheral power consumption across [PITH_FULL_IMAGE:figures/full_fig_p004_5.png] view at source ↗
Figure 7
Figure 7. Figure 7: (a) Accuracy comparison of CNN models across dif [PITH_FULL_IMAGE:figures/full_fig_p005_7.png] view at source ↗
read the original abstract

This work presents E-ReCON, a 16 Kb energy and resource-efficient digital compute-in-memory (DCIM) macro based on a compact 3T1R ReRAM bitcell for edge-AI inference. The proposed bitcell occupies only 0.85 um^2 and supports reliable AND-based in-memory multiplication for both conventional convolutional neural network (CNN) and spiking neural network (SNN) workloads. To reduce accumulation overhead, a novel interleaved 10T/28T adder tree is introduced, reducing transistor count and power consumption by 37% and 28%, respectively, compared to a conventional 28T RCA-based design. Implemented in 65 nm CMOS at 1.2 V, the proposed macro achieves a minimum latency of 0.48 ns, throughput of 2.31-3.1 TOPS, and energy efficiency of up to 419 TOPS/W. When evaluated on LeNet-5, AlexNet, and CNN-8 models, the macro achieves 97.81%, 93.23%, and 96.51% accuracy on MNIST/A-Z, CIFAR10, and SVHN datasets, respectively. In addition, 40% pruning preserves nearly 99.8% of the original accuracy while reducing MAC operations and computation cycles. For SNN-oriented workloads, the proposed AND-type bitcell efficiently supports spike-weight multiplication with low switching activity, where the 2A2W configuration achieves accuracy close to the FP32 baseline across VGG-8, VGG-16, and ResNet-18 networks on CIFAR-10, CIFAR-100, and ImageNet-1K datasets. Compared to prior ADC-based ReRAM-CIM designs, the proposed architecture improves latency and energy efficiency by nearly 30-40% while maintaining robust operation under full PVT and ReRAM variability. Overall, E-ReCON provides a scalable, low-latency, and energy-efficient nvCIM platform for next-generation edge-AI, IoT, biomedical sensing, and neuromorphic applications.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The manuscript presents E-ReCON, a 16 Kb digital compute-in-memory (DCIM) macro in 65 nm CMOS based on a compact 3T1R ReRAM bitcell that supports AND-based in-memory multiplication for both CNN and SNN workloads. It introduces an interleaved 10T/28T adder tree to reduce transistor count and power, reports a minimum latency of 0.48 ns, throughput of 2.31-3.1 TOPS, and energy efficiency up to 419 TOPS/W at 1.2 V, along with accuracy results (97.81% on MNIST, 93.23% on CIFAR-10, etc.) for LeNet-5, AlexNet, VGG, and ResNet models. The work claims 30-40% improvements in latency and energy efficiency over prior ADC-based ReRAM-CIM designs while maintaining robustness under full PVT and ReRAM variability, plus support for 40% pruning with minimal accuracy loss and efficient spike-weight multiplication in SNN configurations.

Significance. If the performance metrics and robustness claims hold, the work would offer a concrete advance in compact, low-latency nvCIM hardware for edge inference, with notable strengths in its dual support for CNN and SNN workloads, the resource-efficient adder tree, and explicit benchmarking on standard models including ImageNet-1K. The reported transistor-count and power reductions (37% and 28%) and pruning results provide practical value for resource-constrained applications.

major comments (2)
  1. [Abstract] Abstract: The central claim that the 3T1R bitcell 'maintains robust operation under full PVT and ReRAM variability' while enabling the reported 0.48 ns latency, 419 TOPS/W efficiency, and 30-40% improvement over prior designs is load-bearing, yet the manuscript provides no Monte-Carlo simulations, corner-analysis results, or quantitative data on how resistance variation, temperature, or voltage shifts affect the effective multiply-accumulate value or accuracy.
  2. [Results] Results and evaluation sections: Accuracy figures (e.g., 97.81% on MNIST for LeNet-5, close-to-FP32 for 2A2W SNN on VGG-8) are stated without accompanying error bars, simulation-setup details, or explicit validation that post-hoc pruning and variability do not introduce bit errors in the AND-based multiplication.
minor comments (2)
  1. [Abstract] Abstract: The throughput range (2.31-3.1 TOPS) should specify the operating conditions or precision configurations that produce each value.
  2. [Related Work] Related work or comparison sections: Direct citations and tabulated metrics for the specific prior ADC-based ReRAM-CIM designs should be included to allow verification of the stated 30-40% latency and energy-efficiency gains.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the thorough and constructive review of our manuscript. We agree that strengthening the presentation of robustness data and accuracy evaluation details will improve the paper. We address each major comment below and will revise the manuscript accordingly.

read point-by-point responses

  1. Referee: [Abstract] Abstract: The central claim that the 3T1R bitcell 'maintains robust operation under full PVT and ReRAM variability' while enabling the reported 0.48 ns latency, 419 TOPS/W efficiency, and 30-40% improvement over prior designs is load-bearing, yet the manuscript provides no Monte-Carlo simulations, corner-analysis results, or quantitative data on how resistance variation, temperature, or voltage shifts affect the effective multiply-accumulate value or accuracy.

    Authors: We acknowledge that the manuscript does not present explicit Monte-Carlo or corner-analysis results quantifying the effects of resistance variation, temperature, and voltage on MAC values or accuracy. The robustness statement is grounded in the fully digital AND-based multiplication performed by the 3T1R bitcell, which produces a binary result and is therefore inherently less sensitive to analog-level variations than current-summing ADC-based ReRAM CIM designs. To directly address the concern, we will add Monte-Carlo simulation results and corner analyses in the revised manuscript, reporting the resulting variation in effective MAC outputs and end-to-end accuracy. revision: yes

  2. Referee: [Results] Results and evaluation sections: Accuracy figures (e.g., 97.81% on MNIST for LeNet-5, close-to-FP32 for 2A2W SNN on VGG-8) are stated without accompanying error bars, simulation-setup details, or explicit validation that post-hoc pruning and variability do not introduce bit errors in the AND-based multiplication.

    Authors: The reported accuracies were obtained from post-layout circuit simulations of the macro interfaced with the neural-network models. We will expand the results section to include (i) explicit simulation-setup details (tools, models, and flow), (ii) error bars derived from multiple Monte-Carlo runs that incorporate device and process variation, and (iii) a direct validation that the digital AND operation combined with the chosen bitcell sizing produces zero bit errors under the considered pruning ratios and variability conditions. These additions will be presented alongside the existing accuracy numbers. revision: yes

Circularity Check

0 steps flagged

No circularity: hardware implementation results are independent of any self-referential derivation

full rationale

The paper is a circuit design and benchmarking study reporting post-layout or measured metrics (0.48 ns latency, 419 TOPS/W, 97.81% MNIST accuracy) from a 65 nm CMOS implementation of the 3T1R bitcell and interleaved adder tree. These quantities are obtained directly from the physical design flow and workload execution rather than from any equation, fitted parameter, or model that reduces to its own inputs by construction. Comparisons to prior ADC-based ReRAM-CIM designs cite external literature numbers and do not rely on self-citation chains or uniqueness theorems imported from the authors' prior work. No mathematical derivation chain exists that could be circular; the central claims rest on circuit-level simulation/measurement and standard neural-network accuracy evaluation.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The design rests on standard CMOS process assumptions and the domain assumption that the ReRAM cells behave reliably for logic operations; no free parameters are fitted to data in the abstract, and no new physical entities are postulated.

axioms (1)
  • domain assumption ReRAM bitcell supports reliable AND-based in-memory multiplication under PVT and variability conditions
    Invoked to support the claimed robust operation and 30-40% improvement over prior designs.

pith-pipeline@v0.9.0 · 5944 in / 1406 out tokens · 95866 ms · 2026-05-21T02:34:38.279064+00:00 · methodology

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