{"record_type":"pith_number_record","schema_url":"https://pith.science/schemas/pith-number/v1.json","pith_number":"pith:2026:QBGDB2A6AK7FPF7KIAS2STBO2U","short_pith_number":"pith:QBGDB2A6","schema_version":"1.0","canonical_sha256":"804c30e81e02be5797ea4025a94c2ed52d10a62895101f13c7d000321dac2489","source":{"kind":"arxiv","id":"2604.04773","version":2},"attestation_state":"computed","paper":{"title":"A comparative study on power delivery aspects of compute-in/near-memory approaches using DRAM","license":"http://arxiv.org/licenses/nonexclusive-distrib/1.0/","headline":"DRAM-based compute-in-memory creates non-traditional current demands that require power delivery network aware designs for reliable scaling.","cross_cats":[],"primary_cat":"cs.AR","authors_text":"Lizy Kurian John, Siddhartha Raman Sundara Raman, Siyuan Ma","submitted_at":"2026-04-06T15:44:40Z","abstract_excerpt":"Compute-in-memory (PIM) mitigates the memory wall by performing computation within memory, reducing data movement and improving energy efficiency. DRAM-based PIM is particularly attractive due to its high density, mature manufacturing ecosystem, and compatibility with existing systems. Recent works exploit multiple levels of the DRAM hierarchy - including subarrays, banks, and 3D-stacked organizations - to enable in-memory computation using mechanisms such as multi-row activation, row-buffer operations, and near-bank compute units. However, these approaches introduce non-traditional current de"},"verification_status":{"content_addressed":true,"pith_receipt":true,"author_attested":false,"weak_author_claims":0,"strong_author_claims":0,"externally_anchored":false,"storage_verified":false,"citation_signatures":0,"replication_records":0,"graph_snapshot":true,"references_resolved":false,"formal_links_present":true},"canonical_record":{"source":{"id":"2604.04773","kind":"arxiv","version":2},"metadata":{"license":"http://arxiv.org/licenses/nonexclusive-distrib/1.0/","primary_cat":"cs.AR","submitted_at":"2026-04-06T15:44:40Z","cross_cats_sorted":[],"title_canon_sha256":"5f57972e543d74ecf1615739673ba35a30d375e9702fccc1ce85eec95c0abe4a","abstract_canon_sha256":"26aec8c1bcb3aa7da6011f50df0a858b7fe65183863e82e81afb3806f9d41d98"},"schema_version":"1.0"},"receipt":{"kind":"pith_receipt","key_id":"pith-v1-2026-05","algorithm":"ed25519","signed_at":"2026-05-26T02:04:10.287801Z","signature_b64":"AwOzR+qbr+fYSi8wTsjsTZUjkO6iJ5Kvn+QAQi4jCg87JmXdmVhUYQzjz6pQ+FSR3gMyVB1jJyj4K3HTTEMNDQ==","signed_message":"canonical_sha256_bytes","builder_version":"pith-number-builder-2026-05-17-v1","receipt_version":"0.3","canonical_sha256":"804c30e81e02be5797ea4025a94c2ed52d10a62895101f13c7d000321dac2489","last_reissued_at":"2026-05-26T02:04:10.287089Z","signature_status":"signed_v1","first_computed_at":"2026-05-26T02:04:10.287089Z","public_key_fingerprint":"8d4b5ee74e4693bcd1df2446408b0d54"},"graph_snapshot":{"paper":{"title":"A comparative study on power delivery aspects of compute-in/near-memory approaches using DRAM","license":"http://arxiv.org/licenses/nonexclusive-distrib/1.0/","headline":"DRAM-based compute-in-memory creates non-traditional current demands that require power delivery network aware designs for reliable scaling.","cross_cats":[],"primary_cat":"cs.AR","authors_text":"Lizy Kurian John, Siddhartha Raman Sundara Raman, Siyuan Ma","submitted_at":"2026-04-06T15:44:40Z","abstract_excerpt":"Compute-in-memory (PIM) mitigates the memory wall by performing computation within memory, reducing data movement and improving energy efficiency. DRAM-based PIM is particularly attractive due to its high density, mature manufacturing ecosystem, and compatibility with existing systems. Recent works exploit multiple levels of the DRAM hierarchy - including subarrays, banks, and 3D-stacked organizations - to enable in-memory computation using mechanisms such as multi-row activation, row-buffer operations, and near-bank compute units. However, these approaches introduce non-traditional current de"},"claims":{"count":4,"items":[{"kind":"strongest_claim","text":"This survey highlights the importance of PDN-aware design for scalable and reliable DRAM-based PIM systems and outlines key future research directions.","source":"verdict.strongest_claim","status":"machine_extracted","claim_id":"C1","attestation":"unclaimed"},{"kind":"weakest_assumption","text":"That the representative PIM techniques surveyed (multi-row activation, row-buffer operations, near-bank compute) sufficiently capture the full range of current-demand patterns that will appear in future DRAM-based PIM deployments.","source":"verdict.weakest_assumption","status":"machine_extracted","claim_id":"C2","attestation":"unclaimed"},{"kind":"one_line_summary","text":"The survey proposes a taxonomy for PIM-induced current behaviors in DRAM and analyzes how representative techniques create voltage droop and thermal issues, along with mitigation strategies using existing DRAM mechanisms.","source":"verdict.one_line_summary","status":"machine_extracted","claim_id":"C3","attestation":"unclaimed"},{"kind":"headline","text":"DRAM-based compute-in-memory creates non-traditional current demands that require power delivery network aware designs for reliable scaling.","source":"verdict.pith_extraction.headline","status":"machine_extracted","claim_id":"C4","attestation":"unclaimed"}],"snapshot_sha256":"1398e844179dfb19f9d0ce593c9f4e4dee594aff4beabe1bef3d5ad604829ba4"},"source":{"id":"2604.04773","kind":"arxiv","version":2},"verdict":{"id":"e9dec489-e647-4c42-9430-641a7f372ad7","model_set":{"reader":"grok-4.3"},"created_at":"2026-05-10T18:53:26.408278Z","strongest_claim":"This survey highlights the importance of PDN-aware design for scalable and reliable DRAM-based PIM systems and outlines key future research directions.","one_line_summary":"The survey proposes a taxonomy for PIM-induced current behaviors in DRAM and analyzes how representative techniques create voltage droop and thermal issues, along with mitigation strategies using existing DRAM mechanisms.","pipeline_version":"pith-pipeline@v0.9.0","weakest_assumption":"That the representative PIM techniques surveyed (multi-row activation, row-buffer operations, near-bank compute) sufficiently capture the full range of current-demand patterns that will appear in future DRAM-based PIM deployments.","pith_extraction_headline":"DRAM-based compute-in-memory creates non-traditional current demands that require power delivery network aware designs for reliable scaling."},"integrity":{"clean":true,"summary":{"advisory":0,"critical":0,"by_detector":{},"informational":0},"endpoint":"/pith/2604.04773/integrity.json","findings":[],"available":true,"detectors_run":[],"snapshot_sha256":"c28c3603d3b5d939e8dc4c7e95fa8dfce3d595e45f758748cecf8e644a296938"},"references":{"count":0,"sample":[],"resolved_work":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57","internal_anchors":0},"formal_canon":{"evidence_count":2,"snapshot_sha256":"af8010def7b396cfbfe4c6f8aa47fae50d1966f569d2cd765ec3a2c2f2f7a990"},"author_claims":{"count":0,"strong_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"builder_version":"pith-number-builder-2026-05-17-v1"},"aliases":[{"alias_kind":"arxiv","alias_value":"2604.04773","created_at":"2026-05-26T02:04:10.287191+00:00"},{"alias_kind":"arxiv_version","alias_value":"2604.04773v2","created_at":"2026-05-26T02:04:10.287191+00:00"},{"alias_kind":"doi","alias_value":"10.48550/arxiv.2604.04773","created_at":"2026-05-26T02:04:10.287191+00:00"},{"alias_kind":"pith_short_12","alias_value":"QBGDB2A6AK7F","created_at":"2026-05-26T02:04:10.287191+00:00"},{"alias_kind":"pith_short_16","alias_value":"QBGDB2A6AK7FPF7K","created_at":"2026-05-26T02:04:10.287191+00:00"},{"alias_kind":"pith_short_8","alias_value":"QBGDB2A6","created_at":"2026-05-26T02:04:10.287191+00:00"}],"events":[],"event_summary":{},"paper_claims":[],"inbound_citations":{"count":3,"internal_anchor_count":3,"sample":[{"citing_arxiv_id":"2605.21912","citing_title":"Emerging memory technologies at room/cryogenic temperature","ref_index":29,"is_internal_anchor":true},{"citing_arxiv_id":"2605.17158","citing_title":"A comprehensive study on ILP acceleration accounting for sparsity, area, energy, data movement using near-memory architecture","ref_index":55,"is_internal_anchor":true},{"citing_arxiv_id":"2605.19405","citing_title":"A complete discussion on fully reconfigurable, digital, scalable, graph and sparsity-aware near-memory accelerator for graph neural networks","ref_index":22,"is_internal_anchor":true}]},"formal_canon":{"evidence_count":2,"sample":[],"anchors":[]},"links":{"html":"https://pith.science/pith/QBGDB2A6AK7FPF7KIAS2STBO2U","json":"https://pith.science/pith/QBGDB2A6AK7FPF7KIAS2STBO2U.json","graph_json":"https://pith.science/api/pith-number/QBGDB2A6AK7FPF7KIAS2STBO2U/graph.json","events_json":"https://pith.science/api/pith-number/QBGDB2A6AK7FPF7KIAS2STBO2U/events.json","paper":"https://pith.science/paper/QBGDB2A6"},"agent_actions":{"view_html":"https://pith.science/pith/QBGDB2A6AK7FPF7KIAS2STBO2U","download_json":"https://pith.science/pith/QBGDB2A6AK7FPF7KIAS2STBO2U.json","view_paper":"https://pith.science/paper/QBGDB2A6","resolve_alias":"https://pith.science/api/pith-number/resolve?arxiv=2604.04773&json=true","fetch_graph":"https://pith.science/api/pith-number/QBGDB2A6AK7FPF7KIAS2STBO2U/graph.json","fetch_events":"https://pith.science/api/pith-number/QBGDB2A6AK7FPF7KIAS2STBO2U/events.json","actions":{"anchor_timestamp":"https://pith.science/pith/QBGDB2A6AK7FPF7KIAS2STBO2U/action/timestamp_anchor","attest_storage":"https://pith.science/pith/QBGDB2A6AK7FPF7KIAS2STBO2U/action/storage_attestation","attest_author":"https://pith.science/pith/QBGDB2A6AK7FPF7KIAS2STBO2U/action/author_attestation","sign_citation":"https://pith.science/pith/QBGDB2A6AK7FPF7KIAS2STBO2U/action/citation_signature","submit_replication":"https://pith.science/pith/QBGDB2A6AK7FPF7KIAS2STBO2U/action/replication_record"}},"created_at":"2026-05-26T02:04:10.287191+00:00","updated_at":"2026-05-26T02:04:10.287191+00:00"}