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arxiv 2106.14332 v1 pith:HUL6RWCL submitted 2021-06-27 cs.DC cond-mat.mtrl-scics.ARcs.CLcs.SE

A Case Study of LLVM-Based Analysis for Optimizing SIMD Code Generation

classification cs.DC cond-mat.mtrl-scics.ARcs.CLcs.SE
keywords codesimda64fxchangesinstructionllvmllvm-basedopenmp
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved
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This paper presents a methodology for using LLVM-based tools to tune the DCA++ (dynamical clusterapproximation) application that targets the new ARM A64FX processor. The goal is to describethe changes required for the new architecture and generate efficient single instruction/multiple data(SIMD) instructions that target the new Scalable Vector Extension instruction set. During manualtuning, the authors used the LLVM tools to improve code parallelization by using OpenMP SIMD,refactored the code and applied transformation that enabled SIMD optimizations, and ensured thatthe correct libraries were used to achieve optimal performance. By applying these code changes, codespeed was increased by 1.98X and 78 GFlops were achieved on the A64FX processor. The authorsaim to automatize parts of the efforts in the OpenMP Advisor tool, which is built on top of existingand newly introduced LLVM tooling.

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