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A 50-spin surface acoustic wave Ising machine

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abstract

Time-multiplexed Spinwave Ising Machines (SWIMs) have unveiled a route towards miniaturized, low-cost, and low-power solvers of combinatorial optimization problems. While the number of supported spins is limited by the nonlinearity of the spinwave dispersion, other collective excitations, such as surface acoustic waves (SAWs), offer a linear dispersion. Here, we demonstrate an all-to-all, fully FPGA reprogrammable, 50-spin surface acoustic wave-based Ising machine (SAWIM), using a 50-mm-long Lithium Niobate SAW delay line, off-the-shelf microwave components, and a low-cost FPGA. The SAWIM can solve any 50-spin MAX-CUT problem, with arbitrary coupling matrices, in less than 340 $\mu$s consuming only 0.62 mJ, corresponding to close to 3000 solutions per second and a figure of merit of 1610 solutions/W/s. We compare the SAWIM computational results with those of a 100-spin optical Coherent Ising machine and find a higher probability of solution. Moreover, we demonstrate that there is an optimum overall coupling strength between spins at which the probability of the exact solution reaches 100%. The SAWIM illustrates the general merits of solid state wave-based time-multiplexed Ising machines in the microwave domain as versatile platforms for commercially feasible high-performance solvers of combinatorial optimization problems.

years

2025 1

verdicts

CONDITIONAL 1

representative citing papers

Extended-variable probabilistic computing with p-dits

physics.app-ph · 2025-05-30 · conditional · novelty 6.0

A new probabilistic computing primitive, the p-dit, extends binary p-bits to multi-dimensional and integer states and is demonstrated in custom ASIC and FPGA hardware with large speedups on optimization benchmarks.

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  • Extended-variable probabilistic computing with p-dits physics.app-ph · 2025-05-30 · conditional · none · ref 16 · internal anchor

    A new probabilistic computing primitive, the p-dit, extends binary p-bits to multi-dimensional and integer states and is demonstrated in custom ASIC and FPGA hardware with large speedups on optimization benchmarks.