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Testing the limits of ITkPixV2: the ATLAS inner tracker pixel detector readout chip

T0 review · 3 major / 4 minor · reviewed 2026-08-08 · deepseek-v4-flash

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Pith's one-line read The ATLAS upgrade pixel readout chip ITkPixV2 operates within design limits at full trigger rate, with hit-rate capacity estimated at 3.34–3.55 GHz/cm².

desk verdict A solid engineering validation of the ATLAS ITk pixel chip, with one caveat that deserves attention: the final 3 GHz/cm2 margin relies on simulated multi-pixel encoding scaling. read the letter →

arxiv 2502.05097 v3 pith:4MAYWEUC submitted 2025-02-07 physics.ins-det hep-ex

Luc Le Pottier , Timon Heim , Maurice Garcia-Sciveres This is my paper · ORCID
classification physics.ins-dethep-ex
keywords trackingdetectorsdetectorfront-endelectronicsHL-LHCupgradephysicsITkPixV2pixelreadoutchipdigitalcurrentbandwidthlimithitrate
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

ITkPixV2 is the final production readout chip for the ATLAS inner tracker upgrade, which must handle 7.5 times higher hit rates and 10 times higher trigger rates than the current detector. This paper reports the first measurements of the chip operated at the full design limits: 1 MHz trigger rate, 12.5 μs latency, and increasing hit rate driven by an X-ray tube. The central result is that the chip's digital current rises linearly with hit rate until output bandwidth saturates at about 1 Gbps with one lane enabled and 4.5 Gbps with four lanes, both inside the 80% safety margin. Correcting for buffer-overflow losses and using the cluster sizes expected in the real detector (2–4 pixels), the estimated sustainable hit rate is 3.34–3.55 GHz/cm², comfortably above the 3 GHz/cm² requirement.

What carries the argument

The central measurement is the activity-induced digital current of the chip as a function of increasing hit rate, taken with a single ITkPixV2 module irradiated by an uncollimated silver-target X-ray tube. The chip is operated at the full design trigger rate of 1 MHz and trigger latency of 12.5 μs while the tube current is swept from 0 to 200 μA. The argument relies on two calibrations: a linear fit of true hit rate versus tube current (slope about 50.65 GHz/cm² per mA) used to correct for buffer-overflow losses, and the measured bandwidth encoding scaling of 1.819 Gbps per GHz/cm², compared against the RD53 compression simulation for cluster sizes 1 through 4. The chip's four output lanes, each rated at 1.28 Gbps, define the bandwidth limits probed in the 1-lane and 4-lane configurations.

What would settle it

Measure the X-ray flux independently at high tube currents (for example with a calibrated photodiode or by comparing with a source whose flux is known) and repeat the current-versus-hit-rate scan; if the corrected hit rates diverge from this independent calibration above ~1 GHz/cm², the claimed 3.34–3.55 GHz/cm² rate limit and the 80%-margin conclusion would need revision.

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Extended reading notes

Core claim

The paper establishes that ITkPixV2, when driven at the target maximum trigger rate of 1 MHz and trigger latency of 12.5 μs, shows a linear increase in digital current with hit rate up to its output bandwidth limits: approximately 1 Gbps with one readout lane and 4.5 Gbps with four lanes. Both limits sit within the 80% safety factor chosen in the design. The measured encoding scaling of $1.819 \pm 0.005$ Gbps per GHz/cm² matches the simulated value of 1.796, and applying the simulated cluster sizes of 2–4 expected for ITk gives an estimated rate limit of 3.34–3.55 GHz/cm², exceeding the 3 GHz/cm² design requirement. The slope of digital current versus hit rate before the bandwidth knee is about 45 mA per GHz/cm², below the simulated 64 mA per GHz/cm², with consistent behavior in one- and four-lane configurations. After the bandwidth limit, current continues to rise because pixels still count hit pulses, and this post-limit slope is identical for both lane configurations.

Load-bearing premise

The correction for buffer-overflow hit loss assumes that the true hit rate is exactly linear in X-ray tube current all the way to the highest currents, even though the calibration fit is only anchored below 1 GHz/cm² and then extrapolated to every data point; if X-ray output saturates or some loss is not due to buffer overflow, the corrected rates, bandwidth limits, and current slopes all shift.

Editorial extensions

If this is right

  • If the central claim holds, the ITk pixel detector can rely on ITkPixV2 to handle the HL-LHC hit rate of 3 GHz/cm² with the expected 2–4 pixel cluster sizes, since the estimated limit is 3.34–3.55 GHz/cm².
  • The measured bandwidth limits of roughly 1 Gbps (1 lane) and 4.5 Gbps (4 lanes) stay below the theoretical 1.28 and 5.12 Gbps per chip, leaving the intended 20% safety margin intact for data-encoding overhead.
  • Because the digital current slope (about 45 mA per GHz/cm²) is below the simulated 64 mA per GHz/cm², the chip's power-per-area budget in the HL-LHC environment should be met, simplifying cooling and serial-powering design.
  • The match between measured and simulated encoding scaling validates the RD53 compression model for system-level data-rate budgeting across the ITk detector's 20:1 range of per-chip data rates.
  • Above the bandwidth limit, the identical current slope for 1-lane and 4-lane configurations means the extra current is drawn by the pixel matrix front-ends, not the readout lanes, which is useful for isolating power contributions in future system designs.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • A testable extension would be to repeat the measurement with a calibrated flux monitor to replace the linear-extrapolation correction, which would tighten the quoted rate-limit uncertainties or expose a saturation effect.
  • The same RD53C framework is shared with the CMS CROC-V2 chip; if a comparable limit test were run on CROC-V2, it would show whether the power and bandwidth behavior is framework-wide or ITkPixV2-specific.
  • The post-saturation current slope being independent of lane count suggests the current is set by per-pixel ToT counting; varying the front-end feedback current (which changes ToT) would test this and could inform power-reduction firmware.
  • If real ITk cluster sizes end up larger than 2–4, the effective rate limit would be even higher, so the 3 GHz/cm² requirement would be met with more margin; conversely, any unexpected 1-pixel-dominated region would lower it.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 4 minor

Summary. The paper reports measurements of the ITkPixV2 pixel readout chip, the final production ASIC for the ATLAS ITk upgrade, operated at the target maximum trigger rate of 1 MHz and trigger latency of 12.5 us. Using an X-ray tube to generate hit rates, the authors measure the digital current as a function of hit rate for both 1-lane and 4-lane readout configurations. They observe a linear increase in current until the bandwidth limit is reached (about 1 Gbps for 1 lane and 4.5 Gbps for 4 lanes) and then a continued increase in pixel-matrix current. A correction factor, based on a linear fit below 1 GHz/cm2 and extrapolated to higher rates, is used to convert measured rates to 'true' hit and data rates. By dividing the measured 4-lane bandwidth limit by the simulated encoding scaling for cluster sizes 2-4 from Ref. [11], the authors estimate a rate limit of 3.34-3.55 GHz/cm2 for ITk-like cluster sizes and conclude that the chip meets the 3 GHz/cm2 design requirement.

Significance. This is the first reported operation of ITkPixV2 at full design specifications for hit rate, trigger rate, and latency, providing valuable data for the ITk upgrade. The direct measurements of bandwidth limits (1 Gbps and 4.5 Gbps) and the activity-induced digital current are useful engineering results, and the empirical validation of the single-pixel encoding efficiency (1.819 measured vs 1.796 simulated Gbps/(GHz/cm2), a 1.3% agreement) is a strong point. However, the central claim that the chip satisfies the 3 GHz/cm2 hit-rate requirement for realistic cluster sizes rests on an unvalidated multi-pixel encoding simulation, and the rate-correction procedure relies on an extrapolated linearity assumption. If the multi-pixel encoding scaling differs from the simulation by about 11%, the design margin would vanish. These issues are addressable but currently limit the strength of the conclusions.

major comments (3)
  1. [Section 4, final paragraph] The estimate of 3.34-3.55 GHz/cm2 for ITk-like cluster sizes is obtained by dividing the measured 4-lane bandwidth limit (4.5 Gbps) by the simulated encoding scaling for clusters of size 2-4 from Ref. [11]. The only empirical validation of the encoding simulation is for single-pixel clusters, where the measured 1.819 +/- 0.005 Gbps/(GHz/cm2) matches the simulated 1.796 within 1.3%. That agreement does not constrain the compression efficiency for multi-pixel clusters, because address correlation and neighbor encoding change the data volume. If the actual scaling for clusters 2-4 were about 1.5 Gbps/(GHz/cm2) rather than the simulated 1.27-1.35, the rate limit would fall to approximately 3.0 GHz/cm2, removing the claimed margin. The paper should either validate the multi-pixel encoding simulation against data (for example, by measuring cluster-size-dependent bandwidth on the chip with a pattern generator or a beam test) or clearly present the 3.34-3.55 GHz/cm2 figure as an estimate that depends on the unvalidated simulation, not as a measured result.
  2. [Section 4, Figure 3 and correction factor] The correction for buffer-overflow hit loss assumes that the true hit rate is linear in X-ray tube current across the entire measured range. The fit used to derive the factor 50.65 GHz/cm2/mA is performed only for hit rates below 1 GHz/cm2, then extrapolated to all data points. If the X-ray tube output saturates at high current, or if some of the measured loss is not due to buffer overflow, every corrected hit rate and digital-current slope will shift, including the quoted values of 2.45 GHz/cm2 at the 4-lane knee. The paper should provide evidence for the linearity assumption (for example, a second measurement method, a discussion of the tube's linearity specification, or an uncertainty band from the extrapolation) or at least state explicitly that the correction is an extrapolation and quantify its sensitivity.
  3. [Section 4, Figure 4 and current-slope comparison] The digital-current slopes are reported as 'about 45 mA/(GHz/cm2)' with no uncertainty, and the comparison to the simulated value of 64 mA/(GHz/cm2) is made without error bars. The power supply accuracy is stated as +/- (0.1% + 2 mA), and the fit itself will have statistical uncertainty; neither is propagated. Given that the paper's quantitative conclusions depend on the magnitude and slope of the current increase, the authors should report fit uncertainties and, where possible, systematic uncertainties from the rate correction and the power measurement.
minor comments (4)
  1. [Abstract] The luminosity unit is given as '5 x 10^34 cm^-1 s^-1' in the abstract; this should be cm^-2 s^-1.
  2. [Section 4, paragraph 1] The correction factor is described only as 'fit factors were applied,' without specifying the fitting range, the number of points, or the functional form beyond 'linear.' A sentence with these details would make the procedure reproducible.
  3. [Section 4, bandwidth limit comparison] The statement that both 1 Gbps and 4.5 Gbps are 'within the 80% safety factor' is ambiguous: 1 Gbps is about 78% of the 1.28 Gbps per-lane maximum, while 4.5 Gbps is about 88% of the 5.12 Gbps total. The intended reference for the 80% safety factor should be clarified.
  4. [Experimental setup] The paper uses a single module and does not discuss run-to-run reproducibility or variations among chips. A brief note on whether the observed trends are single-chip-specific would help the reader gauge generality.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: main results are direct measurements; the self-cited encoding simulation is used only for a secondary extrapolation and is partially validated against measured single-cluster data.

full rationale

The paper's central results—digital current versus hit rate, the 1 Gbps and 4.5 Gbps bandwidth limits, and the current slope of ~45 mA/(GHz/cm2)—are direct measurements of the chip, not derived from the quantities they are used to support. The buffer-overflow correction fits the low-rate hit-rate-versus-tube-current response and extrapolates it to recover "true" hit rates; this is a standard calibration assumption (linear X-ray yield) and does not define any claimed prediction in terms of itself. The only load-bearing external input is the RD53B encoding scaling from Ref. [11], which is co-authored by two of the present authors. However, the paper does not fit its own data to that simulation; instead it validates the single-cluster encoding scaling empirically (1.819 ± 0.005 measured vs 1.796 Gbps/(GHz/cm2) simulated) and then uses the simulated multi-cluster scaling to convert the directly measured 4-lane bandwidth limit into an estimated rate limit of 3.34–3.55 GHz/cm2. This is a model-based extrapolation and its multi-cluster part is not independently validated, which is a correctness/robustness limitation rather than a circular step: the estimated rate limit is not equal to any input by construction, and the main bandwidth and current measurements stand independently of it. No self-definitional, fitted-input-as-prediction, or uniqueness-imported-from-authors pattern is present.

Assumptions & free parameters 3 free parameters · 4 assumptions · 0 invented entities

The central numbers are measured fits, not theory predictions. The main burden is the assumption that X-ray hit rate scales linearly with tube current across the full range, and that a single module represents production behavior.

free parameters (3)
  • X-ray hit-rate conversion slope = 50.65 GHz/cm2 per mA
    Linear fit to low-rate data is extrapolated to correct all high-rate hit and bandwidth values for buffer overflow losses.
  • Digital current slope = ~45 mA/(GHz/cm2)
    Fitted slope of digital current vs corrected hit rate before the bandwidth limit, quoted without an uncertainty.
  • Encoding rate scaling = 1.819 +/- 0.005 Gbps/(GHz/cm2)
    Measured ratio between output bit rate and X-ray hit rate, compared with simulated 1.796 from ref [11].
assumptions (4)
  • domain assumption X-ray tube flux is proportional to tube current over the full 0 to 200 uA operating range.
    The hit-loss correction extrapolates a linear fit made below 1 GHz/cm2 to the full range. Invoked in Section 4, first paragraph.
  • domain assumption The RD53B encoding simulation of ref [11] accurately predicts encoding-rate scaling for cluster sizes 2-4.
    Used to convert measured cluster-size-1 encoding scaling into the operational rate limit 3.34-3.55 GHz/cm2. Invoked in Section 4, final paragraph.
  • domain assumption Activity-induced digital current is accurately represented by the bench power supply current readout at 1.6 V.
    Power supply accuracy is +/- (0.1% + 2 mA), but no error propagation is shown. Invoked in Section 3.
  • domain assumption Results from a single module with a 100 um sensor are representative of production ITkPixV2 modules.
    All measurements use one chip with some dead edge pixels due to bump bonding. Invoked throughout Sections 3 and 4.

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Cite this review

Pith. "Pith review of Testing the limits of ITkPixV2: the ATLAS inner tracker pixel detector readout chip." pith.science (2026). https://pith.science/paper/4MAYWEUC

@misc{pith2026250205097,
  author       = {Pith},
  title        = {Pith review of: Testing the limits of ITkPixV2: the ATLAS inner tracker pixel detector readout chip},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/4MAYWEUC}},
  note         = {Machine review of arXiv:2502.05097}
}
abstract

The ITkPixV2 chip is the final production readout chip for the ATLAS Phase 2 Inner Tracker (ITk) upgrade at the upcoming High-Luminosity LHC (HL-LHC). Due to the extraordinarily high peak luminosity at the HL-LHC of $5 \times 10^{34}$ cm$^{-1}$s$^{-1}$, ITkPixV2 must meet significant increases in nearly all design requirements compared to the current ATLAS Inner Detector (ID), including a 10x increase in trigger rate, a 7.5x increase in hit rate, a 3x increase in radiation tolerance, and a 12.5x decrease in pixel current draw per unit area, all while maintaining a similar power per unit area as present pixel detectors. Here we present the first measurements of the ITkPixV2 chip operated at the limits of the full chip design requirements, including in particular a measurement of the activity-induced current of the chip as a function of increasing hit rate.

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Forward citations

Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. Simulation of irradiated hybrid planar pixels modules at fluences expected at HL-LHC

    hep-ex 2025-06 conditional novelty 4.0 of 10

    A TCAD plus Allpix2 simulation chain, averaging the CMS and Mandic trapping models, reproduces irradiated pixel charge collection and predicts ITk planar modules remain fully efficient at HL-LHC fluences.

Reference graph

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