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The EPFL Logic Synthesis Libraries

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arxiv 1805.05121 v3 pith:FMVQV67G submitted 2018-05-14 cs.LO cs.MS

Mathias Soeken , Heinz Riener , Winston Haaswijk , Eleonora Testa , Bruno Schmitt , Giulia Meuli , Fereshte Mozafari , Siang-Yun Lee
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Alessandro Tempia Calvino Dewmini Sudara Marakkalage Giovanni De Micheli
This is my paper · ORCID
classification cs.LOcs.MS
keywords librarieslogicsynthesiswellapplicationsusedclassicalcollection
verification ladder T0 review T1 audit T2 compute T3 formal
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We present a collection of modular open source C++ libraries for the development of logic synthesis applications. These libraries can be used to develop applications for the design of classical and emerging technologies, as well as for the implementation of quantum compilers. All libraries are well documented and well tested. Furthermore, being header-only, the libraries can be readily used as core components in complex logic synthesis systems.

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Cited by 5 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

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    quant-ph 2025-01 conditional novelty 7.0 of 10

    ASDF compiles the basis-oriented Qwerty language into OpenQASM 3 and QIR, with resource estimates comparable to circuits produced by Qiskit, Quipper, and Q# for five benchmark algorithms.

  2. Miter-Aware LUT Mapping: Aligning Structure and Solvability for Efficient Logic Equivalence Checking

    cs.AR 2026-07 conditional novelty 6.0 of 10

    Joint LUT mapping of golden and implementation circuits, combined with Gaussian-guided XOR modeling and solver-oriented LUT selection, reduces SAT-based logic equivalence checking runtime by up to 92.1%.

  3. Cut Tracing with E-Graphs for Boolean FHE Circuit Synthesis

    cs.CR 2025-06 conditional novelty 6.0 of 10

    A technique called cut tracing records the rewrites of MC- and MD-reducing logic synthesis flows in an e-graph, and extracts an FHE circuit traded off between multiplicative depth and multiplicative complexity to lowe...

  4. Explicit Sign-Magnitude Encoders Enable Power-Efficient Multipliers

    cs.NE 2025-07 conditional novelty 5.0 of 10

    Explicitly converting two's complement inputs to sign-magnitude before 4-bit multiplication reduces switching activity by 12.9% (logic-equivalent) to 33% (reduced range) under zero-centered input distributions.

  5. Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper

    cs.AR 2025-07 reject novelty 5.0 of 10

    Fusing an ASIC mapper with a reinforcement-learning-chosen partial cell library improves FPGA LUT count and area-delay product by about 9% on average.

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