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REVIEW 3 major objections 6 minor 48 references

Timing and resource-aware mapping of quantum circuits to superconducting processors

T0 review · 3 major / 6 minor · reviewed 2026-08-14 · deepseek-v4-flash

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Pith's one-line read Qmap maps quantum circuits onto the Surface-17 processor with timing and resource awareness, reducing latency overhead by up to 47.3% and operation overhead by up to 28.6% compared with an operation-count-minimizing mapper.

desk verdict Useful and practical NISQ compilation paper with a real contribution, but the MOVE precondition is unaddressed in the writeup and the evaluation is not yet independently reproducible. read the letter →

arxiv 1908.04226 v2 pith:QQCMKY5T submitted 2019-08-12 quant-ph

Lingling Lao , Hans van Someren , Imran Ashraf , Carmen G. Almudever This is my paper · ORCID
classification quant-ph
keywords quantumcircuitmappingtiming-awarecompilationresource-constrainedschedulingclassicalcontrolconstraintssuperconductingqubitprocessorroutingSurface-17NISQ
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper argues that mapping a quantum circuit onto a superconducting processor should optimize for execution time under the real hardware constraints, not merely for the number of added gates. It presents Qmap, a mapper that treats shared classical control electronics as resource constraints in a list scheduler, and routes qubits by choosing, among equal-length shortest-path movement sets, the one that least extends the scheduled latency. On 56 benchmarks mapped to the Surface-17 processor, Qmap produces circuits whose latency overhead is up to 47.3% smaller and whose operation overhead is up to 28.6% smaller than those of a prior mapper that minimizes operation count and schedules later, with average reductions of 22% and 3.0%. This matters because NISQ processors have short coherence times, so shorter latency can directly improve the chance that a computation succeeds.

What carries the argument

The central mechanism is a resource-constrained list scheduler built on a weighted Quantum Operation Dependency Graph (QODG), in which every gate is a node and every dependency edge carries the duration of the preceding gate. A machine state S records, for each resource in four configuration tables—Tg1 for single-qubit drive sources, Tgm for measurement feedlines, Tg2f for CZ-versus-CZ concurrency, and Tg2d for qubits that must be detuned during a CZ—the occupying operation and the half-open cycle interval [t0, t1) during which it is busy. A gate can be issued at cycle t only if all its resources are free for its full duration; among available gates the scheduler picks the one with the longest remaining path to the sink. The router reuses this scheduler in a look-back mode, generating all shortest-path movement sets, scheduling each against the already mapped prefix, and keeping the set that minimally extends latency.

What would settle it

Execute a Qmap-generated schedule for a benchmark such as decod24bdd on an actual Surface-17 device and compare the measured output distribution with the ideal simulated one; a missed control constraint—for example, two same-frequency single-qubit gates issued in the same cycle or a CZ executed while a qubit that should be parked is busy—would produce a characteristic error signature on the affected qubits.

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Extended reading notes

Core claim

The paper's central claim is that classical control restrictions—shared microwave sources for single-qubit gates, shared measurement feedlines, and frequency-detuning exclusions during two-qubit gates—can be encoded as resource occupations in a conventional list scheduler, making timing- and resource-aware mapping practical at polynomial scheduling cost. Qmap schedules gates using real durations (single-qubit rotations and measurement take 1 and 15 cycles, CZ gates take 2 cycles) and its router evaluates all shortest-path movement sets for each non-nearest-neighbor gate, interleaves each candidate set with already mapped gates using the same scheduler, and selects the set that minimally extends total latency. Against a MinPath mapper that randomly picks a minimum-operation movement set and only applies timing and control constraints in a later scheduling pass, Qmap achieves lower or equal latency overhead for 96.4% of benchmarks and lower or equal gate overhead for 87.5%, with the largest latency improvement at 47.3% and the largest gate-count improvement at 28.6%. The paper also shows that using MOVE operations (two CNOTs, requiring a destination qubit in |0⟩) instead of SWAPs (three CNOTs) cuts gate overhead by up to 38.9% and latency by up to 29%.

Load-bearing premise

The load-bearing premise is that the configuration tables for Surface-17's classical control—shared single-qubit drive sources, measurement feedlines, and two-qubit detuning exclusions—completely capture the hardware's real restrictions; if a real constraint is missing, the scheduled circuits may not execute correctly.

Editorial extensions

If this is right

  • Qmap's output circuits carry precise per-cycle timing and already respect classical-control restrictions, so the separate pulse-level scheduling pass that earlier mappers require can be reduced or eliminated.
  • Optimizing for gate count alone leaves substantial execution time on the table: Qmap matched or beat the operation-count-minimizing mapper on latency for 96.4% of the benchmarks, and the largest gap was 47.3%.
  • MOVE operations are preferable to SWAPs whenever a qubit known to be in |0⟩ is available, reducing the number of gates by up to 38.9% and latency by up to 29% in the paper's tests.
  • The scheduler's worst-case complexity is polynomial—O(min(g, n)·(n+|R|)·g) in the number of gates, qubits, and resources—so timing-aware mapping is feasible for large gate counts, even though the routing heuristic still scales sub-exponentially with qubit count.
  • Because all hardware characteristics are read from a configuration file, the same mapper can be retargeted to other processors by replacing the topology, duration, and resource tables.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The same resource-table formulation could absorb noise information, such as gate error rates and decoherence decay, as additional costs; if it did, latency-minimizing schedules might also become success-probability-minimizing schedules, which the paper did not test.
  • The 47.3% latency gap was measured on a 17-qubit processor; as processors grow, shared-control constraints become denser, so timing-aware routing is likely to matter even more relative to operation-count minimization.
  • A natural stress test is to map the same benchmarks onto other processors with different shared-control arrangements, using only the configuration file, to see whether the resource-table model transfers and how much latency it recovers.
  • The MOVE-versus-SWAP savings suggest a hardware-design consequence the paper leaves implicit: placing dedicated |0⟩ ancilla storage near frequently interacting qubits could reduce mapping overhead further.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 6 minor

Summary. This paper presents Qmap, a mapping/compilation framework that transforms hardware-agnostic quantum circuits into executable circuits for the 17-qubit Surface-17 superconducting processor, respecting the primitive gate set, gate durations, qubit connectivity, and restrictions from shared classical control electronics (AWGs for single-qubit gates, feedlines for measurement, and frequency-detuning rules for CZ gates). The mapper combines an ILP-based initial placement, a resource-constrained list scheduler (Algorithm 1) that models classical-control limits as resource conflicts, a routing heuristic (Algorithms 2-3) that evaluates multiple shortest-path SWAP/MOVE movement sets and selects the one that minimally extends an ASAP partial schedule, and a global ALAP rescheduling pass. Using 56 benchmarks from RevLib and QLib, the authors compare Qmap with two self-implemented baselines, Trivial and MinPath, and report that Qmap reduces latency overhead by up to 47.3% and gate-count overhead by up to 28.6% relative to MinPath, with average reductions of 22% and 3.0%, at the cost of substantially longer compilation times.

Significance. Assuming the reported results hold, this is a useful contribution to the quantum-compilation literature: it is among the first mappers to fold classical control-electronics restrictions (shared AWGs, shared feedlines, CZ detuning rules) directly into a polynomial-complexity list scheduler, and the latency-aware movement-set selection is a clean, well-motivated improvement over operation-count-only routing. The evaluation uses external benchmark circuits (RevLib and QLib), and no parameters are fitted to the reported outcomes, so the comparison is not circular; the pseudocode for the three algorithms is clear, and the authors are honest about limitations (sub-exponential routing complexity, qubit counts below 20, deferred external comparison). The strength of the central latency-improvement claim, however, is conditional on the two load-bearing points in the major comments: the |0>-precondition for MOVE must be demonstrably enforced, and the randomized self-implemented baseline must be reported with variance and, ideally, anchored by an external comparison.

major comments (3)
  1. [§II.A, §III.B, §IV.C] Section II.A states that a MOVE operation 'requires that the destination qubit where the quantum state needs to be moved to, is in the |0⟩ state.' This precondition is a quantum-state condition, yet none of the three algorithms in Sections III-IV tracks it: the machine state S in Algorithm 1 (Section III.B) covers only the classical resources in Tg1, Tgm, Tg2f, and Tg2d, and the routing state in Algorithms 2-3 (Section IV.C) is the VP-map plus the QODG, with no predicate recording which physical qubits are currently in |0>. The manuscript also states no invariant of the form 'MOVE destinations are chosen only among physical qubits not currently holding a computational state.' Because Table IV reports large MOVE counts for both MinPath and Qmap (e.g., hundreds of MOVEs for several benchmarks), the reader has no basis to conclude that the generated eQASM circuits are equivalent to the input circuits: a MOVE into a data qubit, or into an ancilla that is not guaranteed to be |0>, entangles rather than transfers the state. Since the claimed gate-overhead reductions rely in part on MOVE usage (Sections I and V.E), this is load-bearing for the central claim. I ask the authors to (i) state the precise invariant under which MOVE destinations are known to be |0>, (ii) show where and how Algorithms 2 and 3 enforce it during movement-set enumeration, scheduling, and VP-map updates, and (iii) verify, preferably by instrumenting the compiler or checking the output eQASM for the 56 benchmarks, that every MOVE reported in Table IV satisfies the precondition.
  2. [§V.B, §V.C] Section V.C reports only the minimum of five mapping runs for each benchmark, and Section V.B describes the MinPath router as randomly selecting one movement set along a shortest path; since MinPath is therefore a random baseline, the reported 47.3% (latency) and 28.6% (gates) reductions are comparisons against the best-of-five outcome of a randomized procedure, with no measure of spread, so the reader cannot tell whether these reductions exceed run-to-run variation of the baseline. The paper should report the mean and standard deviation (or all five runs) per benchmark and per mapper, and should state the direction of the bias: because Qmap selects the latency-minimal movement set (Algorithm 3) and is only randomized on ties, reporting the minimum plausibly favors the random MinPath baseline, making the comparison conservative. Furthermore, MinPath is an author-constructed representative rather than a published prior mapper: Section VII concedes that comparison with prior works is future work, so the abstract's phrase 'a prior mapping strategy' overstates the external validity of the comparison. I recommend either benchmarking against at least one published mapper (e.g., a Qiskit/OpenPulse-style flow or the mapper of Ref. [17]) on the same benchmark set, or explicitly presenting MinPath as an ablation baseline and adjusting the claims and abstract accordingly.
  3. [§II.D, §III.B] Sections II.D and III.B define the scheduler's resource model entirely through the configuration tables Tg1, Tgm, Tg2f, and Tg2d, but the paper lists only their sizes (|Tg1|=3, |Tgm|=3, |Tg2f|=48, |Tg2d|=48) and neither includes the tables nor states where the configuration file can be obtained. Because the validity of the scheduled circuits on actual Surface-17 hardware — and hence the correctness of the comparison in Table IV — depends on these tables faithfully capturing the classical-control restrictions (e.g., the detuning rules from Ref. [27]), the omission makes the central modeling contribution unverifiable and the experiments non-reproducible. Please include the full configuration file as supplementary material (or specify all 48-entry tables in the paper) and indicate where the Qmap implementation can be obtained.
minor comments (6)
  1. [§I] In Section I, final bullet, 'respectivel' should read 'respectively'.
  2. [§V.C] Benchmark names are used inconsistently ('gray6 47', 'decod24 b', 'bestein vazirani') relative to the names in Table II ('graycode647', 'decod24bdd', 'bensteinvazirani16'); please use consistent labels throughout.
  3. [§V.D] Section V.D states 'the two-qubit gate number from 5 to 62483', but Table II's largest two-qubit-gate count is 28084 and its largest total gate count is 64283; 62483 matches neither and appears to be a typo.
  4. [Tables II and IV] In the version of the manuscript I reviewed, the table columns run together (e.g., 'alu bdd 288 7 84 38 48 169' and entries such as '0.06365286'), making several rows unreadable; please ensure the published tables have clearly separated columns and unambiguous cell boundaries.
  5. [§IV.C, §V.B] The notation 'O(g√n4√n)' is ambiguous; it should be typeset as O(g·√n·4^√n) (or equivalent) to make the sub-exponential dependence on the qubit count clear.
  6. [§V.C] The statement that MinPath 'can reduce the latency overhead and gate overhead up to 140% and 360%' is ambiguous, since an overhead reduction is itself a percentage; the authors should define whether this is a relative reduction of the overhead values or a percentage-point difference, and give the corresponding formula.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity found: Qmap's reported reductions are measured on external benchmarks against a stated baseline, with no fitted parameter renamed as a prediction.

full rationale

Qmap is evaluated by compiling 56 benchmarks from RevLib and QLib onto a fixed hardware model and comparing latency and gate overheads against two baselines (Trivial and MinPath) described and implemented in the paper itself. The reported reductions (up to 47.3% latency and 28.6% gates) are measurements on external circuits, not values fitted into the mapper. The scheduler (Algorithm 1) and router (Algorithms 2 and 3) are constructive heuristics whose objective of minimizing latency is stated before the experiments rather than derived from the experimental outcomes. MinPath is defined as a baseline that minimizes operation counts and selects a random shortest movement set (Section V.B), while Qmap is defined to evaluate multiple movement sets with a resource-constrained lookback (Algorithms 2 and 3); the comparison therefore tests a design choice rather than reducing one quantity to another by construction. The paper's self-citations, such as the OpenQL compiler [28] and the ILP placement method [38], are instrumental, and the shared ILP-based placement between Qmap and MinPath isolates the router contribution. The MOVE precondition that destinations must be in the |0> state (Section II.A) is a possible correctness gap if the resource model does not track that condition, but a correctness risk is not a circular-definition risk. No fitted parameter is renamed as a prediction, and no uniqueness theorem or ansatz is imported from the authors' prior work to force the result. The central claim is self-contained against the external benchmarks and the stated configuration model, so no significant circularity is present.

Assumptions & free parameters 0 free parameters · 4 assumptions · 0 invented entities

No free parameters are fitted to data; all gate durations and constraint tables are inputs from cited hardware sources or the authors' modeling choices. The only ad hoc element is the self-defined MinPath baseline, which is an assumption about external validity rather than a fitted parameter.

assumptions (4)
  • domain assumption Gate durations and primitive gate set for Surface-17 (Table I: single-qubit gates 1 cycle, CZ 2 cycles, measurement 15 cycles).
    Taken from cited hardware papers [31] and [27]. If the actual durations differ, the latency comparisons change, though the algorithm itself is duration-agnostic.
  • domain assumption Same-frequency qubits are operated by the same microwave source or AWG, so different single-qubit gates on same-frequency qubits cannot run concurrently; measurement on the same feedline serializes; CZ gates have the detuning rules described in Section II.C.
    The paper states 'we assume that same-frequency qubits are operated by the same microwave source or arbitrary waveform generator' (Section II.C.a). These shared-control constraints are the central new modeling element and are not independently verified in the paper.
  • domain assumption A MOVE operation requires the destination qubit to be in state |0>, and ancilla qubits are available for current benchmarks.
    Section II.B and IV.E state that MOVE uses two CNOTs and requires a |0> ancilla. The benchmark evaluation assumes such ancillas exist for circuits with fewer than 17 active qubits.
  • ad hoc to paper The MinPath mapper is a fair representative of prior operation-count-minimizing mappers.
    MinPath is implemented by the authors with random movement-set selection (Section V.B). If actual prior mappers route more cleverly, the headline improvement over prior art is overstated.

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Cite this review

Pith. "Pith review of Timing and resource-aware mapping of quantum circuits to superconducting processors." pith.science (2026). https://pith.science/paper/QQCMKY5T

@misc{pith2026190804226,
  author       = {Pith},
  title        = {Pith review of: Timing and resource-aware mapping of quantum circuits to superconducting processors},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/QQCMKY5T}},
  note         = {Machine review of arXiv:1908.04226}
}
read the original abstract

Quantum algorithms need to be compiled to respect the constraints imposed by quantum processors, which is known as the mapping problem. The mapping procedure will result in an increase of the number of gates and of the circuit latency, decreasing the algorithm's success rate. It is crucial to minimize mapping overhead, especially for Noisy Intermediate-Scale Quantum (NISQ) processors that have relatively short qubit coherence times and high gate error rates. Most of prior mapping algorithms have only considered constraints such as the primitive gate set and qubit connectivity, but the actual gate duration and the restrictions imposed by the use of shared classical control electronics have not been taken into account. In this paper, we present a timing and resource-aware mapper called Qmap to make quantum circuits executable on a scalable superconducting processor named Surface-17 with the objective of achieving the shortest circuit latency. In particular, we propose an approach to formulate the classical control restrictions as resource constraints in a conventional list scheduler with polynomial complexity. Furthermore, we implement a routing heuristic to cope with the connectivity limitation. This router finds a set of movement operations that minimally extends circuit latency. To analyze the mapping overhead and evaluate the performance of different mappers, we map 56 quantum benchmarks onto Surface-17. Compared to a prior mapping strategy that minimizes the number of operations, Qmap can reduce the latency overhead up to 47.3% and operation overhead up to 28.6%, respectively.

Figures

Figures reproduced from arXiv: 1908.04226 by the authors.

Figure 2
Figure 2. FIG. 2: Schematic of the realization of Surface-17 [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 1
Figure 1. FIG. 1: Gate decomposition into primitives supported [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 3
Figure 3. FIG. 3: An example circuit consisting of 6 qubits and [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figures from the paper (3 more)
Figure 4
Figure 4. Figure 4: FIG. 4: (a) The QODG of the circuit in Figure [PITH_FULL_IMAGE:figures/full_fig_p005_4.png]
Figure 6
Figure 6. Figure 6: FIG. 6: Comparison of three different mapping strategies. Overhead reduction (left) when comparing the MinPath [PITH_FULL_IMAGE:figures/full_fig_p011_6.png]
Figure 7
Figure 7. Figure 7: FIG. 7: Reduction of mapping overhead when using [PITH_FULL_IMAGE:figures/full_fig_p011_7.png]

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Pith tools

Reviewed August 14, 2026 · model on record in the stance chip above.