Typed states for the displayed outbound observations.
Source: paper_references, paper_reference_links
Paper Citation Record · LEDGER
SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model
As of 10 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 9 inbound Pith citation observations for arXiv:2401.13266.
A citation records a reference. It does not transfer a finding from one paper to another.
Coverage vector
One-hop event checks from named stored sources.
Source: scholarly_work_events, retraction_status_cache, observed 2026-08-10T06:31:04.303077+00:00
Pith citing papers itemized under the disclosed page cap.
Source: paper_references, paper_reference_links, observed 2026-08-10T19:49:55.566058Z
A source-named dated measurement, never combined with another source.
Source: arxiv_reference, observed 2026-08-05T02:28:24.338817Z
Reference resolution
0 of 0 outbound references displayed
- verified exact0
- verified fuzzy0
- unresolved0
- parse uncertain0
- malformed identifier0
- metadata mismatch0
External citation measurements
5
arxiv_reference, observed 2026-08-05T02:28:24.338817Z
Outbound references
No outbound reference observations are available for this paper version.
Pith citing papers
Observation 1a6ca73d-692e-402d-9b5d-0c838d012056 · inbound
A Survey of Research in Large Language Models for Electronic Design Automation cites this paper.
A Survey of Research in Large Language Models for Electronic Design Automation SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model
Reference 30
- Resolution
- unresolved
- no resolver link, observed 2026-08-10T19:49:55.566058Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation f3518713-0b75-41d6-beb7-44d8462a8943 · inbound
Formalising Software Requirements using Large Language Models cites this paper.
Formalising Software Requirements using Large Language Models SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model
Reference 5
- Resolution
- unresolved
- no resolver link, observed 2026-08-07T04:22:32.613138Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation c9fa1f2e-44ac-4154-bbe5-1d0e6de4cad4 · inbound
A Short Survey on Formalising Software Requirements using Large Language Models cites this paper.
A Short Survey on Formalising Software Requirements using Large Language Models SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model
Reference 31
- Resolution
- unresolved
- no resolver link, observed 2026-08-07T01:07:24.956619Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation b9e46e6b-7bf5-4ef9-be8d-58ab5fefd76e · inbound
Leveraging LLMs for Formal Software Requirements -- Challenges and Prospects cites this paper.
Leveraging LLMs for Formal Software Requirements -- Challenges and Prospects SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model
Reference 13
- Resolution
- unresolved
- no resolver link, observed 2026-08-06T16:13:49.973658Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 164bc178-8406-4244-9429-7df1ac1ac970 · inbound
RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs cites this paper.
RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model
Reference 30
- Resolution
- unresolved
- no resolver link, observed 2026-08-06T15:19:54.115981Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 62f78b1b-3687-4026-904d-f8a4ae094aaf · inbound
Automated HEMT Model Construction from Datasheets via Multi-Modal Intelligence and Prior-Knowledge-Free Optimization cites this paper.
Automated HEMT Model Construction from Datasheets via Multi-Modal Intelligence and Prior-Knowledge-Free Optimization SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model
Reference 18
- Resolution
- unresolved
- no resolver link, observed 2026-08-06T12:53:06.725231Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 197f657e-322d-4e91-913b-a165b5aec7a0 · inbound
DiffAxE: Diffusion-driven Hardware Accelerator Generation and Design Space Exploration cites this paper.
DiffAxE: Diffusion-driven Hardware Accelerator Generation and Design Space Exploration SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model
Reference 26
- Resolution
- unresolved
- no resolver link, observed 2026-08-05T20:33:59.940074Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 59cc461e-139d-4582-a677-eb7db571b308 · inbound
Large Language Models (LLMs) for Electronic Design Automation (EDA) cites this paper.
Large Language Models (LLMs) for Electronic Design Automation (EDA) SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model
Reference 7
- Resolution
- unresolved
- no resolver link, observed 2026-08-05T15:17:26.438693Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 749477e9-977e-4387-978c-84af094509b0 · inbound
Closing the Loop on LLM-Generated RTL Assertions with Quality-Aware Formal Verification cites this paper.
Closing the Loop on LLM-Generated RTL Assertions with Quality-Aware Formal Verification SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model
Reference 1
- Resolution
- verified exact
- arxiv_id, observed 2026-06-26T12:59:29.729262Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.