Pith. sign in

Paper Citation Record · LEDGER

HDLdebugger: Streamlining HDL debugging with Large Language Models

As of 9 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 8 inbound Pith citation observations for arXiv:2403.11671.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2403.11671 v1

Coverage vector

measured 0 of 0 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links

measured 8 of 8 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-09T06:31:02.800959+00:00

measured 8 of 8 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-07T14:11:57.275703Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: arxiv_reference, observed 2026-06-29T18:53:51.249643Z

Reference resolution

0 of 0 outbound references displayed

  • verified exact0
  • verified fuzzy0
  • unresolved0
  • parse uncertain0
  • malformed identifier0
  • metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

No outbound reference observations are available for this paper version.

Pith citing papers

Observation 8aa321b0-182e-4229-be0a-99dba0eb4ebf · inbound

From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification cites this paper.

From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification HDLdebugger: Streamlining HDL debugging with Large Language Models

Reference 31

Resolution
verified exact
arxiv_id, observed 2026-05-22T18:01:54.489794Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

source=pdf_text observed=2026-05-22T17:58:45.319714Z digest=sha256:e585dd8bde310c4b2fb30a0983072e918874d55a925c19ba7a9980929e41d147

Observation 92678aa1-b9ed-472e-8007-06f4deb640b1 · inbound

ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection cites this paper.

ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection HDLdebugger: Streamlining HDL debugging with Large Language Models

Reference 33

Resolution
unresolved
no resolver link, observed 2026-08-07T14:11:57.275703Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-07T14:11:57.275703Z digest=sha256:39ca60a546511f919fd15f7b716844176d33f1b04c24366f8aca67db42696062

Observation 7d801361-ec76-4f30-beaf-ac4523e28112 · inbound

SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models cites this paper.

SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models HDLdebugger: Streamlining HDL debugging with Large Language Models

Reference 72

Resolution
unresolved
no resolver link, observed 2026-08-06T22:55:09.351544Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-06T22:55:09.351544Z digest=sha256:8593035c333339cc6767bdf499c7d4ce0fec85c1b237f6a548ee6809faee354d

Observation 8401bb39-20f6-4c61-9cda-33d689e90ab2 · inbound

ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning cites this paper.

ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning HDLdebugger: Streamlining HDL debugging with Large Language Models

Reference 30

Resolution
verified exact
arxiv_id, observed 2026-05-19T06:52:08.251970Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

source=pdf_text observed=2026-05-19T06:48:29.015759Z digest=sha256:b811d2c0962b3e01ecf3ba1b5c83c9760c5a36d40abd0ac6e07831f41def5855

Observation 77b36558-44ef-4312-80e1-243e94660b8f · inbound

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs cites this paper.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs HDLdebugger: Streamlining HDL debugging with Large Language Models

Reference 21

Resolution
unresolved
no resolver link, observed 2026-08-06T15:19:53.469553Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-06T15:19:53.469553Z digest=sha256:c1a54fce31b95bec44ebb6d83c21c870291bc180ed4d61f53d1c332b1f0a4960

Observation 4e03cc3f-6a8a-481c-aa5d-05f889901df3 · inbound

HLSDebugger: Identification and Correction of Logic Bugs in HLS Code with LLM Solutions cites this paper.

HLSDebugger: Identification and Correction of Logic Bugs in HLS Code with LLM Solutions HDLdebugger: Streamlining HDL debugging with Large Language Models

Reference 9

Resolution
unresolved
no resolver link, observed 2026-08-06T12:46:40.775559Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-06T12:46:40.775559Z digest=sha256:a665098098b9c2c54ebd8ad66ae24f884068faf29a7c52d8a2b1c212819901ff

Observation a19b3676-e523-469e-b58d-daf5829a4a36 · inbound

Can Agents Secure Hardware? Evaluating Agentic LLM-Driven Obfuscation for IP Protection cites this paper.

Can Agents Secure Hardware? Evaluating Agentic LLM-Driven Obfuscation for IP Protection HDLdebugger: Streamlining HDL debugging with Large Language Models

Reference 10

Resolution
verified exact
arxiv_id, observed 2026-05-10T14:40:32.672677Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

source=pdf_text observed=2026-05-10T14:39:02.174611Z digest=sha256:3baefbf2d91b3a8a22d68a71ee5931be00ec2a03904e6aa4350062af0aaf0752

Observation d29dd144-f887-4dd8-bc2f-4e4ad8d163e9 · inbound

Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation cites this paper.

Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation HDLdebugger: Streamlining HDL debugging with Large Language Models

Reference 14

Resolution
verified exact
arxiv_id, observed 2026-06-29T18:53:51.251685Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.

source=pdf_text observed=2026-06-29T18:49:52.243940Z digest=sha256:0fc6f057d0b6bf2dca7613ddf8cc96cbc25c1a95be56118161903f56f8a17551