Pith. sign in

REVIEW 2 major objections 5 minor 33 references

A reconfigurable calibration-free digital-to-time converter based on a high-speed transceiver

T0 review · 2 major / 5 minor · reviewed 2026-08-11 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗ Review JSON

Pith's one-line read An FPGA's high-speed transceiver can act as a calibration-free digital-to-time converter with 100 ps resolution.

desk verdict Clever repurposing of an FPGA GTX transceiver as a DTC, but the headline linearity numbers come from the digital frame, not the physical output edges. read the letter →

arxiv 2412.06330 v2 pith:RW6LMSP6 submitted 2024-12-09 eess.SP

Dexuan Kong , Zaiming Fu , Yujie Deng , Ruiqi Wang This is my paper · ORCID
classification eess.SP
keywords digital-to-timeconverterhigh-speedtransceiverFPGAtimingsignalgenerationcalibration-freepulsegeneratorreal-timeencodingtimeinterval
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper claims that an FPGA's high-speed transceiver can serve as a calibration-free digital-to-time converter with 100 ps resolution, a dynamic range from 1 ns to 40 µs, and linearity of about 0.02-0.04 LSB. The key idea is to encode each desired time interval as a number of consecutive 1s in a parallel data frame, serialize that frame at 10 Gbps, and let the output pulse width equal the 1-count times the 100 ps bit period. A real-time encoding scheme stitches intervals across 32-bit frames, so arbitrary-length sequences and random intervals can be produced without large memory tables. On the tested FPGA the authors report sub-3 ps standard deviation across the full range and both sequence and random-signal output modes. If this holds, it gives a simple, reconfigurable DTC that avoids the calibration burden of delay-line designs.

What carries the argument

The load-bearing mechanism is the real-time frame encoder feeding the FPGA's GTX, a high-speed serial transceiver. Each timing parameter Ti is turned into Ti/100 ps consecutive 1s; because the serializer emits one bit every 100 ps at 10 Gbps, the high level duration equals the 1-count times 100 ps. To handle intervals longer than 32 bits or starting mid-frame, the encoder splits each 32-bit output into Part1 (high bits, current interval) and Part2 (low bits, next interval), and the decode pseudocode (Fig. 6) selects among three cases: the frame completes the interval exactly, the interval overflows the frame, or the frame has spare bits, in which case the remainder is carried into Part2. The transceiver's serializer then outputs the frame unchanged (8B/10B bypassed), so the encoded 1-run becomes the pulse width.

What would settle it

Measure the output pulse width for every 32-bit frame (or a dense subset covering run lengths from 1 to 32 and all transition positions) with a reference time base whose jitter is below 1 ps, and check whether any width deviates from the integer-multiple prediction by more than the claimed sub-3 ps precision; a single pattern-dependent deviation above that bound would falsify the calibration-free claim.

Watch

Extended reading notes

Core claim

The central claim is that a standard high-speed serializer with 8B/10B encoding disabled can synthesize timing signals directly: the output pulse's high time is the number of consecutive 1s times the 100 ps serial bit period. The paper's real-time decoding algorithm converts time parameters into 32-bit frames composed of a Part1 field (current interval) and a Part2 field (next interval) whose valid bit widths always sum to 32, so the bitstream never pauses and no deep memory is needed. The authors measure a 10 Gbps transceiver implementation and obtain 100 ps resolution, 1.0179 ns to 40.000109 µs range, DNL between -0.02 and 0.02 LSB, INL between -0.04 and 0.03 LSB, and a standard deviation below 3 ps. They also demonstrate two output modes: a timing sequence with user-defined variable intervals and a random timing signal whose intervals are uniformly distributed.

Load-bearing premise

The entire accuracy depends on the assumption that the serializer reproduces the encoded run of 1s with negligible pattern-dependent jitter and that the reference clock's jitter is low enough that the pulse width is exactly the number of 1s times 100 ps; the paper asserts this via clock stability but does not decompose jitter sources.

Editorial extensions

If this is right

  • The same encoding scheme should scale to faster transceivers: a 25 Gbps link would give 40 ps resolution with the same architecture and no calibration.
  • Because the time base is the serial clock rather than a delay chain, temperature and voltage drift affect only the clock frequency, which can be disciplined, instead of each tap's delay.
  • The 32-bit frame plus 10 Gbps bit rate bounds the maximum single-frame interval at 3.2 ns; the encoding's carry mechanism is what extends the range to 40 µs, so wider frames or faster clocks would extend the range further.
  • The random-interval output, based on multiple m sequences read in parallel, gives a uniform distribution that is directly useful for dithering in power converters and motor drives.
  • The resource cost is small (about 5,000 flip-flops plus one transceiver), so the DTC can be embedded in a larger FPGA design without a separate timing chip.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • An unstated sensitivity is pattern-dependent jitter in the serializer: run lengths and transition density vary from frame to frame, and the reported <3 ps precision may not be uniform across all 32-bit patterns; measuring every possible frame's width would test this.
  • The architecture is essentially a pulse-density modulation at 10 Gbps, so low-pass filtering the output could extend the DTC into an arbitrary waveform generator, a direction the authors do not explore.
  • The claimed 'calibration-free' property rests on the transceiver's clock stability; if a lower-cost FPGA with a noisier PLL is used, the same encoding would likely show worse INL, meaning the method transfers the calibration burden from delay taps to the clock source.
  • The uniform-random certification is only statistical; a longer capture and a chi-square or spectral test would be needed to verify the m-sequence combination's randomness, especially because the period of the combined sequence is the product of 12 maximal-length sequences, which may still produce detectable periodicities.
Share X Bluesky LinkedIn Reddit HN

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

2 major / 5 minor

Summary. The paper proposes a digital-to-time converter (DTC) implemented with a Xilinx Kintex-7 GTP/GTX-class high-speed transceiver. Time information is encoded in real time into 32-bit parallel data frames whose run of 1-bits determines the output pulse width after serialization at 10 Gbps, giving a nominal 100 ps resolution. The design also supports timing-sequence and random-interval outputs via a phase accumulator and multiple LFSRs. Experimental results report a minimum interval of 1.0179 ns, a maximum interval of 40.000109 µs, a <3 ps standard deviation at those endpoints, a 100 ps resolution step, and DNL/INL of -0.02/0.02 LSB and -0.04/0.03 LSB, respectively. The paper claims calibration-free operation and variable resolution through clock reconfiguration.

Significance. If the central claims hold, the paper offers an unusually simple and attractive DTC architecture: the output time interval is defined directly by the serialized bit pattern, with no fitted parameters, no lookup-table calibration, and no analog delay-line tuning. The measured oscilloscope traces are consistent with the claimed resolution and endpoint behavior, and the real-time encoding strategy is clever for avoiding large on-chip memories. The main significance would be a low-resource FPGA DTC with a very wide dynamic range and good linearity. However, the headline linearity and precision numbers are currently supported only by data-frame simulations and two endpoint measurements, not by physical output-edge characterization across the range, so the significance is not yet established at the claimed level.

major comments (2)
  1. [Section 3, Fig. 12] The DNL/INL values quoted in the abstract and conclusion (-0.02/0.02 LSB and -0.04/0.03 LSB) are measured on the 32-bit data frame, not on the physical output timing edges, as the text explicitly states: "We tested the INL and DNL of the data frame." The linearity of the frame composition logic is a property of digital arithmetic and is not the same as the linearity of the realized pulse widths, because the serializer bit positions, pattern-dependent jitter, output-driver duty-cycle distortion, and clock path can all add code-dependent timing errors. This gap is load-bearing: the claim that these values hold "across the entire range" is not supported by the measurements shown. The authors should measure DNL/INL on the actual output pulse widths (e.g., by time-interval measurements over a dense set of codes spanning 1 ns to 40 µs) and report those results as the DTC linearity.
  2. [Section 3, Figs. 9 and 10] The precision claim of "standard deviation less than 3 ps" over the entire dynamic range is supported only by two static measurements at 1.0179 ns and 40.000109 µs. In a serializer-based DTC, output jitter and timing error can be pattern-dependent and code-dependent, because different codes produce different bit patterns and different transition positions in the serial stream. Two endpoints do not establish consistency across the full range. Please provide precision/jitter measurements at several intermediate code values and describe the acquisition procedure (number of samples, measurement method), or restrict the claim to the measured endpoints.
minor comments (5)
  1. [Abstract and Section 3] The phrase "across the entire range" is used in the abstract and in Table 2's comparison, but the supporting measurement (Fig. 12) is explicitly a data-frame test. Consider rewording to avoid confusing digital-frame linearity with analog-output linearity until the physical-edge measurements are available.
  2. [Section 3, Fig. 14] The claim that the random timing signal obeys a uniform distribution is not quantified; provide a histogram of the measured intervals, the sample size, and a statistical test (e.g., chi-square) rather than only a label on the oscilloscope trace.
  3. [Section 3, Fig. 13] The timing-sequence demonstration shows a repeating nine-pulse pattern, but no expected-versus-measured interval table is given. Adding quantitative values would strengthen the multifunctionality claim.
  4. [Section 2.3] The sentence "To keep the data original, the 8B/10B encoding function will not be used" should explain how this is configured in the transceiver and whether disabling 8B/10B affects transmitter constraints such as DC balance or run-length limits.
  5. [Title] There is a typo in the title: "conver ter" should be "converter."

Circularity Check

1 steps flagged · score 6.0 of 10

Headline DNL/INL figures are measured on the digital data frame, whose time value is defined by the one-bit count; the claimed transfer to physical DTC linearity is self-definitional.

  1. self definitional [Section 2.2 (Data encoding) and Section 3 (Experiment and result), Fig. 12]
    "Each time parameter represents the time interval of the DTC output, which is the number of 1s in the high-speed serial data. ... The synthesis of the 32-bit data frame is at the heart of timing signal synthesis, and its nonlinear performance is representative of DTC performance over the entire dynamic range. We tested the INL and DNL of the data frame."

    The output time interval is defined as the number of 1-bits in the serial data, so the INL/DNL of the data frame is exactly the linearity of the encoding arithmetic used to place those 1-bits. That arithmetic is a digital count and is exact by construction; it says nothing about the physical pulse widths produced by the GTX serializer, pattern-dependent jitter, output-driver duty-cycle distortion, or reference-clock jitter. Presenting the frame-level result as 'representative of DTC performance over the entire dynamic range' substitutes the definition of the time code for a measurement of the physical output.

full rationale

The core architecture is otherwise self-contained: the output pulse is simply the serialized bit pattern, so the 100 ps resolution follows directly from the 10 Gbps line rate, and the endpoint precision values come from external oscilloscope measurements, which are legitimate independent evidence. There is no self-citation chain, no fitted parameter, and no imported uniqueness theorem. The single circular step is the derivation of the headline DNL/INL: the paper defines the output time interval as the number of 1-bits, then reports the INL/DNL of the 32-bit data frame as the nonlinearity of the DTC. Because the frame's linearity is the linearity of that digital count by construction, it cannot validate the physical pulse-width linearity that the abstract claims. This makes a central quantitative claim partially reduce to its own input definition, so a non-trivial circularity score is appropriate; the independent physical precision measurements keep the paper from an 8 or 10.

Assumptions & free parameters 0 free parameters · 4 assumptions · 0 invented entities

No novel entities are introduced. The design parameters D, K, and the 10 Gbps clock rate are user or config choices, not fitted. The analysis assumes transceiver clock stability, encoder timing closure, oscilloscope measurement accuracy, and LFSR randomness properties.

assumptions (4)
  • domain assumption The high-speed transceiver's serializer output bit period is a stable 100 ps and the reference clock path has low enough jitter that the synthesized signal achieves <3 ps precision without calibration.
    Invoked in the abstract and Sec. 2.3; no jitter budget or transceiver characterization is provided, so this is an unverified hardware assumption.
  • domain assumption The data encoding module can produce a new valid 32-bit frame every parallel clock cycle (312.5 MHz for 10 Gbps with 8B/10B disabled), including the split/splice logic in Fig. 6, without timing closure violations.
    Load-bearing for continuous timing streams; the paper reports no maximum clock frequency or timing analysis for the encoder.
  • domain assumption The 13 GHz/40 GSPS oscilloscope measurements accurately capture 100 ps transitions with measurement noise below the claimed <3 ps jitter and 0.05 LSB nonlinearity.
    Used for all reported precision and INL/DNL numbers; no measurement uncertainty analysis is given.
  • standard math The 12 m-sequences with different primitive polynomials produce uncorrelated bits so that the 12-bit pseudo-random numbers are uniform over the intended range.
    Standard LFSR theory (Eqs. 2-4); periodic, and the paper shows only a histogram, no statistical test.

how reviews work

0 comments
Cite this review

Pith. "Pith review of A reconfigurable calibration-free digital-to-time converter based on a high-speed transceiver." pith.science (2026). https://pith.science/paper/RW6LMSP6

@misc{pith2026241206330,
  author       = {Pith},
  title        = {Pith review of: A reconfigurable calibration-free digital-to-time converter based on a high-speed transceiver},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/RW6LMSP6}},
  note         = {Machine review of arXiv:2412.06330}
}
read the original abstract

This paper proposes a high-speed transceiver-based method for implementing a digital-to-time converter (DTC). A real-time decoding technique is introduced to inject time information into high-speed pattern data. The stability of the high-speed clock ensures the high precision of the synthesized timing signal without the need for calibration. The reconfigurability of the clock resources provides the DTC with variable resolution and enhanced flexibility for various applications. Based on this approach, a multifunctional DTC is designed to offer both timing sequence and random timing signal functionalities, catering to a wide range of application scenarios. The timing sequence function generates a continuously variable timing signal stream, while the random timing signal function produces random signals with uniformly distributed time intervals. Experimental results, using a Xilinx Kintex-7 FPGA, validate the effectiveness of the proposed methodology. The system achieves a resolution of 100 ps, a dynamic range from 1 ns to 40 {\mu}s, a DNL of -0.02/0.02 LSB, an INL of -0.04/0.03 LSB across the entire range. This approach can be readily adapted to various high-precision timing signal applications.

Figures

Figures reproduced from arXiv: 2412.06330 by the authors.

Figure 1
Figure 1. Overall structure of the proposed DTC. 2 [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Structure of Sequences Generator By serializing these single timing signals, a sequence with fixed timing intervals can be created. This DTC supports sequences containing 2 to 1000 fixed intervals. Additionally, automated test equipment often requires timing signals with varying intervals, known as timing sequences. To generate these, the DTC employs a sequence generator module, which determines the timing parameter… view at source ↗
Figure 3
Figure 3. Structure of an n-level LFSR. The relationship between L (the length of the individual signals in the output timing sequences) and fs (the clock frequency) is expressed by Eq.(1). L = 2 D K · fs . (1) Varying the frequency control word K can change the length of the individual signals in the timing sequences of the output signal. Timing signal with random timing intervals are critical in controlling switching power … view at source ↗
Figures from the paper (11 more)
Figure 4
Figure 4. Figure 4: Data frame structure 4 [PITH_FULL_IMAGE:figures/full_fig_p004_4.png]
Figure 5
Figure 5. Figure 5: Flowchart of data frame compositing [PITH_FULL_IMAGE:figures/full_fig_p005_5.png]
Figure 6
Figure 6. Figure 6: Pseudocode of timing parameter decoding. [PITH_FULL_IMAGE:figures/full_fig_p005_6.png]
Figure 7
Figure 7. Figure 7: Structure of SerDes Module. The structure of the SerDes module in the FPGA is shown in Fig.7. The SerDes module structure includes two channels: the transmit line (TX Line) and the receive line (RX Line). The main thing used in this DTC device is the TX line. The paral…
Figure 8
Figure 8. Figure 8: Photograph of the experimental platform. (a) PCB. (b) [PITH_FULL_IMAGE:figures/full_fig_p006_8.png]
Figure 9
Figure 9. Figure 9: Minimum timing interval test chart. 40.000109 s [PITH_FULL_IMAGE:figures/full_fig_p007_9.png]
Figure 10
Figure 10. Figure 10: Maxmum timing interval test chart. Δ x = 10×100 ps = 1 ns [PITH_FULL_IMAGE:figures/full_fig_p007_10.png]
Figure 11
Figure 11. Figure 11: Timing resolution test chart. 7 [PITH_FULL_IMAGE:figures/full_fig_p007_11.png]
Figure 12
Figure 12. Figure 12: Nonlinearity test chart of data frame. performance, the precision of the time signal has good consistency over the entire dynamic range, with a standard deviation of less than 3 ps. Fig.11 shows the timing signal resolution reaching 100 ps. The synthesis of the 32-bit…
Figure 13
Figure 13. Figure 13: shows the sequence generation function, demonstrating two sequence cycles. The sequence increases in pulse width with time, with nine timing signal as the cycle. Users can adjust the number of timing signal and interval according to their needs. After sampling 1 M ran…
Figure 14
Figure 14. Figure 14: Random timing signal test chart. 4 Conclusion This paper presents a novel DTC leveraging FPGA high-speed transceivers for high-precision timing signal synthesis. The design achieves an INL of [-0.04, 0.03] LSB and a DNL of [-0.02, 0.02] LSB. A real-time encoding schem…

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

33 extracted references · 17 canonical work pages

  1. [1]

    Microwave The- ory Tech

    Tseng, Shao-Ting, et al .: ”Equivalent-time direct-sampling impulse-radio radar with rotatab le cyclic vernier digital-to-time converter for wireless sensor network loca lization.” IEEE Trans. Microwave The- ory Tech. 66.1 (2017) 485-508 (DOI:10.1109/TMTT.2017.2718510)

    arXiv 2017

  2. [2]

    Solid-State Circuits 50.11 (2015) 2665-2677 (DOI: 10.1109/JSSC.2015.2472599)

    Kao, Yu-Hsien, and Ta-Shun Chu: ”A direct-sampling pulsed time- of-flight radar with frequency-defined vernier digital-to-time converter in 65 nm CMOS.” IEEE J. Solid-State Circuits 50.11 (2015) 2665-2677 (DOI: 10.1109/JSSC.2015.2472599)

    work page arXiv 2015

  3. [3]

    Selection of Amplifier for Optimized Charge Transfer in Active Pixel CMOS Time of Flight (TOF) Image Sensors

    Halin, Izhal Abdul, et al .: “Selection of Amplifier for Optimized Charge Transfer in Active Pixel CMOS Time of Flight (TOF) Image Sensors.” IEICE Electron. Express 8.22 (2011) 1913–19 (DOI: doi.org/10.1587/elex.8.1913.)

    work page doi:10.1587/elex.8.1913 2011

  4. [4]

    Express 20.13 (2023) 20230133 (DOI: 10.1587/elex.20.20230133)

    Uehara, Tomoyuki, et al .: ”Calibration on X-band radar ranging with laser lidar.” IEICE Electro n. Express 20.13 (2023) 20230133 (DOI: 10.1587/elex.20.20230133)

    work page doi:10.1587/elex.20.20230133 2023

  5. [5]

    An ULP Capacitor-DAC-Based Constant-Slope Digital-to-Time Co nverter

    Rashed, Kareem, et al .: “An ULP Capacitor-DAC-Based Constant-Slope Digital-to-Time Co nverter.” Proc. Int. Conf. Microelectron. ICM (2020) 1–4. (DOI: 10.1109/ ICM50269.2020.9331506)

    arXiv 2020

  6. [6]

    A Neural Stimulator Frontend With High-Voltage Compliance and Pr o- grammable Pulse Shape for Epiretinal Implants

    Noorsal, Emilia, et al .: “A Neural Stimulator Frontend With High-Voltage Compliance and Pr o- grammable Pulse Shape for Epiretinal Implants.” IEEE J. Solid-State Circuits 47.1 (2012) 244–56 (DOI: 10.1109/JSSC.2011.2164667)

    arXiv 2012

  7. [7]

    Solid-State Circuits 55.7 (2020) 1830-1841 (DOI: 10.1109/ESS- CIRC.2019.8902912)

    Madoglio, Paolo, et al .: ”A cellular multiband DTC-based digital polar transmitter with- 153- dBc/Hz noise in 14-nm FinFET.” IEEE J. Solid-State Circuits 55.7 (2020) 1830-1841 (DOI: 10.1109/ESS- CIRC.2019.8902912)

    arXiv 2020

  8. [8]

    Solid-State Circuits 55.12 (2020) 3414-3425 (DOI: 10.1109/JSSC.2020.3024973)

    Ben-Bassat, Assaf, et al .: ”A fully integrated 27-dBm dual-band all-digital polar transmitter s upport- ing 160 MHz for Wi-Fi 6 applications.” IEEE J. Solid-State Circuits 55.12 (2020) 3414-3425 (DOI: 10.1109/JSSC.2020.3024973)

    work page arXiv 2020

Show all 33 references
  1. [9]

    Overview of Sub-Terahertz Communication a nd 300GHz CMOS Transceivers

    Fujishima, Minoru: “Overview of Sub-Terahertz Communication a nd 300GHz CMOS Transceivers.” IEICE Electron. Express 18.8 (2021) 20212002 (DOI: 10.1587/elex.18.20212002). 9

    2021 doi

  2. [10]

    A Low Power All-Digital PLL With -40dBc In-Band Fractional Spur S uppression for NB-IoT Applications

    Yan, N., et al .: “A Low Power All-Digital PLL With -40dBc In-Band Fractional Spur S uppression for NB-IoT Applications.” IEEE Access 7 (2019) 7897–904 (DOI: 10.1109/ACCESS.2018.2890073)

    2019

  3. [11]

    Solid-State Circuits 54.11 (2019) 3149-3160 (DOI: 10.1109/CICC.2019.8780235)

    Santiccioli, Alessio, et al .: ”A 1.6-to-3.0-GHz Fractional- N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Powe r.” IEEE J. Solid-State Circuits 54.11 (2019) 3149-3160 (DOI: 10.1109/CICC.2019.8780235)

    2019

  4. [12]

    DTC Linearization via Mismatch-Noise Cancellation for Digital Fract ional-N PLLs

    Helal, Eslam, et al .: “DTC Linearization via Mismatch-Noise Cancellation for Digital Fract ional-N PLLs.” IEEE Trans. Circuits Syst. I 69.12 (2022) 4993–5006 (DOI: 10.1109/TCSI.2022.3200047)

    2022

  5. [13]

    A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an I nverse- Constant-Slope DTC and FCW Subtractive Dithering

    Dartizio, Simone M., et al.: “A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an I nverse- Constant-Slope DTC and FCW Subtractive Dithering.” IEEE J. Solid-S tate Circuits 58.12 (2023) 3320–37 (DOI: 10.1109/JSSC.2023.3311681)

    2023

  6. [14]

    A Low-Noise Fractional- N Digital Frequency Synthesizer With Imp licit Fre- quency Tripling for Mm-Wave Applications

    Zong, Zhirui, et al .: “A Low-Noise Fractional- N Digital Frequency Synthesizer With Imp licit Fre- quency Tripling for Mm-Wave Applications.” IEEE J. Solid-State Circuit s 54.3 (2019) 755–67 (DOI: 10.1109/JSSC.2018.2883397)

    2019

  7. [15]

    Observation of Parity-Time Symmetry Breaking in a Single-Spin Sys tem

    Wu, Yang, et al .: “Observation of Parity-Time Symmetry Breaking in a Single-Spin Sys tem.” Science, 364.6443, (2019) 878–80, (DOI: 10.1126/science.aaw8205)

    2019 doi

  8. [16]

    Multipartite Entanglement Among Single Spins in Diamond

    Neumann, P., et al .: “Multipartite Entanglement Among Single Spins in Diamond.” Science 320.5881, (2008) 1326–29 (DOI: 10.1126/science.1157233)

    2008 doi

  9. [17]

    Simultaneous Classical Co mmunication and Quantum Key Distribution Based on Gaussian Modulated Coherent States

    Kim, Youngjun, and Young-Chai Ko: “Simultaneous Classical Co mmunication and Quantum Key Distribution Based on Gaussian Modulated Coherent States.” IEICE Electron. Express 13.16 (2016) 20160680 (DOI: 10.1587/elex.13.20160680)

    2016 doi

  10. [18]

    Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-Nm CMO S

    Chen, Peng, et al .: “Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-Nm CMO S.” IEEE Trans. Circuits Syst. I 69.1 (2022) 196–206 (https://doi.org/10.1109/TCSI.2021.3105451)

    2022

  11. [19]

    A 10-Bit 563-Fs Step Constant-Slope Digital-to-Time Converter in 40-Nm CMOS With Nonlinearity Cancellation and Range Extension Techniques

    Liu, Yan, et al .: “A 10-Bit 563-Fs Step Constant-Slope Digital-to-Time Converter in 40-Nm CMOS With Nonlinearity Cancellation and Range Extension Techniques.” IEEE Trans. Circuits Syst. I, (2023) 1–11. (DOI: 10.1109/TCSI.2023.3323429)

    2023

  12. [20]

    A High-Linearity Digital-to-Time Converter Technique: Constant -Slope Charging

    Ru, Jiayoon Zhiyu, et al .: “A High-Linearity Digital-to-Time Converter Technique: Constant -Slope Charging.” IEEE J. Solid-State Circuits 50.6 (2015) 1412–23 (DOI: 10.1109/JSSC.2015.2414421)

    2015

  13. [21]

    A 31- u W, 148-Fs Step, 9-Bit Capacitor-DAC-Based Constant- Slope Digital- to-Time Converter in 28-nm CMOS

    Chen, Peng, et al .: “A 31- u W, 148-Fs Step, 9-Bit Capacitor-DAC-Based Constant- Slope Digital- to-Time Converter in 28-nm CMOS.” IEEE J. Solid-State Circuits 54.11 (2019) 3075–85 (DOI: 10.1109/JSSC.2019.2939663)

    2019

  14. [22]

    Design of Time Interval Generator Based on Hybrid Counting Met hod

    Yao, Yuan, et al .: “Design of Time Interval Generator Based on Hybrid Counting Met hod.” Nucl. Instrum. Methods Phys. Res., Sect. A 832 (2016) 103–07 (DOI: 10.1016/j.nima.2016.06.063)

    2016 doi

  15. [23]

    Eight-Channel Fully Adjustable Pulse Generator

    Miari, Luca, et al .: “Eight-Channel Fully Adjustable Pulse Generator.” IEEE Trans. I nstrum. Meas. 64.9 (2015) 2399–408 (DOI: 10.1109/TIM.2015.2408803)

    2015

  16. [24]

    A Simple Field Programmable Gate Array (FPGA) Based High Precision Low- Jitter Delay Generator

    Chen, Zeyang, et al .: “A Simple Field Programmable Gate Array (FPGA) Based High Precision Low- Jitter Delay Generator.” Rev. Sci. Instrum. 92.2 (2021) 024701. (DOI: 10.1063/5.0030341)

    2021 doi

  17. [25]

    High-Resolution Digital-to-Time Converter Implemented in an FPGA Chip

    Wang, H., et al .: “High-Resolution Digital-to-Time Converter Implemented in an FPGA Chip.” Appl. Sci. 7 (2017) 52. (DOI: 10.3390/app7010052)

    2017 doi

  18. [26]

    A High Resolution Vernier Digital-to-Time Converter Implemented w ith 65 Nm FPGA

    Yan, C., et al .: “A High Resolution Vernier Digital-to-Time Converter Implemented w ith 65 Nm FPGA.” Appl. Sci. 9 (2019) 2705 (DOI: 10.3390/app9132705)

    2019 doi

  19. [27]

    A High-Resolution Programmable Vernier Delay Generator Based o n Carry Chains in FPGA

    Cui, Ke, et al .: “A High-Resolution Programmable Vernier Delay Generator Based o n Carry Chains in FPGA.” Rev. Sci. Instrum. 88.6 June (2017) 064703 (DOI: 10.1063/1.4985542). 10

    2017 doi

  20. [28]

    Digital-to-Time Converter with P ulse Train Generation Capabil- ity

    Kwiatkowski, P., and R. Szplet: “Digital-to-Time Converter with P ulse Train Generation Capabil- ity.” I2MTC - IEEE Int. Instrum. Meas. Technol. Conf.: Discov. New Horizons in (2018) 1–6 (DOI: 10.1109/I2MTC.2018.8409538)

    2018

  21. [29]

    Digital-to-Time Converter for Test Equipment Implemented Using FPGA DSP Blocks

    Kwiatkowski, P: “Digital-to-Time Converter for Test Equipment Implemented Using FPGA DSP Blocks.” Measurement 177 (2021) 109267 (DOI: 10.1016/j.measurement.2021.109267)

    2021

  22. [30]

    A Pico-Second Resolution Arbitrary Timing Generator Based on Tim e Folding and Time Interpolating

    Qin, Xi, et al .: “A Pico-Second Resolution Arbitrary Timing Generator Based on Tim e Folding and Time Interpolating.” Rev. Sci. Instrum. 89.7 (2018) 074701 (DOI: 10.1063/1.5037841)

    2018 doi

  23. [31]

    A Field-Programmable-Gate-Array Based High Time Resolution Arb itrary Timing Generator with a Time Folding Method Utilizing Multiple Carry-Chains

    Wang, Lin, et al .: “A Field-Programmable-Gate-Array Based High Time Resolution Arb itrary Timing Generator with a Time Folding Method Utilizing Multiple Carry-Chains.” Re v. Sci. Instrum. 92.1 (2021) 014701 (DOI: 10.1063/5.0024594)

    2021 doi

  24. [32]

    Sharma, Ashok, et al.: ”Design and implementation of a re-configurable versatile direct dig ital synthesis- based pulse generator.” IEEE Trans. Instrum. Meas. 70 (2021) 1-14. (DOI: 10.1109/TIM.2021.3094240)

    2021

  25. [33]

    Zhang, Wen-Zhe, et al .: ”A fully-adjustable picosecond resolution arbitrary timing genera tor based on multi-stage time interpolation.” Rev. Sci. Instrum. 90.11 (2019) (DOI: 10.1063/1.5119148) 11

    2019 doi

Pith tools

Reviewed August 11, 2026 · model on record in the stance chip above.